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Jacob Potter 5b9b784b30 cm3: scb: add Cortex-M7 cache registers and bits 
Cortex-M7 supports a D-cache and I-cache on the AXI bus, controlled by these bits in SCB.
2021-02-03 22:17:21 +00:00
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libopencm3
cm3: scb: add Cortex-M7 cache registers and bits
2021-02-03 22:17:21 +00:00
libopencmsis
.gitignore: ignore autogenerated include/libopencmsis/swm050/
2019-06-17 22:34:15 +00:00