213a6b4244
* merged: nrf tree from unicore-mx * fixed: small changes to make merged code play with rest of locm3 again * added: linker script generator defines for nRF51/52 stubs * added: doxygen support This removes code and changes names and styles where relevant to be more inline with normal libopencm3. NRF52x library is built for hardfloat, M4F by default. The M4 no float variants are less common, and if needed, the library can be built manually for those variants. Unless some very common boards show up using those parts, we don't need an extra library build. Reviewed-by: Karl Palsson <karlp@tweak.net.au> Tested-by: Karl Palsson <karlp@tweak.net.au>
149 lines
6.1 KiB
C
149 lines
6.1 KiB
C
/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2017-2018 Unicore MX project<dev(at)lists(dot)unicore-mx(dot)org>
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* Copyright (C) 2021 Eduard Drusa <ventyl86(at)netkosice(dot)sk>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#pragma once
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/cm3/nvic.h>
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#include <libopencm3/nrf/memorymap.h>
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/* Common Peripheral Interface.
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* The implementation only applies to peripherals on APB
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* bus, which for this part excludes only GPIO.
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*/
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/* Peripheral IDs
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*
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* For peripherals on the APB bus there is a direct relationship between its ID
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* and its base address. A peripheral with base address 0x40000000 is therefore
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* assigned ID=0, and a peripheral with base address 0x40001000 is assigned
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* ID=1. The peripheral with base address 0x4001F000 is assigned ID=31
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*/
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#define PERIPH_CLOCK_ID (0x00)
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#define PERIPH_POWER_ID (0x00)
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#define PERIPH_MPU_ID (0x00)
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#define PERIPH_RADIO_ID (0x01)
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#define PERIPH_UART_ID (0x02)
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#define PERIPH_SPI0_ID (0x03)
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#define PERIPH_TWI0_ID (0x03)
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#define PERIPH_I2C0_ID (0x03)
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#define PERIPH_SPI1_ID (0x04)
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#define PERIPH_SPIS1_ID (0x04)
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#define PERIPH_TWI1_ID (0x04)
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#define PERIPH_I2C1_ID (0x04)
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#define PERIPH_GPIOTE_ID (0x06)
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#define PERIPH_ADC_ID (0x07)
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#define PERIPH_TIMER0_ID (0x08)
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#define PERIPH_TIMER1_ID (0x09)
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#define PERIPH_TIMER2_ID (0x0a)
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#define PERIPH_RTC0_ID (0x0b)
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#define PERIPH_TEMP_ID (0x0c)
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#define PERIPH_RNG_ID (0x0d)
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#define PERIPH_ECB_ID (0x0e)
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#define PERIPH_AAR_ID (0x0f)
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#define PERIPH_CCM_ID (0x0f)
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#define PERIPH_WDT_ID (0x10)
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#define PERIPH_RTC1_ID (0x11)
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#define PERIPH_QDEC_ID (0x12)
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#define PERIPH_LPCOMP_ID (0x13)
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#define PERIPH_SWI0_ID (0x14)
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#define PERIPH_SWI1_ID (0x15)
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#define PERIPH_SWI2_ID (0x16)
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#define PERIPH_SWI3_ID (0x17)
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#define PERIPH_SWI4_ID (0x18)
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#define PERIPH_SWI5_ID (0x19)
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#define PERIPH_NVMC_ID (0x1e)
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#define PERIPH_PPI_ID (0x1f)
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#define PERIPH_BASE_FROM_ID(periph_id) (ABP_BASE + 0x1000 * (periph_id))
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#define PERIPH_ID_FROM_BASE(base) (((base) - APB_BASE) >> 12)
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#define PERIPH_BASE_FROM_REG(reg) (((uint32_t) &(reg)) & 0xfffff000)
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/*
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* Tasks are used to trigger actions in a peripheral, for example, to start a
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* particular behavior. A peripheral can implement multiple tasks with each
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* task having a separate register in that peripheral's task register group.
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*
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* A task is triggered when firmware writes a '1' to the task register or when
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* the peripheral itself, or another peripheral, toggles the corresponding task
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* signal.
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*/
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/** Starting address of all the tasks in the peripheral. */
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#define PERIPH_TASK_OFFSET (0x000)
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/*
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* Events are used to notify peripherals and the CPU about events that have
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* happened, for example, a state change in a peripheral. A peripheral may
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* generate multiple events with each event having a separate register in that
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* peripheral’s event register group. An event is generated when the
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* peripheral itself toggles the corresponding event signal, whereupon the
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* event register is updated to reflect that the event has been generated.
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*/
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/** Starting address of all the events in the peripheral. */
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#define PERIPH_EVENT_OFFSET (0x100)
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#define PERIPH_TRIGGER_TASK(task) (task) = (1)
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/* All peripherals on the APB bus support interrupts. A peripheral only
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* occupies one interrupt, and the interrupt number follows the peripheral ID,
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* for example, the peripheral with ID=4 is connected to interrupt number 4 in
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* the Nested Vector Interrupt Controller (NVIC).
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*/
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#define PERIPH_ENABLE_IRQ(base) nvic_enable_irq(periph_id_from_base(base))
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#define PERIPH_DISABLE_IRQ(base) nvic_disable_irq(periph_id_from_base(base))
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/* Common regisgers. Not all peripherals have these registers, but when they
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* are present, they are at this offset.
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*/
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#define PERIPH_SHORTS_OFFSET (0x200)
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#define PERIPH_INTEN_OFFSET (0x300)
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#define PERIPH_INTENSET_OFFSET (0x304)
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#define PERIPH_INTENCLR_OFFSET (0x308)
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#define _PERIPH_SHORTS(base) MMIO32((base) + PERIPH_SHORTS_OFFSET)
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#define _PERIPH_INTEN(base) MMIO32((base) + PERIPH_INTEN_OFFSET)
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#define _PERIPH_INTENSET(base) MMIO32((base) + PERIPH_INTENSET_OFFSET)
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#define _PERIPH_INTENCLR(base) MMIO32((base) + PERIPH_INTENCLR_OFFSET)
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/* TODO: convert these to functions */
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#define periph_enable_shorts(base, shorts) periph_shorts(base) |= (shorts)
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#define periph_disable_shorts(base, shorts) periph_shorts(base) &= (~(shorts))
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#define periph_clear_shorts(base) periph_shorts(base) = (0)
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#define periph_enable_interrupts(base, mask) periph_intenset(base) |= (mask)
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#define periph_disable_interrupts(base, mask) periph_intenclr(base) = (mask)
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#define periph_clear_interrupts(base) periph_intenclr(base) = (0xffffffff)
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/** Mark the signal as not connected to any pin. */
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#define GPIO_UNCONNECTED 0xFFFFFFFFU
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/** This is an approximation of log2. As used here, works correctly
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* only for single bit set, which should be the case when used to.
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* convert above GPIOxy macros to pin numbers as needed for PSEL
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* registers of peripherals.
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*/
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#define __GPIO2PIN(x) (31 - __builtin_clz((uint32_t) (x)))
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