Make examples/other make use of new clock setup.
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@@ -20,51 +20,9 @@
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#include <libopenstm32/rcc.h>
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#include <libopenstm32/flash.h>
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#include <libopenstm32/gpio.h>
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#include <libopenstm32/usart.h>
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#include <libopenstm32/timer.h>
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#include <libopenstm32/nvic.h>
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/* Set STM32 to 72 MHz. HSE 16MHz */
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void clock_setup(void)
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{
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/* enable Internal High Speed Oscillator */
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rcc_osc_on(HSI);
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rcc_wait_for_osc_ready(HSI);
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/* Select HSI as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSICLK);
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/* enable External High Speed Oscillator 16MHz */
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rcc_osc_on(HSE);
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rcc_wait_for_osc_ready(HSE);
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rcc_set_sysclk_source(SW_SYSCLKSEL_HSECLK);
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/* set prescalers for ADC, ABP1, ABP2... make this before touching the PLL */
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rcc_set_hpre(HPRE_SYSCLK_NODIV); //prescales the AHB clock from the SYSCLK
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rcc_set_adcpre(ADCPRE_PLCK2_DIV6); //prescales the ADC from the APB2 clock; max 14MHz
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rcc_set_ppre1(PPRE1_HCLK_DIV2); //prescales the APB1 from the AHB clock; max 36MHz
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rcc_set_ppre2(PPRE2_HCLK_NODIV); //prescales the APB2 from the AHB clock; max 72MHz
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/* sysclk should run with 72MHz -> 2 Waitstates ; choose 0WS from 0-24MHz, 1WS from 24-48MHz, 2WS from 48-72MHz */
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flash_set_ws(FLASH_LATENCY_2WS);
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/* Set the PLL multiplication factor to 9. -> 16MHz (external) * 9 (multiplier) / 2 (PLLXTPRE_HSE_CLK_DIV2) = 72MHz */
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rcc_set_pll_multiplication_factor(PLLMUL_PLL_CLK_MUL9);
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/* Select HSI as PLL source. */
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rcc_set_pll_source(PLLSRC_HSE_CLK);
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/* divide external frequency by 2 before entering pll (only valid/needed for HSE) */
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rcc_set_pllxtpre(PLLXTPRE_HSE_CLK_DIV2);
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/* Enable PLL oscillator and wait for it to stabilize. */
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rcc_osc_on(PLL);
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rcc_wait_for_osc_ready(PLL);
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/* Select PLL as SYSCLK source. */
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rcc_set_sysclk_source(SW_SYSCLKSEL_PLLCLK);
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}
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void gpio_setup(void)
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{
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/* Enable GPIOB clock. */
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@@ -95,7 +53,7 @@ void tim2_isr()
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int main(void)
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{
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clock_setup();
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rcc_clock_setup_in_hse_16mhz_out_72mhz();
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gpio_setup();
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nvic_setup();
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