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Spellchecking fixes.

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This commit is contained in:
Piotr Esden-Tempski
2013-06-16 14:06:37 -07:00
parent 169dbd6c08
commit fb5c86db07
22 changed files with 44 additions and 44 deletions
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2
include/libopencm3/stm32/can.h
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@@ -41,7 +41,7 @@ LGPL License Terms @ref lgpl_license
/* --- Convenience macros -------------------------------------------------- */ /* --- Convenience macros -------------------------------------------------- */
/* CAN register base adresses (for convenience) */ /* CAN register base addresses (for convenience) */
/*****************************************************************************/ /*****************************************************************************/
/** @defgroup can_reg_base CAN register base address /** @defgroup can_reg_base CAN register base address
@ingroup can_defines @ingroup can_defines

6
include/libopencm3/stm32/common/crc_common_all.h
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@@ -77,9 +77,9 @@ BEGIN_DECLS
void crc_reset(void); void crc_reset(void);
/** /**
* Add a word to the crc calculator and return the result. * Add a word to the CRC calculator and return the result.
* @param data new word to add to the crc calculator * @param data new word to add to the CRC calculator
* @return final crc calculator value * @return final CRC calculator value
*/ */
uint32_t crc_calculate(uint32_t data); uint32_t crc_calculate(uint32_t data);

2
include/libopencm3/stm32/common/gpio_common_f24.h
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@@ -248,7 +248,7 @@ specific memorymap.h header before including this header file.*/
/* --- GPIOx_AFRL/H values ------------------------------------------------- */ /* --- GPIOx_AFRL/H values ------------------------------------------------- */
/* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */ /* Note: AFRL is used for bits 0..7, AFRH is used for 8..15 */
/* See Datasheet Table 6 (pg. 48) for alternate function mappings. */ /* See datasheet table 6 (pg. 48) for alternate function mappings. */
#define GPIO_AFR(n, af) (af << ((n) * 4)) #define GPIO_AFR(n, af) (af << ((n) * 4))
#define GPIO_AFR_MASK(n) (0xf << ((n) * 4)) #define GPIO_AFR_MASK(n) (0xf << ((n) * 4))

8
include/libopencm3/stm32/common/i2c_common_all.h
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@@ -39,7 +39,7 @@ specific memorymap.h header before including this header file.*/
/* --- Convenience macros -------------------------------------------------- */ /* --- Convenience macros -------------------------------------------------- */
/* I2C register base adresses (for convenience) */ /* I2C register base addresses (for convenience) */
/****************************************************************************/ /****************************************************************************/
/** @defgroup i2c_reg_base I2C register base address /** @defgroup i2c_reg_base I2C register base address
@ingroup i2c_defines @ingroup i2c_defines
@@ -109,7 +109,7 @@ specific memorymap.h header before including this header file.*/
/* PEC: Packet error checking */ /* PEC: Packet error checking */
#define I2C_CR1_PEC (1 << 12) #define I2C_CR1_PEC (1 << 12)
/* POS: Acknowledge / PEC postition */ /* POS: Acknowledge / PEC position */
#define I2C_CR1_POS (1 << 11) #define I2C_CR1_POS (1 << 11)
/* ACK: Acknowledge enable */ /* ACK: Acknowledge enable */
@@ -342,7 +342,7 @@ specific memorymap.h header before including this header file.*/
* TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode) * TRISE[5:0]: Maximum rise time in Fast/Standard mode (master mode)
*/ */
/* --- I2C const definitions ----------------------------------------------- */ /* --- I2C constant definitions -------------------------------------------- */
/****************************************************************************/ /****************************************************************************/
/** @defgroup i2c_rw I2C Read/Write bit /** @defgroup i2c_rw I2C Read/Write bit
@@ -353,7 +353,7 @@ specific memorymap.h header before including this header file.*/
#define I2C_READ 1 #define I2C_READ 1
/**@}*/ /**@}*/
/* --- I2C funtion prototypes----------------------------------------------- */ /* --- I2C function prototypes---------------------------------------------- */
BEGIN_DECLS BEGIN_DECLS

2
include/libopencm3/stm32/common/iwdg_common_all.h
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@@ -70,7 +70,7 @@ specific memorymap.h header before including this header file.*/
/* PR[2:0]: Prescaler divider */ /* PR[2:0]: Prescaler divider */
#define IWDG_PR_LSB 0 #define IWDG_PR_LSB 0
/** @defgroup iwdg_prediv IWDG Prescaler divider /** @defgroup iwdg_prediv IWDG prescaler divider
@ingroup STM32F_iwdg_defines @ingroup STM32F_iwdg_defines
@{*/ @{*/

6
include/libopencm3/stm32/common/rng_common_f24.h
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@@ -45,7 +45,7 @@ specific memorymap.h header before including this header file.*/
/* RNG ENABLE */ /* RNG ENABLE */
#define RNG_CR_RNGEN (1 << 2) #define RNG_CR_RNGEN (1 << 2)
/* RNG interupt enable */ /* RNG interrupt enable */
#define RNG_CR_IE (1 << 3) #define RNG_CR_IE (1 << 3)
/* --- RNG_SR values ------------------------------------------------------- */ /* --- RNG_SR values ------------------------------------------------------- */
@@ -59,10 +59,10 @@ specific memorymap.h header before including this header file.*/
/* Seed error current status */ /* Seed error current status */
#define RNG_SR_SECS (1 << 2) #define RNG_SR_SECS (1 << 2)
/* Clock error interup status */ /* Clock error interrupt status */
#define RNG_SR_CEIS (1 << 5) #define RNG_SR_CEIS (1 << 5)
/* Seed error interup status */ /* Seed error interrupt status */
#define RNG_SR_SEIS (1 << 6) #define RNG_SR_SEIS (1 << 6)
#endif #endif

2
include/libopencm3/stm32/common/timer_common_all.h
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@@ -40,7 +40,7 @@ specific memorymap.h header before including this header file.*/
/* --- Convenience macros -------------------------------------------------- */ /* --- Convenience macros -------------------------------------------------- */
/* Timer register base adresses (for convenience) */ /* Timer register base addresses (for convenience) */
/****************************************************************************/ /****************************************************************************/
/** @defgroup tim_reg_base Timer register base addresses /** @defgroup tim_reg_base Timer register base addresses
@ingroup timer_defines @ingroup timer_defines

2
include/libopencm3/stm32/common/usart_common_all.h
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@@ -235,7 +235,7 @@ specific memorymap.h header before including this header file.*/
/* LBDL: LIN break detection length */ /* LBDL: LIN break detection length */
#define USART_CR2_LBDL (1 << 5) #define USART_CR2_LBDL (1 << 5)
/* ADD[3:0]: Addres of the usart node */ /* ADD[3:0]: Address of the usart node */
#define USART_CR2_ADD_MASK 0xF #define USART_CR2_ADD_MASK 0xF
/* --- USART_CR3 values ---------------------------------------------------- */ /* --- USART_CR3 values ---------------------------------------------------- */

2
include/libopencm3/stm32/desig.h
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@@ -39,7 +39,7 @@
BEGIN_DECLS BEGIN_DECLS
/** /**
* Read the onboard flash size * Read the on board flash size
* @return flash size in KB * @return flash size in KB
*/ */
uint16_t desig_get_flash_size(void); uint16_t desig_get_flash_size(void);

8
include/libopencm3/stm32/f1/adc.h
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@@ -448,7 +448,7 @@ and ADC2
#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12) #define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
/** Timer 5 Trigger Output */ /** Timer 5 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12) #define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
/** Timer53 Compare Output 4 */ /** Timer 5 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12) #define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
/** Injected Software Trigger */ /** Injected Software Trigger */
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */ #define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
@@ -457,7 +457,7 @@ and ADC2
#define ADC_CR2_JEXTSEL_MASK (0x7 << 12) #define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
#define ADC_CR2_JEXTSEL_SHIFT 12 #define ADC_CR2_JEXTSEL_SHIFT 12
/* ALIGN: Data alignement. */ /* ALIGN: Data alignment. */
#define ADC_CR2_ALIGN_RIGHT (0 << 11) #define ADC_CR2_ALIGN_RIGHT (0 << 11)
#define ADC_CR2_ALIGN_LEFT (1 << 11) #define ADC_CR2_ALIGN_LEFT (1 << 11)
#define ADC_CR2_ALIGN (1 << 11) #define ADC_CR2_ALIGN (1 << 11)
@@ -603,9 +603,9 @@ and ADC2
#define ADC_JSQR_JSQ2_LSB 5 #define ADC_JSQR_JSQ2_LSB 5
#define ADC_JSQR_JSQ1_LSB 0 #define ADC_JSQR_JSQ1_LSB 0
/* JL[2:0]: Discontinous mode channel count injected channels. */ /* JL[2:0]: Discontinuous mode channel count injected channels. */
/****************************************************************************/ /****************************************************************************/
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro /** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode from
injected channels. injected channels.
@ingroup adc_defines @ingroup adc_defines

4
include/libopencm3/stm32/f1/ethernet.h
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@@ -137,14 +137,14 @@
#define ETH_MACFCR_ZQPD 0x00000080 #define ETH_MACFCR_ZQPD 0x00000080
#define ETH_MACFCR_PT 0xFFFF0000 #define ETH_MACFCR_PT 0xFFFF0000
/* Ethernet MAC interrupt status regster ETH_MACSR bits */ /* Ethernet MAC interrupt status register ETH_MACSR bits */
#define ETH_MACSR_PMTS 0x0008 #define ETH_MACSR_PMTS 0x0008
#define ETH_MACSR_MMCS 0x0010 #define ETH_MACSR_MMCS 0x0010
#define ETH_MACSR_MMCRS 0x0020 #define ETH_MACSR_MMCRS 0x0020
#define ETH_MACSR_MMCTS 0x0040 #define ETH_MACSR_MMCTS 0x0040
#define ETH_MACSR_TSTS 0x0200 #define ETH_MACSR_TSTS 0x0200
/* Ethernet MAC interrupt mask regster ETH_MACIMR bits */ /* Ethernet MAC interrupt mask register ETH_MACIMR bits */
#define ETH_MACIMR_PMTIM 0x0008 #define ETH_MACIMR_PMTIM 0x0008
#define ETH_MACIMR_TSTIM 0x0200 #define ETH_MACIMR_TSTIM 0x0200

10
include/libopencm3/stm32/f1/gpio.h
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@@ -780,33 +780,33 @@ Line Devices only
/* ADC2_ETRGREG_REMAP: */ /* ADC2_ETRGREG_REMAP: */
/** /**
* ADC2 external trigger regulator conversion remapping * ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) * (only low-, medium-, high- and XL-density devices)
*/ */
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20) #define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
/* ADC2_ETRGINJ_REMAP: */ /* ADC2_ETRGINJ_REMAP: */
/** /**
* ADC2 external trigger injected conversion remapping * ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) * (only low-, medium-, high- and XL-density devices)
*/ */
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19) #define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
/* ADC1_ETRGREG_REMAP: */ /* ADC1_ETRGREG_REMAP: */
/** /**
* ADC1 external trigger regulator conversion remapping * ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) * (only low-, medium-, high- and XL-density devices)
*/ */
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18) #define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
/* ADC1_ETRGINJ_REMAP: */ /* ADC1_ETRGINJ_REMAP: */
/** /**
* ADC1 external trigger injected conversion remapping * ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices) * (only low-, medium-, high- and XL-density devices)
*/ */
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17) #define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
/* TIM5CH4_IREMAP: */ /* TIM5CH4_IREMAP: */
/** TIM5 channel4 internal remap */ /** TIM5 channel 4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16) #define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
/* PD01_REMAP: */ /* PD01_REMAP: */

2
include/libopencm3/stm32/f1/memorymap.h
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@@ -24,7 +24,7 @@
/* --- STM32 specific peripheral definitions ------------------------------- */ /* --- STM32 specific peripheral definitions ------------------------------- */
/* Memory map for all busses */ /* Memory map for all buses */
#define FLASH_BASE ((uint32_t)0x08000000) #define FLASH_BASE ((uint32_t)0x08000000)
#define PERIPH_BASE ((uint32_t)0x40000000) #define PERIPH_BASE ((uint32_t)0x40000000)
#define INFO_BASE ((uint32_t)0x1ffff000) #define INFO_BASE ((uint32_t)0x1ffff000)

8
include/libopencm3/stm32/f1/rcc.h
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@@ -155,7 +155,7 @@ LGPL License Terms @ref lgpl_license
/* ADCPRE: ADC prescaler */ /* ADCPRE: ADC prescaler */
/****************************************************************************/ /****************************************************************************/
/** @defgroup rcc_cfgr_adcpre RCC ADC Clock Prescaler enable values /** @defgroup rcc_cfgr_adcpre RCC ADC clock prescaler enable values
@ingroup STM32F1xx_rcc_defines @ingroup STM32F1xx_rcc_defines
@{*/ @{*/
@@ -166,7 +166,7 @@ LGPL License Terms @ref lgpl_license
/**@}*/ /**@}*/
/* PPRE2: APB high-speed prescaler (APB2) */ /* PPRE2: APB high-speed prescaler (APB2) */
/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 Prescale Factors /** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors
@ingroup STM32F1xx_rcc_defines @ingroup STM32F1xx_rcc_defines
@{*/ @{*/
@@ -178,7 +178,7 @@ LGPL License Terms @ref lgpl_license
/**@}*/ /**@}*/
/* PPRE1: APB low-speed prescaler (APB1) */ /* PPRE1: APB low-speed prescaler (APB1) */
/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 Prescale Factors /** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors
@ingroup STM32F1xx_rcc_defines @ingroup STM32F1xx_rcc_defines
@{*/ @{*/
@@ -190,7 +190,7 @@ LGPL License Terms @ref lgpl_license
/**@}*/ /**@}*/
/* HPRE: AHB prescaler */ /* HPRE: AHB prescaler */
/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB Prescale Factors /** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors
@ingroup STM32F1xx_rcc_defines @ingroup STM32F1xx_rcc_defines
@{*/ @{*/

2
include/libopencm3/stm32/f1/rtc.h
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@@ -32,7 +32,7 @@ LGPL License Terms @ref lgpl_license
*/ */
/* /*
* The F1 RTC is a straight timestamp, a completely different peripheral to * The F1 RTC is a straight time stamp, a completely different peripheral to
* that found in the F2, F3, F4, L1 and F0. * that found in the F2, F3, F4, L1 and F0.
*/ */

6
include/libopencm3/stm32/f1/usb.h
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@@ -43,7 +43,7 @@ LGPL License Terms @ref lgpl_license
/* --- USB base addresses -------------------------------------------------- */ /* --- USB base addresses -------------------------------------------------- */
/* USB packet buffer memory base addr. */ /* USB packet buffer memory base address. */
#define USB_PMA_BASE 0x40006000L #define USB_PMA_BASE 0x40006000L
/* --- USB general registers ----------------------------------------------- */ /* --- USB general registers ----------------------------------------------- */
@@ -104,12 +104,12 @@ LGPL License Terms @ref lgpl_license
#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF) #define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF) #define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
/* --- USB device addres register masks / bits ----------------------------- */ /* --- USB device address register masks / bits ---------------------------- */
#define USB_DADDR_ENABLE 0x0080 #define USB_DADDR_ENABLE 0x0080
#define USB_DADDR_ADDR 0x007F #define USB_DADDR_ADDR 0x007F
/* --- USB device addres register manipulators ----------------------------- */ /* --- USB device address register manipulators ---------------------------- */
/* --- USB endpoint register offsets --------------------------------------- */ /* --- USB endpoint register offsets --------------------------------------- */

2
include/libopencm3/stm32/fsmc.h
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@@ -123,7 +123,7 @@
/* FACCEN: Flash access enable */ /* FACCEN: Flash access enable */
#define FSMC_BCR_FACCEN (1 << 6) #define FSMC_BCR_FACCEN (1 << 6)
/* MWID[5:4]: Memory databus width */ /* MWID[5:4]: Memory data bus width */
#define FSMC_BCR_MWID (1 << 4) #define FSMC_BCR_MWID (1 << 4)
/* MTYP[3:2]: Memory type */ /* MTYP[3:2]: Memory type */

2
include/libopencm3/stm32/otg_fs.h
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@@ -330,7 +330,7 @@
#define OTG_FS_DOEPINTX_EPDISD (1 << 1) #define OTG_FS_DOEPINTX_EPDISD (1 << 1)
#define OTG_FS_DOEPINTX_XFRC (1 << 0) #define OTG_FS_DOEPINTX_XFRC (1 << 0)
/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_FS_DOEPTSIZ0) */ /* OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_FS_DOEPTSIZ0) */
/* Bit 31 - Reserved */ /* Bit 31 - Reserved */
#define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) #define OTG_FS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
#define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) #define OTG_FS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)

2
include/libopencm3/stm32/otg_hs.h
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@@ -384,7 +384,7 @@
#define OTG_HS_DOEPINTX_EPDISD (1 << 1) #define OTG_HS_DOEPINTX_EPDISD (1 << 1)
#define OTG_HS_DOEPINTX_XFRC (1 << 0) #define OTG_HS_DOEPINTX_XFRC (1 << 0)
/* OTG_FS Device OUT Endpoint 0 Transfer Size Regsiter (OTG_HS_DOEPTSIZ0) */ /* OTG_FS Device OUT Endpoint 0 Transfer Size Register (OTG_HS_DOEPTSIZ0) */
/* Bit 31 - Reserved */ /* Bit 31 - Reserved */
#define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29) #define OTG_HS_DIEPSIZ0_STUPCNT_1 (0x1 << 29)
#define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29) #define OTG_HS_DIEPSIZ0_STUPCNT_2 (0x2 << 29)

4
include/libopencm3/stm32/sdio.h
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@@ -182,7 +182,7 @@
/* DBLOCKSIZE: Data block size */ /* DBLOCKSIZE: Data block size */
/* SDIO_DCTRL_DBLOCKSIZE_n /* SDIO_DCTRL_DBLOCKSIZE_n
* blocksize is 2**n bytes with 0<=n<=14 * block size is 2**n bytes with 0<=n<=14
*/ */
#define SDIO_DCTRL_DBLOCKSIZE_SHIFT 4 #define SDIO_DCTRL_DBLOCKSIZE_SHIFT 4
#define SDIO_DCTRL_DBLOCKSIZE_0 (0x0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) #define SDIO_DCTRL_DBLOCKSIZE_0 (0x0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT)
@@ -204,7 +204,7 @@
/* DMAEN: DMA enable bit */ /* DMAEN: DMA enable bit */
#define SDIO_DCTRL_DMAEN (1 << 3) #define SDIO_DCTRL_DMAEN (1 << 3)
/* DTMODE: Data transfer mode selection 1: Stream or SDIO multibyte transfer */ /* DTMODE: Data transfer mode selection 1: Stream or SDIO multi byte transfer */
#define SDIO_DCTRL_DTMODE (1 << 2) #define SDIO_DCTRL_DTMODE (1 << 2)
/* DTDIR: Data transfer direction selection */ /* DTDIR: Data transfer direction selection */

4
include/libopencm3/stm32/tools.h
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@@ -45,8 +45,8 @@
* *
* This means that we look at the bits in the bit window designated by * This means that we look at the bits in the bit window designated by
* the mask. If the bit in the masked window is not matching the * the mask. If the bit in the masked window is not matching the
* bitmask BIT then we write 1 and if the bit in the masked window is * bit mask BIT then we write 1 and if the bit in the masked window is
* matching the bitmask BIT we write 0. * matching the bit mask BIT we write 0.
* *
* TODO: We may need a faster implementation of that one? * TODO: We may need a faster implementation of that one?
*/ */

2
include/libopencm3/stm32/wwdg.h
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@@ -76,7 +76,7 @@
/* EWIF: Early wakeup interrupt flag */ /* EWIF: Early wakeup interrupt flag */
#define WWDG_SR_EWIF (1 << 0) #define WWDG_SR_EWIF (1 << 0)
/* --- WWDG funtion prototypes---------------------------------------------- */ /* --- WWDG function prototypes---------------------------------------------- */
/* TODO */ /* TODO */