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Spellchecking fixes.

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This commit is contained in:
Piotr Esden-Tempski
2013-06-16 14:06:37 -07:00
parent 169dbd6c08
commit fb5c86db07
22 changed files with 44 additions and 44 deletions
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include/libopencm3/stm32/f1/adc.h
+4 -4
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@@ -448,7 +448,7 @@ and ADC2
#define ADC_CR2_JEXTSEL_TIM8_CC4 (0x4 << 12)
/** Timer 5 Trigger Output */
#define ADC_CR2_JEXTSEL_TIM5_TRGO (0x5 << 12)
/** Timer53 Compare Output 4 */
/** Timer 5 Compare Output 4 */
#define ADC_CR2_JEXTSEL_TIM5_CC4 (0x6 << 12)
/** Injected Software Trigger */
#define ADC_CR2_JEXTSEL_JSWSTART (0x7 << 12) /* Software start. */
@@ -457,7 +457,7 @@ and ADC2
#define ADC_CR2_JEXTSEL_MASK (0x7 << 12)
#define ADC_CR2_JEXTSEL_SHIFT 12
/* ALIGN: Data alignement. */
/* ALIGN: Data alignment. */
#define ADC_CR2_ALIGN_RIGHT (0 << 11)
#define ADC_CR2_ALIGN_LEFT (1 << 11)
#define ADC_CR2_ALIGN (1 << 11)
@@ -603,9 +603,9 @@ and ADC2
#define ADC_JSQR_JSQ2_LSB 5
#define ADC_JSQR_JSQ1_LSB 0
/* JL[2:0]: Discontinous mode channel count injected channels. */
/* JL[2:0]: Discontinuous mode channel count injected channels. */
/****************************************************************************/
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode fro
/** @defgroup adc_jsqr_jl ADC Number of channels in discontinuous mode from
injected channels.
@ingroup adc_defines
include/libopencm3/stm32/f1/ethernet.h
+2 -2
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@@ -137,14 +137,14 @@
#define ETH_MACFCR_ZQPD 0x00000080
#define ETH_MACFCR_PT 0xFFFF0000
/* Ethernet MAC interrupt status regster ETH_MACSR bits */
/* Ethernet MAC interrupt status register ETH_MACSR bits */
#define ETH_MACSR_PMTS 0x0008
#define ETH_MACSR_MMCS 0x0010
#define ETH_MACSR_MMCRS 0x0020
#define ETH_MACSR_MMCTS 0x0040
#define ETH_MACSR_TSTS 0x0200
/* Ethernet MAC interrupt mask regster ETH_MACIMR bits */
/* Ethernet MAC interrupt mask register ETH_MACIMR bits */
#define ETH_MACIMR_PMTIM 0x0008
#define ETH_MACIMR_TSTIM 0x0200
include/libopencm3/stm32/f1/gpio.h
+5 -5
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@@ -780,33 +780,33 @@ Line Devices only
/* ADC2_ETRGREG_REMAP: */
/**
* ADC2 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
* (only low-, medium-, high- and XL-density devices)
*/
#define AFIO_MAPR_ADC2_ETRGREG_REMAP (1 << 20)
/* ADC2_ETRGINJ_REMAP: */
/**
* ADC2 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
* (only low-, medium-, high- and XL-density devices)
*/
#define AFIO_MAPR_ADC2_ETRGINJ_REMAP (1 << 19)
/* ADC1_ETRGREG_REMAP: */
/**
* ADC1 external trigger regulator conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
* (only low-, medium-, high- and XL-density devices)
*/
#define AFIO_MAPR_ADC1_ETRGREG_REMAP (1 << 18)
/* ADC1_ETRGINJ_REMAP: */
/**
* ADC1 external trigger injected conversion remapping
* (only low-, medium-, high- and XL-densitiy devices)
* (only low-, medium-, high- and XL-density devices)
*/
#define AFIO_MAPR_ADC1_ETRGINJ_REMAP (1 << 17)
/* TIM5CH4_IREMAP: */
/** TIM5 channel4 internal remap */
/** TIM5 channel 4 internal remap */
#define AFIO_MAPR_TIM5CH4_IREMAP (1 << 16)
/* PD01_REMAP: */
include/libopencm3/stm32/f1/memorymap.h
+1 -1
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@@ -24,7 +24,7 @@
/* --- STM32 specific peripheral definitions ------------------------------- */
/* Memory map for all busses */
/* Memory map for all buses */
#define FLASH_BASE ((uint32_t)0x08000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
#define INFO_BASE ((uint32_t)0x1ffff000)
include/libopencm3/stm32/f1/rcc.h
+4 -4
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@@ -155,7 +155,7 @@ LGPL License Terms @ref lgpl_license
/* ADCPRE: ADC prescaler */
/****************************************************************************/
/** @defgroup rcc_cfgr_adcpre RCC ADC Clock Prescaler enable values
/** @defgroup rcc_cfgr_adcpre RCC ADC clock prescaler enable values
@ingroup STM32F1xx_rcc_defines
@{*/
@@ -166,7 +166,7 @@ LGPL License Terms @ref lgpl_license
/**@}*/
/* PPRE2: APB high-speed prescaler (APB2) */
/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 Prescale Factors
/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
@@ -178,7 +178,7 @@ LGPL License Terms @ref lgpl_license
/**@}*/
/* PPRE1: APB low-speed prescaler (APB1) */
/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 Prescale Factors
/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
@@ -190,7 +190,7 @@ LGPL License Terms @ref lgpl_license
/**@}*/
/* HPRE: AHB prescaler */
/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB Prescale Factors
/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB prescale Factors
@ingroup STM32F1xx_rcc_defines
@{*/
include/libopencm3/stm32/f1/rtc.h
+1 -1
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@@ -32,7 +32,7 @@ LGPL License Terms @ref lgpl_license
*/
/*
* The F1 RTC is a straight timestamp, a completely different peripheral to
* The F1 RTC is a straight time stamp, a completely different peripheral to
* that found in the F2, F3, F4, L1 and F0.
*/
include/libopencm3/stm32/f1/usb.h
+3 -3
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@@ -43,7 +43,7 @@ LGPL License Terms @ref lgpl_license
/* --- USB base addresses -------------------------------------------------- */
/* USB packet buffer memory base addr. */
/* USB packet buffer memory base address. */
#define USB_PMA_BASE 0x40006000L
/* --- USB general registers ----------------------------------------------- */
@@ -104,12 +104,12 @@ LGPL License Terms @ref lgpl_license
#define USB_CLR_ISTR_SOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_SOF)
#define USB_CLR_ISTR_ESOF() CLR_REG_BIT(USB_ISTR_REG, USB_ISTR_ESOF)
/* --- USB device addres register masks / bits ----------------------------- */
/* --- USB device address register masks / bits ---------------------------- */
#define USB_DADDR_ENABLE 0x0080
#define USB_DADDR_ADDR 0x007F
/* --- USB device addres register manipulators ----------------------------- */
/* --- USB device address register manipulators ---------------------------- */
/* --- USB endpoint register offsets --------------------------------------- */