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lpc43xx/uart: Fix TER register definition

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I'm not sure why bit 7 and offset 0x30 were used previously. Revision
1.6 of UM10503 claims that the TXEN bit is bit 0 in all UARTs' TER
registers.
This commit is contained in:
Ben Gamari
2013-07-02 07:45:10 -04:00
committed by Piotr Esden-Tempski
parent dbf9c3bc39
commit fa47bb80d5
2 changed files with 8 additions and 30 deletions
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8
include/libopencm3/lpc43xx/uart.h
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@@ -74,9 +74,6 @@
/* Oversampling Register only for UART0/2/3 */
#define UART_OSR(port) MMIO32(port + 0x02C)
/* Transmit Enable Register Only for UART1 */
#define UART_TER_UART1(port) MMIO32(port + 0x030)
/* Half-Duplex enable Register only for UART0/2/3 */
#define UART_HDEN(port) MMIO32(port + 0x040)
@@ -95,7 +92,7 @@
/* Synchronous Mode Control Register only for UART0/2/3 */
#define UART_SYNCCTRL(port) MMIO32(port + 0x058)
/* Transmit Enable Register Only for UART0/2/3 */
/* Transmit Enable Register */
#define UART_TER(port) MMIO32(port + 0x05C)
/* --------------------- BIT DEFINITIONS -------------------------------------- */
@@ -255,8 +252,7 @@
/*********************************************************************
* Macro defines for Macro defines for UART Tx Enable register
**********************************************************************/
#define UART1_TER_TXEN ((uint8_t)(BIT7)) /* Transmit enable bit */
#define UART0_2_3_TER_TXEN ((uint8_t)(BIT0)) /* Transmit enable bit */
#define UART_TER_TXEN ((uint8_t)(BIT0)) /* Transmit enable bit */
/**********************************************************************
* Macro defines for Macro defines for UART FIFO Level register