From f99e7118732f5749f9de2c56fccb0c5ac05fdf00 Mon Sep 17 00:00:00 2001
From: Guillaume Revaillot <revaillot@archos.com>
Date: Wed, 3 Jul 2019 17:19:48 +0200
Subject: [PATCH] stm32g0: lptim: add additional cr bits and cfgr2 reg.

---
 include/libopencm3/stm32/g0/lptimer.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/include/libopencm3/stm32/g0/lptimer.h b/include/libopencm3/stm32/g0/lptimer.h
index 183f9b4e..e3606d7c 100644
--- a/include/libopencm3/stm32/g0/lptimer.h
+++ b/include/libopencm3/stm32/g0/lptimer.h
@@ -39,6 +39,29 @@
 #define LPTIM2				LPTIM2_BASE
 /**@}*/
 
+/** LPTIM_CFGR2 LPTIM configuration register 2 */
+#define LPTIM_CFGR2(tim_base)			MMIO32((tim_base) + 0x24)
+
+/** @addtogroup lptim_cr
+@{*/
+/** COUNTRST Counter reset **/
+#define LPTIM_CR_COUNTRST		(1 << 3)
+/** RSTARE Reset after read enable **/
+#define LPTIM_CR_RSTARE		(1 << 4)
+/**@}*/
+
+/** @defgroup lptim_cfgr2 LPTIM_CFGR2 Configuration Register 2
+@{*/
+
+#define LPTIM_CFGR2_IN2SEL_SHIFT	4
+#define LPTIM_CFGR2_IN2SEL_MASK		0x03
+
+#define LPTIM_CFGR2_IN1SEL_SHIFT	0
+#define LPTIM_CFGR2_IN1SEL_MASK		0x03
+
+/**@}*/
+
+
 BEGIN_DECLS
 
 END_DECLS