diff --git a/include/libopencm3/stm32/g0/rcc.h b/include/libopencm3/stm32/g0/rcc.h
index 3c5ad375..40441ee1 100644
--- a/include/libopencm3/stm32/g0/rcc.h
+++ b/include/libopencm3/stm32/g0/rcc.h
@@ -463,7 +463,7 @@
 /** @defgroup rcc_ccipr_rngdiv RNGDIV
 @{*/
 #define RCC_CCIPR_RNGDIV_1		0
-#define RCC_CCIPR_RNGDIV_2 		1
+#define RCC_CCIPR_RNGDIV_2		1
 #define RCC_CCIPR_RNGDIV_4		2
 #define RCC_CCIPR_RNGDIV_8		3
 /**@}*/
@@ -473,7 +473,7 @@
 /** @defgroup rcc_ccipr_rngsel RNGSEL
 @{*/
 #define RCC_CCIPR_RNGSEL_NONE		0
-#define RCC_CCIPR_RNGSEL_HSI16 		1
+#define RCC_CCIPR_RNGSEL_HSI16		1
 #define RCC_CCIPR_RNGSEL_SYSCLK		2
 #define RCC_CCIPR_RNGSEL_PLLQCLK	3
 /**@}*/
@@ -483,7 +483,7 @@
 /** @defgroup rcc_ccipr_tim15sel TIM15SEL
 @{*/
 #define RCC_CCIPR_TIM15SEL_TIMPCLK		0
-#define RCC_CCIPR_TIM15SEL_PLLQCLK 		1
+#define RCC_CCIPR_TIM15SEL_PLLQCLK		1
 /**@}*/
 
 #define RCC_CCIPR_TIM1SEL_MASK		0x1
@@ -491,7 +491,7 @@
 /** @defgroup rcc_ccipr_tim1sel TIM1SEL
 @{*/
 #define RCC_CCIPR_TIM1SEL_TIMPCLK		0
-#define RCC_CCIPR_TIM1SEL_PLLQCLK 		1
+#define RCC_CCIPR_TIM1SEL_PLLQCLK		1
 /**@}*/
 
 #define RCC_CCIPR_LPTIM2SEL_MASK		0x3
@@ -499,8 +499,8 @@
 /** @defgroup rcc_ccipr_lptim2sel LPTIM2SEL LPTIM2 Clock source selection
 @{*/
 #define RCC_CCIPR_LPTIM2SEL_PCLK		0
-#define RCC_CCIPR_LPTIM2SEL_LSI		 	1
-#define RCC_CCIPR_LPTIM2SEL_HSI16 		2
+#define RCC_CCIPR_LPTIM2SEL_LSI			1
+#define RCC_CCIPR_LPTIM2SEL_HSI16		2
 #define RCC_CCIPR_LPTIM2SEL_LSE			3
 /**@}*/
 
@@ -510,7 +510,7 @@
 @{*/
 #define RCC_CCIPR_LPTIM1SEL_PCLK		0
 #define RCC_CCIPR_LPTIM1SEL_LSI			1
-#define RCC_CCIPR_LPTIM1SEL_HSI16 		2
+#define RCC_CCIPR_LPTIM1SEL_HSI16		2
 #define RCC_CCIPR_LPTIM1SEL_LSE			3
 /**@}*/
 
@@ -520,8 +520,8 @@
 @{*/
 #define RCC_CCIPR_I2S1SEL_SYSCLK		0
 #define RCC_CCIPR_I2S1SEL_PLLPLCK		1
-#define RCC_CCIPR_I2S1SEL_HSI16 		2
-#define RCC_CCIPR_I2S1SEL_I2S_CKIN 		2
+#define RCC_CCIPR_I2S1SEL_HSI16			2
+#define RCC_CCIPR_I2S1SEL_I2S_CKIN		3
 /**@}*/
 
 #define RCC_CCIPR_I2C1SEL_MASK		0x3
@@ -530,7 +530,7 @@
 @{*/
 #define RCC_CCIPR_I2C1SEL_PCLK			0
 #define RCC_CCIPR_I2C1SEL_SYSCLK		1
-#define RCC_CCIPR_I2C1SEL_HSI16 		2
+#define RCC_CCIPR_I2C1SEL_HSI16			2
 /**@}*/
 
 #define RCC_CCIPR_LPUART1SEL_MASK		0x3
@@ -539,7 +539,7 @@
 @{*/
 #define RCC_CCIPR_LPUART1SEL_PCLK			0
 #define RCC_CCIPR_LPUART1SEL_SYSCLK			1
-#define RCC_CCIPR_LPUART1SEL_HSI16 			2
+#define RCC_CCIPR_LPUART1SEL_HSI16			2
 #define RCC_CCIPR_LPUART1SEL_LSE			3
 /**@}*/
 
@@ -548,7 +548,7 @@
 /** @defgroup rcc_ccipr_cecsel CECSEL CEC Clock souce selection
 @{*/
 #define RCC_CCIPR_CECSEL_HSI16			0
-#define RCC_CCIPR_CECSEL_LSE 			1
+#define RCC_CCIPR_CECSEL_LSE			1
 /**@}*/
 
 #define RCC_CCIPR_USART2SEL_MASK		0x3
@@ -556,8 +556,8 @@
 /** @defgroup rcc_ccipr_usart2sel USART2SEL USART2 Clock source selection
 @{*/
 #define RCC_CCIPR_USART2SEL_PCLK		0
-#define RCC_CCIPR_USART2SEL_SYSCLK	 	1
-#define RCC_CCIPR_USART2SEL_HSI16 		2
+#define RCC_CCIPR_USART2SEL_SYSCLK		1
+#define RCC_CCIPR_USART2SEL_HSI16		2
 #define RCC_CCIPR_USART2SEL_LSE			3
 /**@}*/
 
@@ -567,7 +567,7 @@
 @{*/
 #define RCC_CCIPR_USART1SEL_PCLK		0
 #define RCC_CCIPR_USART1SEL_SYSCLK		1
-#define RCC_CCIPR_USART1SEL_HSI16 		2
+#define RCC_CCIPR_USART1SEL_HSI16		2
 #define RCC_CCIPR_USART1SEL_LSE			3
 /**@}*/
 /**@}*/