[stm32l0] Initial support for STM32L0 architecture, Add GPIO peripheral

Makefile

@@ -34,8 +34,8 @@ space:=
 space+=
 SRCLIBDIR:= $(subst $(space),\$(space),$(realpath lib))
 
-TARGETS:= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/l1 lpc13xx lpc17xx \
+TARGETS:= stm32/f0 stm32/f1 stm32/f2 stm32/f3 stm32/f4 stm32/l0 stm32/l1 \
-	  lpc43xx/m4 lpc43xx/m0 lm3s lm4f \
+	  lpc13xx lpc17xx lpc43xx/m4 lpc43xx/m0 lm3s lm4f \
 	  efm32/efm32tg efm32/efm32g efm32/efm32lg efm32/efm32gg \
 	  sam/3a sam/3n sam/3s sam/3u sam/3x \
 	  vf6xx

include/libopencm3/dispatch/nvic.h

@@ -8,6 +8,8 @@
 #	include <libopencm3/stm32/f3/nvic.h>
 #elif defined(STM32F4)
 #	include <libopencm3/stm32/f4/nvic.h>
+#elif defined(STM32L0)
+#	include <libopencm3/stm32/l0/nvic.h>
 #elif defined(STM32L1)
 #	include <libopencm3/stm32/l1/nvic.h>
 

include/libopencm3/stm32/gpio.h

@@ -30,6 +30,8 @@
 #       include <libopencm3/stm32/f3/gpio.h>
 #elif defined(STM32F4)
 #       include <libopencm3/stm32/f4/gpio.h>
+#elif defined(STM32L0)
+#       include <libopencm3/stm32/l0/gpio.h>
 #elif defined(STM32L1)
 #       include <libopencm3/stm32/l1/gpio.h>
 #else

include/libopencm3/stm32/l0/gpio.h

@@ -0,0 +1,75 @@
+/** @defgroup gpio_defines GPIO Defines
+ *
+ * @brief <b>Defined Constants and Types for the STM32F0xx General Purpose I/O</b>
+ *
+ * @ingroup STM32L0xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @date 1 July 2012
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_GPIO_H
+#define LIBOPENCM3_GPIO_H
+
+#include <libopencm3/stm32/common/gpio_common_f24.h>
+
+/*****************************************************************************/
+/* Module definitions                                                        */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* Register definitions                                                      */
+/*****************************************************************************/
+
+#define GPIO_BRR(port)			MMIO32(port + 0x28)
+#define GPIOA_BRR			GPIO_BRR(GPIOA)
+#define GPIOB_BRR			GPIO_BRR(GPIOB)
+#define GPIOC_BRR			GPIO_BRR(GPIOC)
+#define GPIOD_BRR			GPIO_BRR(GPIOD)
+#define GPIOH_BRR			GPIO_BRR(GPIOH)
+
+/*****************************************************************************/
+/* Register values                                                           */
+/*****************************************************************************/
+
+/** @defgroup gpio_speed GPIO Output Pin Speed
+@ingroup gpio_defines
+@{*/
+#define GPIO_OSPEED_LOW		0x0
+#define GPIO_OSPEED_MED		0x1
+#define GPIO_OSPEED_HIGH	0x3
+/**@}*/
+
+/*****************************************************************************/
+/* API definitions                                                           */
+/*****************************************************************************/
+
+/*****************************************************************************/
+/* API Functions                                                             */
+/*****************************************************************************/
+
+BEGIN_DECLS
+
+END_DECLS
+
+#endif

include/libopencm3/stm32/l0/irq.json

@@ -0,0 +1,39 @@
+{
+    "irqs": [
+        "wwdg", 
+        "pvd", 
+        "rtc", 
+        "flash", 
+        "rcc", 
+        "exti0_1", 
+        "exti2_3", 
+        "exti4_15", 
+        "tsc", 
+        "dma1_channel1", 
+        "dma1_channel2_3", 
+        "dma1_channel4_5", 
+        "adc_comp", 
+        "lptim1", 
+        "reserved1", 
+        "tim2", 
+        "reserved2", 
+        "tim6_dac", 
+        "reserved3", 
+        "reserved4", 
+        "tim21", 
+        "reserved5", 
+        "tim22", 
+        "i2c1", 
+        "i2c2", 
+        "spi1", 
+        "spi2", 
+        "usart1", 
+        "usart2", 
+        "lpuart1", 
+        "lcd", 
+        "usb"
+    ], 
+    "partname_humanreadable": "STM32 L0 series", 
+    "partname_doxygen": "STM32L0", 
+    "includeguard": "LIBOPENCM3_STM32_L0_NVIC_H"
+}

include/libopencm3/stm32/l0/memorymap.h

@@ -0,0 +1,93 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_MEMORYMAP_H
+#define LIBOPENCM3_MEMORYMAP_H
+
+#include <libopencm3/cm3/memorymap.h>
+
+/* --- STM32 specific peripheral definitions ------------------------------- */
+
+/* Memory map for all busses */
+#define PERIPH_BASE			(0x40000000U)
+#define IOPORT_BASE			(0x50000000U)
+#define INFO_BASE			(0x1ff80000U)
+#define PERIPH_BASE_APB1		(PERIPH_BASE + 0x00000)
+#define PERIPH_BASE_APB2		(PERIPH_BASE + 0x10000)
+#define PERIPH_BASE_AHB			(PERIPH_BASE + 0x20000)
+
+/* Register boundary addresses */
+
+/* APB1 */
+#define TIM2_BASE			(PERIPH_BASE_APB1 + 0x0000)
+#define TIM6_BASE			(PERIPH_BASE_APB1 + 0x1000)
+#define LCD_BASE			(PERIPH_BASE_APB1 + 0x2400)
+#define RTC_BASE			(PERIPH_BASE_APB1 + 0x2800)
+#define WWDG_BASE			(PERIPH_BASE_APB1 + 0x2c00)
+#define IWDG_BASE			(PERIPH_BASE_APB1 + 0x3000)
+#define SPI2_BASE			(PERIPH_BASE_APB1 + 0x3800)
+#define USART2_BASE			(PERIPH_BASE_APB1 + 0x4400)
+#define LPUART1_BASE			(PERIPH_BASE_APB1 + 0x4800)
+#define I2C1_BASE			(PERIPH_BASE_APB1 + 0x5400)
+#define I2C2_BASE			(PERIPH_BASE_APB1 + 0x5800)
+#define USB_DEV_FS_BASE			(PERIPH_BASE_APB1 + 0x5c00)
+#define USB_SRAM_BASE			(PERIPH_BASE_APB1 + 0x6000)
+#define CRS_BASE			(PERIPH_BASE_APB1 + 0x6C00)
+#define POWER_CONTROL_BASE		(PERIPH_BASE_APB1 + 0x7000)
+#define DAC_BASE			(PERIPH_BASE_APB1 + 0x7400)
+#define LPTIM1_BASE			(PERIPH_BASE_APB1 + 0x7c00)
+
+
+/* APB2 */
+#define SYSCFG_BASE			(PERIPH_BASE_APB2 + 0x0000)
+#define EXTI_BASE			(PERIPH_BASE_APB2 + 0x0400)
+#define TIM21_BASE			(PERIPH_BASE_APB2 + 0x0800)
+#define TIM22_BASE			(PERIPH_BASE_APB2 + 0x1400)
+#define FIREWALL_BASE			(PERIPH_BASE_APB2 + 0x1C00)
+#define ADC1_BASE			(PERIPH_BASE_APB2 + 0x2400)
+#define SPI1_BASE			(PERIPH_BASE_APB2 + 0x3000)
+#define USART1_BASE			(PERIPH_BASE_APB2 + 0x3800)
+#define DBGMCU_BASE			(PERIPH_BASE_APB2 + 0x5800)
+
+/* AHB */
+#define DMA1_BASE			(PERIPH_BASE_AHB + 0x00000)
+#define RCC_BASE			(PERIPH_BASE_AHB + 0x01000)
+#define FLASH_MEM_INTERFACE_BASE	(PERIPH_BASE_AHB + 0x02000)
+#define CRC_BASE			(PERIPH_BASE_AHB + 0x03000)
+#define TSC_BASE			(PERIPH_BASE_AHB + 0x04000)
+#define RNG_BASE			(PERIPH_BASE_AHB + 0x05000)
+#define AES_BASE			(PERIPH_BASE_AHB + 0x06000)
+
+#define GPIO_PORT_A_BASE		(IOPORT_BASE + 0x00000)
+#define GPIO_PORT_B_BASE		(IOPORT_BASE + 0x00400)
+#define GPIO_PORT_C_BASE		(IOPORT_BASE + 0x00800)
+#define GPIO_PORT_D_BASE		(IOPORT_BASE + 0x00c00)
+#define GPIO_PORT_H_BASE		(IOPORT_BASE + 0x01C00)
+
+/* Device Electronic Signature */
+#define DESIG_FLASH_SIZE_BASE		(INFO_BASE + 0x7C)
+#define DESIG_UNIQUE_ID_BASE		(INFO_BASE + 0x50)
+#define DESIG_UNIQUE_ID0		MMIO32(DESIG_UNIQUE_ID_BASE)
+#define DESIG_UNIQUE_ID1		MMIO32(DESIG_UNIQUE_ID_BASE + 4)
+#define DESIG_UNIQUE_ID2		MMIO32(DESIG_UNIQUE_ID_BASE + 0x14)
+
+/* ST provided factory calibration values @ 3.0V */
+#define ST_VREFINT_CAL			MMIO16((INFO_BASE + 0x78))
+#define ST_TSENSE_CAL1_30C		MMIO16((INFO_BASE + 0x7A))
+#define ST_TSENSE_CAL2_110C		MMIO16((INFO_BASE + 0x7E))
+
+#endif

include/libopencm3/stm32/memorymap.h

@@ -30,6 +30,8 @@
 #	include <libopencm3/stm32/f3/memorymap.h>
 #elif defined(STM32F4)
 #	include <libopencm3/stm32/f4/memorymap.h>
+#elif defined(STM32L0)
+#	include <libopencm3/stm32/l0/memorymap.h>
 #elif defined(STM32L1)
 #	include <libopencm3/stm32/l1/memorymap.h>
 #else

ld/devices.data

@@ -127,6 +127,9 @@ stm32f4[01][57]?g* stm32f4ccm ROM=1024K RAM=128K CCM=64K
 stm32f4[23][79]?g* stm32f4ccm ROM=1024K RAM=192K CCM=64K
 stm32f4[23][79]?i* stm32f4ccm ROM=2048K RAM=192K CCM=64K
 
+stm32l0???6* stm32l0 ROM=32K RAM=8K
+stm32l0???8* stm32l0 ROM=64K RAM=8K
+
 stm32l100?6* stm32l1 ROM=32K RAM=4K
 stm32l100?8* stm32l1 ROM=64K RAM=8K
 stm32l100?b* stm32l1 ROM=128K RAM=10K
@@ -334,6 +337,7 @@ stm32f1 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb -DST
 stm32f2 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb -DSTM32F2 -lopencm3_stm32f2 -msoft-float
 stm32f3 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m4 -mthumb -DSTM32F3 -lopencm3_stm32f3 -mfloat-abi=hard -mfpu=fpv4-sp-d16
 stm32f4 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m4 -mthumb -DSTM32F4 -lopencm3_stm32f4 -mfloat-abi=hard -mfpu=fpv4-sp-d16
+stm32l0 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m0 -mthumb -DSTM32L0 -lopencm3_stm32l0 -msoft-float
 stm32l1 stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb -DSTM32L1 -lopencm3_stm32l1 -msoft-float
 stm32w stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb
 stm32t stm32 ROM_OFF=0x08000000 RAM_OFF=0x20000000 -mcpu=cortex-m3 -mthumb

lib/dispatch/vector_nvic.c

@@ -8,6 +8,8 @@
 #	include "../stm32/f3/vector_nvic.c"
 #elif defined(STM32F4)
 #	include "../stm32/f4/vector_nvic.c"
+#elif defined(STM32L0)
+#	include "../stm32/l0/vector_nvic.c"
 #elif defined(STM32L1)
 #	include "../stm32/l1/vector_nvic.c"
 

lib/stm32/l0/Makefile

@@ -0,0 +1,44 @@
+##
+## This file is part of the libopencm3 project.
+##
+## Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
+##
+## This library is free software: you can redistribute it and/or modify
+## it under the terms of the GNU Lesser General Public License as published by
+## the Free Software Foundation, either version 3 of the License, or
+## (at your option) any later version.
+##
+## This library is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU Lesser General Public License for more details.
+##
+## You should have received a copy of the GNU Lesser General Public License
+## along with this library.  If not, see <http://www.gnu.org/licenses/>.
+##
+
+LIBNAME		= libopencm3_stm32l0
+SRCLIBDIR	?= ../..
+
+PREFIX		?= arm-none-eabi
+#PREFIX		?= arm-elf
+CC		= $(PREFIX)-gcc
+AR		= $(PREFIX)-ar
+CFLAGS		= -Os -g \
+		  -Wall -Wextra -Wimplicit-function-declaration \
+		  -Wredundant-decls -Wmissing-prototypes -Wstrict-prototypes \
+		  -Wundef -Wshadow \
+		  -I../../../include -fno-common \
+		  -mcpu=cortex-m0 $(FP_FLAGS) -mthumb -Wstrict-prototypes \
+		  -ffunction-sections -fdata-sections -MD -DSTM32L0
+
+ARFLAGS		= rcs
+
+OBJS		= gpio.o
+
+OBJS            += gpio_common_all.o gpio_common_f0234.o
+
+VPATH += ../../usb:../:../../cm3:../common
+
+include ../../Makefile.include
+

lib/stm32/l0/gpio.c

@@ -0,0 +1,31 @@
+/** @defgroup gpio_file GPIO
+ *
+ * @ingroup STM32L0xx
+ *
+ * @brief <b>libopencm3 STM32L0xx General Purpose I/O</b>
+ *
+ * @version 1.0.0
+ *
+ * @date 8 September 2014
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <libopencm3/stm32/gpio.h>

lib/stm32/l0/libopencm3_stm32l0.ld

@@ -0,0 +1,106 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Generic linker script for STM32 targets using libopencm3. */
+
+/* Memory regions must be defined in the ld script which includes this one. */
+
+/* Enforce emmition of the vector table. */
+EXTERN (vector_table)
+
+/* Define the entry point of the output file. */
+ENTRY(reset_handler)
+
+/* Define sections. */
+SECTIONS
+{
+	.text : {
+		*(.vectors)	/* Vector table */
+		*(.text*)	/* Program code */
+		. = ALIGN(4);
+		*(.rodata*)	/* Read-only data */
+		. = ALIGN(4);
+	} >rom
+
+	/* C++ Static constructors/destructors, also used for __attribute__
+	 * ((constructor)) and the likes */
+	.preinit_array : {
+		. = ALIGN(4);
+		__preinit_array_start = .;
+		KEEP (*(.preinit_array))
+		__preinit_array_end = .;
+	} >rom
+	.init_array : {
+		. = ALIGN(4);
+		__init_array_start = .;
+		KEEP (*(SORT(.init_array.*)))
+		KEEP (*(.init_array))
+		__init_array_end = .;
+	} >rom
+	.fini_array : {
+		. = ALIGN(4);
+		__fini_array_start = .;
+		KEEP (*(.fini_array))
+		KEEP (*(SORT(.fini_array.*)))
+		__fini_array_end = .;
+	} >rom
+
+	/*
+	 * Another section used by C++ stuff, appears when using newlib with
+	 * 64bit (long long) printf support
+	 */
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} >rom
+	.ARM.exidx : {
+		__exidx_start = .;
+		*(.ARM.exidx*)
+		__exidx_end = .;
+	} >rom
+
+	. = ALIGN(4);
+	_etext = .;
+
+	.data : {
+		_data = .;
+		*(.data*)	/* Read-write initialized data */
+		. = ALIGN(4);
+		_edata = .;
+	} >ram AT >rom
+	_data_loadaddr = LOADADDR(.data);
+
+	.bss : {
+		*(.bss*)	/* Read-write zero initialized data */
+		*(COMMON)
+		. = ALIGN(4);
+		_ebss = .;
+	} >ram
+
+	/*
+	 * The .eh_frame section appears to be used for C++ exception handling.
+	 * You may need to fix this if you're using C++.
+	 */
+	/DISCARD/ : { *(.eh_frame) }
+
+	. = ALIGN(4);
+	end = .;
+}
+
+PROVIDE(_stack = ORIGIN(ram) + LENGTH(ram));
+