UART driver and Example code for JellyBean.
This commit is contained in:
TitanMKD
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
2f425af647
commit
f8542c09a6
@@ -35,7 +35,7 @@ CFLAGS = -O2 -g3 \
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-mfloat-abi=hard -mfpu=fpv4-sp-d16 -DLPC43XX
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# ARFLAGS = rcsv
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ARFLAGS = rcs
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OBJS = gpio.o scu.o i2c.o ssp.o
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OBJS = gpio.o vector.o scu.o i2c.o ssp.o nvic.o systick.o uart.o
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VPATH += ../cm3
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264
lib/lpc43xx/uart.c
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264
lib/lpc43xx/uart.c
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@@ -0,0 +1,264 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Benjamin Vernoux <titanmkd@gmail.com>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/lpc43xx/uart.h>
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#include <libopencm3/lpc43xx/cgu.h>
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#define UART_SRC_32K 0x00
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#define UART_SRC_IRC 0x01
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#define UART_SRC_ENET_RX 0x02
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#define UART_SRC_ENET_TX 0x03
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#define UART_SRC_GP_CLKIN 0x04
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#define UART_SRC_XTAL 0x06
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#define UART_SRC_PLL0USB 0x07
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#define UART_SRC_PLL0AUDIO 0x08
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#define UART_SRC_PLL1 0x09
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#define UART_SRC_IDIVA 0x0C
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#define UART_SRC_IDIVB 0x0D
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#define UART_SRC_IDIVC 0x0E
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#define UART_SRC_IDIVD 0x0F
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#define UART_SRC_IDIVE 0x10
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#define UART_CGU_AUTOBLOCK_CLOCK_BIT 11
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#define UART_CGU_BASE_CLK_SEL_SHIFT 24 /* clock source selection (5 bits) */
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u32 dummy_read;
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/*
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* UART Init function
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*/
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void uart_init(uart_num_t uart_num,
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uart_databit_t data_nb_bits,
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uart_stopbit_t data_nb_stop,
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uart_parity_t data_parity,
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u16 uart_divisor,
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u8 uart_divaddval,
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u8 uart_mulval)
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{
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u32 lcr_config;
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u32 uart_port;
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uart_port = uart_num;
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switch(uart_num)
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{
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case UART0_NUM:
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/* use PLL1 as clock source for UART0 */
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CGU_BASE_UART0_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
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break;
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case UART1_NUM:
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/* use PLL1 as clock source for UART1 */
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CGU_BASE_UART1_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
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break;
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case UART2_NUM:
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/* use PLL1 as clock source for UART2 */
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CGU_BASE_UART2_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
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break;
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case UART3_NUM:
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/* use PLL1 as clock source for UART3 */
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CGU_BASE_UART3_CLK = (CGU_SRC_PLL1<<UART_CGU_BASE_CLK_SEL_SHIFT) | (1<<UART_CGU_AUTOBLOCK_CLOCK_BIT);
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break;
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default:
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return; /* error */
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}
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/* FIFOs RX/TX Enabled and Reset RX/TX FIFO (DMA Mode is also cleared) */
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UART_FCR(uart_port) = ( UART_FCR_FIFO_EN | UART_FCR_RX_RS | UART_FCR_TX_RS);
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/* Disable FIFO */
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UART_FCR(uart_port) = 0;
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// Dummy read (to clear existing data)
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while( UART_LSR(uart_port) & UART_LSR_RDR )
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{
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dummy_read = UART_RBR(uart_port);
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}
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/* Wait end of TX & disable TX */
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if(uart_num == UART1_NUM)
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{
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UART_TER_UART1(uart_port) = UART1_TER_TXEN;
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/* Wait for current transmit complete */
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while (!(UART_LSR(uart_port) & UART_LSR_THRE));
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/* Disable Tx */
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UART_TER_UART1(uart_port) = 0;
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}else
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{
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UART_TER(uart_port) = UART0_2_3_TER_TXEN;
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/* Wait for current transmit complete */
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while (!(UART_LSR(uart_port) & UART_LSR_THRE));
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/* Disable Tx */
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UART_TER(uart_port) = 0;
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}
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/* Disable interrupt */
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UART_IER(uart_port) = 0;
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/* Set LCR to default state */
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UART_LCR(uart_port) = 0;
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/* Set ACR to default state */
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UART_ACR(uart_port) = 0;
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/* Dummy Read to Clear Status */
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dummy_read = UART_LSR(uart_port);
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/*
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Table 835. USART Fractional Divider Register:
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UARTbaudrate = PCLK / ( 16* (((256*DLM)+ DLL)*(1+(DivAddVal/MulVal))) )
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The value of MULVAL and DIVADDVAL should comply to the following conditions:
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1. 1 <= MULVAL <= 15
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2. 0 <= DIVADDVAL <= 14
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3. DIVADDVAL < MULVAL
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*/
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/* Set DLAB Bit */
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UART_LCR(uart_port) |= UART_LCR_DLAB_EN;
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UART_DLM(uart_port) = UART_LOAD_DLM(uart_divisor);
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UART_DLL(uart_port) = UART_LOAD_DLL(uart_divisor);
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/* Clear DLAB Bit */
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UART_LCR(uart_port) &= (~UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
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UART_FDR(uart_port) = (UART_FDR_MULVAL(uart_mulval) | UART_FDR_DIVADDVAL(uart_divaddval)) & UART_FDR_BITMASK;
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/* Read LCR config & Force Enable of Divisor Latches Access */
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lcr_config = (UART_LCR(uart_port) & UART_LCR_DLAB_EN) & UART_LCR_BITMASK;
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lcr_config |= data_nb_bits; /* Set Nb Data Bits */
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lcr_config |= data_nb_stop; /* Set Nb Stop Bits */
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lcr_config |= data_parity; /* Set Data Parity */
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/* Write LCR (only 8bits) */
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UART_LCR(uart_port) = (lcr_config & UART_LCR_BITMASK);
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/* Enable TX */
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if(uart_num == UART1_NUM)
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{
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UART_TER_UART1(uart_port) = UART1_TER_TXEN;
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}else
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{
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UART_TER(uart_port) = UART0_2_3_TER_TXEN;
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}
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}
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/*
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* This Function return if data are received or not received.
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*/
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uart_rx_data_ready_t uart_rx_data_ready(uart_num_t uart_num)
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{
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u32 uart_port;
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u8 uart_status;
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uart_rx_data_ready_t data_ready;
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uart_port = uart_num;
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uart_status = UART_LSR(uart_port) & 0xFF;
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/* Check Error */
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if( (uart_status & UART_LSR_ERROR_MASK) == 0)
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{
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/* No errors check if data is ready */
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if((uart_status & UART_LSR_RDR) == 0)
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{
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data_ready = UART_RX_NO_DATA;
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}else
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{
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data_ready = UART_RX_DATA_READY;
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}
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}else
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{
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/* UART Error */
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data_ready = UART_RX_DATA_ERROR;
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}
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return data_ready;
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}
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/*
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* This Function Wait until Data RX Ready, and return Data Read from UART.
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*/
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u8 uart_read(uart_num_t uart_num)
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{
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u32 uart_port;
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u8 uart_val;
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uart_port = uart_num;
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/* Wait Until Data Received (Rx Data Not Ready) */
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while( (UART_LSR(uart_port) & UART_LSR_RDR) == 0);
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uart_val = (UART_RBR(uart_port) & UART_RBR_MASKBIT);
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return uart_val;
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}
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/*
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* This Function Wait until Data RX Ready, and return Data Read from UART.
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*/
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u8 uart_read_timeout(uart_num_t uart_num, u32 rx_timeout_nb_cycles, uart_error_t* error)
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{
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u32 uart_port;
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u8 uart_val;
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u32 counter;
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uart_port = uart_num;
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/* Wait Until Data Received (Rx Data Not Ready) */
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counter = 0;
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while( (UART_LSR(uart_port) & UART_LSR_RDR) == 0)
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{
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if(rx_timeout_nb_cycles>0)
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{
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counter++;
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if(counter>=rx_timeout_nb_cycles)
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{
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*error = UART_TIMEOUT_ERROR;
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return 0;
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}
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}
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}
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uart_val = (UART_RBR(uart_port) & UART_RBR_MASKBIT);
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/* Clear error */
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*error = UART_NO_ERROR;
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return uart_val;
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}
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/* This Function Wait Data TX Ready, and Write Data to UART
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if rx_timeout_nb_cycles = 0 Infinite wait
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*/
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void uart_write(uart_num_t uart_num, u8 data)
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{
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u32 uart_port;
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uart_port = uart_num;
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/* Wait Until FIFO not full */
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while( (UART_LSR(uart_port) & UART_LSR_THRE) == 0);
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UART_THR(uart_port) = data;
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}
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