lm4f: Implement GPIO configuration and control
Everything needed to set up and control the GPIO pins is implemented, EXCEPT setting up interrupts. This is the subject of a subsequent patch. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Alexandru Gagniuc
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
a3784aa54f
commit
f53839f33f
@@ -6,9 +6,10 @@
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2011 Gareth McMullin <gareth@blacksphere.co.nz>
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* @author @htmlonly © @endhtmlonly 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* @date 10 March 2013
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* @date 16 March 2013
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*
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* LGPL License Terms @ref lgpl_license
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*/
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@@ -69,6 +70,8 @@
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* These are usable across all GPIO registers,
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* except GPIO_LOCK and GPIO_PCTL
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* ---------------------------------------------------------------------------*/
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/** @defgroup gpio_pin_id GPIO pin identifiers
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* @{*/
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#define GPIO0 (1 << 0)
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#define GPIO1 (1 << 1)
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#define GPIO2 (1 << 2)
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@@ -78,6 +81,7 @@
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#define GPIO6 (1 << 6)
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#define GPIO7 (1 << 7)
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#define GPIO_ALL 0xff
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/** @} */
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/* =============================================================================
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* GPIO registers
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@@ -171,11 +175,157 @@
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#define GPIO_PCELL_ID2(port) MMIO32(port + 0xFF8)
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#define GPIO_PCELL_ID3(port) MMIO32(port + 0xFFC)
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/* =============================================================================
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* Convenience enums
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* ---------------------------------------------------------------------------*/
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enum gpio_mode {
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GPIO_MODE_OUTPUT, /**< Configure pin as output */
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GPIO_MODE_INPUT, /**< Configure pin as input */
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GPIO_MODE_ANALOG, /**< Configure pin as analog function */
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};
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enum gpio_pullup {
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GPIO_PUPD_NONE, /**< Do not pull the pin high or low */
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GPIO_PUPD_PULLUP, /**< Pull the pin high */
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GPIO_PUPD_PULLDOWN, /**< Pull the pin low */
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};
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enum gpio_output_type {
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GPIO_OTYPE_PP, /**< Push-pull configuration */
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GPIO_OTYPE_OD, /**< Open drain configuration */
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};
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enum gpio_drive_strength {
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GPIO_DRIVE_2MA, /**< 2mA drive */
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GPIO_DRIVE_4MA, /**< 4mA drive */
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GPIO_DRIVE_8MA, /**< 8mA drive */
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GPIO_DRIVE_8MA_SLEW_CTL,/**< 8mA drive with slew rate control */
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};
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/* =============================================================================
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* Function prototypes
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* ---------------------------------------------------------------------------*/
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BEGIN_DECLS
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void gpio_set(u32 gpioport, u8 gpios);
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void gpio_clear(u32 gpioport, u8 gpios);
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void gpio_enable_ahb_aperture(void);
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void gpio_mode_setup(u32 gpioport, enum gpio_mode mode, enum gpio_pullup pullup,
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u8 gpios);
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void gpio_set_output_config(u32 gpioport, enum gpio_output_type otype,
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enum gpio_drive_strength drive, u8 gpios);
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void gpio_set_af(u32 gpioport, u8 alt_func_num, u8 gpios);
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void gpio_toggle(u32 gpioport, u8 gpios);
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void gpio_unlock_commit(u32 gpioport, u8 gpios);
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/* Let's keep these ones inlined. GPIO control should be fast */
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/** @ingroup gpio_control
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* @{ */
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/**
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* \brief Get status of a Group of Pins (atomic)
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*
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* Reads the level of the given pins. Bit 0 of the returned data corresponds to
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* GPIO0 level, bit 1 to GPIO1 level. and so on. Bits corresponding to masked
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* pins (corresponding bit of gpios parameter set to zero) are returned as 0.
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*
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* This is an atomic operation.
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*
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* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
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* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
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* by OR'ing then together.
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*
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* @return The level of the GPIO port. The pins not specified in gpios are
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* masked to zero.
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*/
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static inline u8 gpio_read(u32 gpioport, u8 gpios)
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{
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return GPIO_DATA(gpioport)[gpios];
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}
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/**
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* \brief Set level of a Group of Pins (atomic)
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*
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* Sets the level of the given pins. Bit 0 of the data parameter corresponds to
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* GPIO0, bit 1 to GPIO1. and so on. Maskedpins (corresponding bit of gpios
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* parameter set to zero) are returned not affected.
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*
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* This is an atomic operation.
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*
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* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
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* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
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* by OR'ing then together.
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* @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit
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* 1 to GPIO1. and so on.
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*/
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static inline void gpio_write(u32 gpioport, u8 gpios, u8 data)
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{
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/* ipaddr[9:2] mask the bits to be set, hence the array index */
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GPIO_DATA(gpioport)[gpios] = data;
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}
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/**
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* \brief Set a Group of Pins (atomic)
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*
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* Set one or more pins of the given GPIO port. This is an atomic operation.
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*
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* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
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* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
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* by OR'ing then together.
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*/
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static inline void gpio_set(u32 gpioport, u8 gpios)
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{
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gpio_write(gpioport, gpios, 0xff);
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}
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/**
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* \brief Clear a Group of Pins (atomic)
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*
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* Clear one or more pins of the given GPIO port. This is an atomic operation.
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*
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* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
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* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
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* by OR'ing then together.
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*/
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static inline void gpio_clear(u32 gpioport, u8 gpios)
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{
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gpio_write(gpioport, gpios, 0);
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}
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/**
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* \brief Read level of all pins from a port (atomic)
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*
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* Read the current value of the given GPIO port. This is an atomic operation.
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*
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* This is functionally identical to @ref gpio_read (gpioport, GPIO_ALL).
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*
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* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
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*
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* @return The level of all the pins on the GPIO port.
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*/
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static inline u8 gpio_port_read(u32 gpioport)
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{
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return gpio_read(gpioport, GPIO_ALL);
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}
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/**
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* \brief Set level of of all pins from a port (atomic)
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*
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* Set the level of all pins on the given GPIO port. This is an atomic operation.
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*
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* This is functionally identical to @ref gpio_write (gpioport, GPIO_ALL, data).
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*
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* @param[in] gpioport GPIO block register address base @ref gpio_reg_base
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* @param[in] gpios @ref gpio_pin_id. Any combination of pins may be specified
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* by OR'ing then together.
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* @param[in] data Level to set pin to. Bit 0 of data corresponds to GPIO0, bit
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* 1 to GPIO1. and so on.
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*/
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static inline void gpio_port_write(u32 gpioport, u8 data)
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{
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gpio_write(gpioport, GPIO_ALL, data);
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}
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/** @} */
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END_DECLS
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