From f2a1f2b6ae3dc896d880750977b7ae26b04bd4bb Mon Sep 17 00:00:00 2001 From: dragonmux Date: Tue, 26 Sep 2023 21:42:09 +0100 Subject: [PATCH] stm32/timer: Moved the OC1 mode logic into its own function --- lib/stm32/common/timer_common_all.c | 65 ++++++++++++++++------------- 1 file changed, 35 insertions(+), 30 deletions(-) diff --git a/lib/stm32/common/timer_common_all.c b/lib/stm32/common/timer_common_all.c index 220c13fb..130b2813 100644 --- a/lib/stm32/common/timer_common_all.c +++ b/lib/stm32/common/timer_common_all.c @@ -830,6 +830,40 @@ void timer_set_oc_slow_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id) } } +void timer_set_oc1_mode(uint32_t timer_peripheral, enum tim_oc_mode oc_mode) +{ + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK; + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT; + TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK; + switch (oc_mode) { + case TIM_OCM_FROZEN: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN; + break; + case TIM_OCM_ACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE; + break; + case TIM_OCM_INACTIVE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE; + break; + case TIM_OCM_TOGGLE: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE; + break; + case TIM_OCM_FORCE_LOW: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW; + break; + case TIM_OCM_FORCE_HIGH: + TIM_CCMR1(timer_peripheral) |= + TIM_CCMR1_OC1M_FORCE_HIGH; + break; + case TIM_OCM_PWM1: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1; + break; + case TIM_OCM_PWM2: + TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2; + break; + } +} + /*---------------------------------------------------------------------------*/ /** @brief Timer Set Output Compare Mode @@ -862,36 +896,7 @@ void timer_set_oc_mode(uint32_t timer_peripheral, enum tim_oc_id oc_id, { switch (oc_id) { case TIM_OC1: - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC1S_MASK; - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_CC1S_OUT; - TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_OC1M_MASK; - switch (oc_mode) { - case TIM_OCM_FROZEN: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FROZEN; - break; - case TIM_OCM_ACTIVE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_ACTIVE; - break; - case TIM_OCM_INACTIVE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_INACTIVE; - break; - case TIM_OCM_TOGGLE: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_TOGGLE; - break; - case TIM_OCM_FORCE_LOW: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_FORCE_LOW; - break; - case TIM_OCM_FORCE_HIGH: - TIM_CCMR1(timer_peripheral) |= - TIM_CCMR1_OC1M_FORCE_HIGH; - break; - case TIM_OCM_PWM1: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM1; - break; - case TIM_OCM_PWM2: - TIM_CCMR1(timer_peripheral) |= TIM_CCMR1_OC1M_PWM2; - break; - } + timer_set_oc1_mode(timer_peripheral, oc_mode); break; case TIM_OC2: TIM_CCMR1(timer_peripheral) &= ~TIM_CCMR1_CC2S_MASK;