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stm32f3: rcc: drop useless 44MHz clock structure.

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This clock speed is not USB compatible, it's not the maximum for
anything, nor the minimum, it's just a distraction.  Drop it.
This commit is contained in:
Karl Palsson
2018-05-04 21:02:44 +00:00
parent 1e9a2e641c
commit ee8b5bf4ac
2 changed files with 0 additions and 12 deletions
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1
include/libopencm3/stm32/f3/rcc.h
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@@ -414,7 +414,6 @@ extern uint32_t rcc_apb2_frequency;
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */
enum rcc_clock { enum rcc_clock {
RCC_CLOCK_44MHZ,
RCC_CLOCK_48MHZ, RCC_CLOCK_48MHZ,
RCC_CLOCK_64MHZ, RCC_CLOCK_64MHZ,
RCC_CLOCK_END RCC_CLOCK_END

11
lib/stm32/f3/rcc.c
View File

@@ -45,17 +45,6 @@ uint32_t rcc_apb1_frequency = 8000000;
uint32_t rcc_apb2_frequency = 8000000; uint32_t rcc_apb2_frequency = 8000000;
const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = { const struct rcc_clock_scale rcc_hsi_8mhz[RCC_CLOCK_END] = {
{ /* 44MHz */
.pllmul = RCC_CFGR_PLLMUL_MUL11,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,
.hpre = RCC_CFGR_HPRE_DIV_NONE,
.ppre1 = RCC_CFGR_PPRE1_DIV_2,
.ppre2 = RCC_CFGR_PPRE2_DIV_NONE,
.flash_waitstates = 1,
.ahb_frequency = 44000000,
.apb1_frequency = 22000000,
.apb2_frequency = 44000000,
},
{ /* 48MHz */ { /* 48MHz */
.pllmul = RCC_CFGR_PLLMUL_MUL12, .pllmul = RCC_CFGR_PLLMUL_MUL12,
.pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2, .pllsrc = RCC_CFGR_PLLSRC_HSI_DIV2,