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[swo] Add/Update definitions necessary for SWO to work

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ITM Stimulus ports need to be accessible with different sizes

The amount of data written out is determined by the size of the write.
Writing a full 32 bit value when you only need 8 for printf() style
substantially reduces the available bandwidth of the SWO

Note: this is an API change for doing 32bit writes.
Old:
    ITM_STIM[stimulus_port] = value
New:
    ITM_STIM32(stimulus_port) = value

This api is much more in common with some of the other registers that
behave this way.  As there's very little (if any) code already using
this API, it's a good time to fix it permanently.

Remove misleading ITM register definitions

ITM_SSPSR is the supported parallel trace size, in _bits_
ITM_CSPSR is in _bits_ as well.  There's really no advantage in even
having these sorts of definitions in libopencm3, as these settings are
normally controlled from the debugger side, not the target itself.

Lock and lock status register definitions were added, as per ARM:
  "For ARMv7-M, the component ID registers are required for the ROM table,
   and the CoreSight management lock access mechanism is defined for the
   DWT, ITM, FPB and TPIU blocks."
This commit is contained in:
Karl Palsson
2013-11-18 17:48:29 +00:00
parent dfeeda24ba
commit ec9fc5c122
5 changed files with 32 additions and 28 deletions
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22
include/libopencm3/cm3/tpiu.h
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@@ -50,25 +50,13 @@
/* (TPIU_DEVID) */
#define TPIU_DEVID MMIO32(TPIU_BASE + 0xFC8)
/* CoreSight Lock Status Register for this peripheral */
#define TPIU_LSR MMIO32(TPIU_BASE + 0xFB4)
/* CoreSight Lock Access Register for this peripheral */
#define TPIU_LAR MMIO32(TPIU_BASE + 0xFB0)
/* TODO: PID, CID */
/* --- TPIU_SSPSR values --------------------------------------------------- */
/*
* bit[N] == 0, trace port width of (N+1) not supported
* bit[N] == 1, trace port width of (N+1) supported
*/
#define TPIU_SSPSR_BYTE (1 << 0)
#define TPIU_SSPSR_HALFWORD (1 << 1)
#define TPIU_SSPSR_WORD (1 << 3)
/* --- TPIU_SSPSR values --------------------------------------------------- */
/* Same format as TPIU_SSPSR, except only one is set */
#define TPIU_CSPSR_BYTE (1 << 0)
#define TPIU_CSPSR_HALFWORD (1 << 1)
#define TPIU_CSPSR_WORD (1 << 3)
/* --- TPIU_ACPR values ---------------------------------------------------- */
/* Bits 31:16 - Reserved */