[swo] Add/Update definitions necessary for SWO to work

ITM Stimulus ports need to be accessible with different sizes

The amount of data written out is determined by the size of the write.
Writing a full 32 bit value when you only need 8 for printf() style
substantially reduces the available bandwidth of the SWO

Note: this is an API change for doing 32bit writes.
Old:
    ITM_STIM[stimulus_port] = value
New:
    ITM_STIM32(stimulus_port) = value

This api is much more in common with some of the other registers that
behave this way.  As there's very little (if any) code already using
this API, it's a good time to fix it permanently.

Remove misleading ITM register definitions

ITM_SSPSR is the supported parallel trace size, in _bits_
ITM_CSPSR is in _bits_ as well.  There's really no advantage in even
having these sorts of definitions in libopencm3, as these settings are
normally controlled from the debugger side, not the target itself.

Lock and lock status register definitions were added, as per ARM:
  "For ARMv7-M, the component ID registers are required for the ROM table,
   and the CoreSight management lock access mechanism is defined for the
   DWT, ITM, FPB and TPIU blocks."

include/libopencm3/cm3/fpb.h

@@ -40,6 +40,12 @@
 /* Flash Patch Comparator (FPB_COMPx) */
 #define FPB_COMP			(&MMIO32(FPB_BASE + 8))
 
+/* CoreSight Lock Status Register for this peripheral */
+#define FPB_LSR				MMIO32(FPB_BASE + 0xFB4)
+/* CoreSight Lock Access Register for this peripheral */
+#define FPB_LAR				MMIO32(FPB_BASE + 0xFB0)
+
+
 /* TODO: PID, CID */
 
 /* --- FPB_CTRL values ----------------------------------------------------- */