stm32f4: rcc: add plli2s config function

lib/stm32/f4/rcc.c

@@ -542,6 +542,18 @@ void rcc_css_disable(void)
 	RCC_CR &= ~RCC_CR_CSSON;
 }
 
+/**
+ * Set the dividers for the PLLI2S clock outputs
+ * @param n valid range depends on target device, check your RefManual.
+ * @param r valid range is 2..7
+ */
+void rcc_plli2s_config(uint16_t n, uint8_t r)
+{
+	RCC_PLLI2SCFGR = (
+	  ((n & RCC_PLLI2SCFGR_PLLI2SN_MASK) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) |
+	  ((r & RCC_PLLI2SCFGR_PLLI2SR_MASK) << RCC_PLLI2SCFGR_PLLI2SR_SHIFT));
+}
+
 /**
  * Set the dividers for the PLLSAI clock outputs
  * divider p is only available on F4x9 parts, pass 0 for other parts.