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Fix STM32H7 FDCAN FIFO acknowledgment process

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Fix FDCAN FIFO acknowledge register definition to make it correct for H7
MCUs. Previous definition contained hardcoded offset instead of using
MCU-specific macro.

Fix incorrect decoding of buffer element size. During decoding, value
returned was erratically set to 7 instead of setting 4th LSB. Buffer
element size was then always reported as 15 bytes.
This commit is contained in:
Eduard Drusa
2021-05-18 15:34:04 +02:00
committed by Karl Palsson
parent 9478931d69
commit e9c68ff9e8
2 changed files with 6 additions and 4 deletions
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4
include/libopencm3/stm32/fdcan.h
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@@ -78,7 +78,9 @@
* @param can_base FDCAN block base address @ref fdcan_block
* @param fifo_id ID of FIFO, 0 or 1
*/
#define FDCAN_RXFIA(can_base, fifo_id) MMIO32(can_base + 0x0094 + (FDCAN_RXFI_OFFSET * fifo_id))
#define FDCAN_RXFIA(can_base, fifo_id) \
MMIO32(can_base + FDCAN_RXFIA_BASE + (FDCAN_RXFI_OFFSET * fifo_id))
#define FDCAN_RXF0A(can_base) FDCAN_RXFIA(can_base, 0)
#define FDCAN_RXF1A(can_base) FDCAN_RXFIA(can_base, 1)