[Cortex] Add preliminary support for core-dependent defines ARMv6m / ARMv7m, ARMv7em
This commit is contained in:
BuFran
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
2a588f11aa
commit
e1ebcc9da8
@@ -22,6 +22,11 @@
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/* Cortex-M3 Flash Patch and Breakpoint (FPB) unit */
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/* Those defined only on ARMv7 and above */
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#if !defined(__ARM_ARCH_7M__) || !defined(__ARM_ARCH_7EM__)
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#error "Flash Patch and Breakpoint not available in CM0"
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#endif
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/* Note: We always use "FPB" as abbreviation, docs sometimes use only "FP". */
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/* --- FPB registers ------------------------------------------------------- */
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@@ -22,6 +22,11 @@
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/* Cortex-M3 Instrumentation Trace Macrocell (ITM) */
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/* Those defined only on ARMv7 and above */
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#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
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#error "Instrumentation Trace Macrocell not available in CM0"
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#endif
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/* --- ITM registers ------------------------------------------------------- */
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/* Stimulus Port x (ITM_STIM[x]) */
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@@ -20,17 +20,33 @@
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#ifndef LIBOPENCM3_CM3_MEMORYMAP_H
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#define LIBOPENCM3_CM3_MEMORYMAP_H
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/* --- ARM Cortex-M3 specific definitions ---------------------------------- */
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/* --- ARM Cortex-M0, M3 and M4 specific definitions ----------------------- */
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/* Private peripheral bus - Internal */
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#define PPBI_BASE 0xE0000000
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* ITM: Instrumentation Trace Macrocell */
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#define ITM_BASE (PPBI_BASE + 0x0000)
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/* DWT: Data Watchpoint and Trace unit */
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#define DWT_BASE (PPBI_BASE + 0x1000)
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/* FPB: Flash Patch and Breakpoint unit */
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#define FPB_BASE (PPBI_BASE + 0x2000)
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#endif
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/* PPBI_BASE + 0x3000 (0xE000 3000 - 0xE000 DFFF): Reserved */
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#define SCS_BASE (PPBI_BASE + 0xE000)
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/* PPBI_BASE + 0xF000 (0xE000 F000 - 0xE003 FFFF): Reserved */
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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#define TPIU_BASE (PPBI_BASE + 0x40000)
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#endif
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/* --- ITM: Instrumentation Trace Macrocell --- */
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/* TODO */
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@@ -43,17 +59,38 @@
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/* --- SCS: System Control Space --- */
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* ITR: Interrupt Type Register */
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#define ITR_BASE (SCS_BASE + 0x0000)
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#endif
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/* SYS_TICK: System Timer */
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#define SYS_TICK_BASE (SCS_BASE + 0x0010)
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/* NVIC: Nested Vector Interrupt Controller */
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#define NVIC_BASE (SCS_BASE + 0x0100)
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/* SCB: System Control Block */
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#define SCB_BASE (SCS_BASE + 0x0D00)
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#ifdef CM0_PLUS
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/* MPU: Memory protection unit */
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#define MPU_BASE (SCS_BASE + 0x0D90)
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#endif
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/* Those defined only on CM0*/
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#if defined(__ARM_ARCH_6M__)
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/* DEBUG: Debug control and configuration */
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#define DEBUG_BASE (SCS_BASE + 0x0DF0)
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#endif
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* STE: Software Trigger Interrupt Register */
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#define STIR_BASE (SCS_BASE + 0x0F00)
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/* ID: ID space */
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#define ID_BASE (SCS_BASE + 0x0FD0)
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#endif
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#endif
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110
include/libopencm3/cm3/mpu.h
Normal file
110
include/libopencm3/cm3/mpu.h
Normal file
@@ -0,0 +1,110 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef LIBOPENCM3_CM0_MPU_H
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#define LIBOPENCM3_CM0_MPU_H
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#ifndef CM0_PLUS
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#error "mpu is supported only on CM0+ architecture"
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#else
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#include <libopencm3/cm0/memorymap.h>
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#include <libopencm3/cm0/common.h>
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/* --- SCB: Registers ------------------------------------------------------ */
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#define MPU_TYPE MMIO32(MPU_BASE + 0x00)
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#define MPU_CTRL MMIO32(MPU_BASE + 0x04)
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#define MPU_RNR MMIO32(MPU_BASE + 0x08)
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#define MPU_RBAR MMIO32(MPU_BASE + 0x0C)
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#define MPU_RASR MMIO32(MPU_BASE + 0x10)
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/* --- MPU values ---------------------------------------------------------- */
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/* --- MPU_TYPE values ----------------------------------------------------- */
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#define MPU_TYPE_IREGION_LSB 16
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#define MPU_TYPE_IREGION (0xFF << MPU_TYPE_IREGION_LSB)
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#define MPU_TYPE_DREGION_LSB 8
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#define MPU_TYPE_DREGION (0xFF << MPU_TYPE_DREGION_LSB)
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#define MPU_TYPE_SEPARATE (1<<0)
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/* --- MPU_CTRL values ----------------------------------------------------- */
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#define MPU_CTRL_PRIVDEFENA (1<<2)
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#define MPU_CTRL_HFNMIENA (1<<1)
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#define MPU_CTRL_ENABLE (1<<0)
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/* --- MPU_RNR values ------------------------------------------------------ */
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#define MPU_RNR_REGION_LSB 0
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#define MPU_RNR_REGION (0xFF << MPU_RNR_REGION_LSB)
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/* --- MPU_RBAR values ----------------------------------------------------- */
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#define MPU_RBAR_ADDR_LSB 8
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#define MPU_RBAR_ADDR (0x00FFFFFF << MPU_RBAR_REGION_LSB)
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#define MPU_RBAR_VALID (1<<4)
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#define MPU_RBAR_REGION_LSB 0
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#define MPU_RBAR_REGION (0xF << MPU_RBAR_REGION_LSB)
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/* --- MPU_RASR values ----------------------------------------------------- */
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#define MPU_RASR_ATTRS_LSB 16
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#define MPU_RASR_ATTRS (0xFFFF << MPU_RASR_ATTRS_LSB)
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#define MPU_RASR_SRD_LSB 8
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#define MPU_RASR_SRD (0xFF << MPU_RASR_SRD_LSB)
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#define MPU_RASR_SIZE_LSB 1
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#define MPU_RASR_SIZE (0x1F << MPU_RASR_SIZE_LSB)
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#define MPU_RASR_ENABLE (1 << 0)
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#define MPU_RASR_ATTR_XN (1 << 28)
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#define MPU_RASR_ATTR_AP (7 << 24)
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#define MPU_RASR_ATTR_AP_PNO_UNO (0 << 24)
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#define MPU_RASR_ATTR_AP_PRW_UNO (1 << 24)
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#define MPU_RASR_ATTR_AP_PRW_URO (2 << 24)
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#define MPU_RASR_ATTR_AP_PRW_URW (3 << 24)
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#define MPU_RASR_ATTR_AP_PRO_UNO (5 << 24)
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#define MPU_RASR_ATTR_AP_PRO_URO (6 << 24)
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#define MPU_RASR_ATTR_AP_PRO_URO (7 << 24)
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#define MPU_RASR_ATTR_TEX (7 << 19)
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#define MPU_RASR_ATTR_S (1 << 18)
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#define MPU_RASR_ATTR_C (1 << 17)
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#define MPU_RASR_ATTR_B (1 << 16)
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#define MPU_RASR_ATTR_SCB (7 << 16)
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#define MPU_RASR_ATTR_SCB_SH_STRONG (0 << 16)
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#define MPU_RASR_ATTR_SCB_SH_DEVICE (1 << 16)
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#define MPU_RASR_ATTR_SCB_NSH_WT (2 << 16)
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#define MPU_RASR_ATTR_SCB_NSH_WB (3 << 16)
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#define MPU_RASR_ATTR_SCB_SH_STRONG (4 << 16)
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#define MPU_RASR_ATTR_SCB_SH_DEVICE (5 << 16)
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#define MPU_RASR_ATTR_SCB_SH_WT (6 << 16)
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#define MPU_RASR_ATTR_SCB_SH_WB (7 << 16)
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/* --- MPU functions ------------------------------------------------------- */
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BEGIN_DECLS
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END_DECLS
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#endif /* CM0_PLUS */
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#endif
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@@ -19,18 +19,18 @@
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/** @defgroup CM3_nvic_defines NVIC Defines
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@brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
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@ingroup CM3_defines
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
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@date 18 August 2012
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LGPL License Terms @ref lgpl_license
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*
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* @brief <b>libopencm3 Cortex Nested Vectored Interrupt Controller</b>
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*
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* @ingroup CM3_defines
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*
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* @version 1.0.0
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*
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* @author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
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*
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* @date 18 August 2012
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/**@{*/
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@@ -44,6 +44,7 @@ LGPL License Terms @ref lgpl_license
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/* ISER: Interrupt Set Enable Registers */
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/* Note: 8 32bit Registers */
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/* Note: Single register on CM0 */
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#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \
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(iser_id * 4))
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@@ -51,6 +52,7 @@ LGPL License Terms @ref lgpl_license
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/* ICER: Interrupt Clear Enable Registers */
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/* Note: 8 32bit Registers */
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/* Note: Single register on CM0 */
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#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \
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(icer_id * 4))
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@@ -58,6 +60,7 @@ LGPL License Terms @ref lgpl_license
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/* ISPR: Interrupt Set Pending Registers */
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/* Note: 8 32bit Registers */
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/* Note: Single register on CM0 */
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#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \
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(ispr_id * 4))
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@@ -65,42 +68,59 @@ LGPL License Terms @ref lgpl_license
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/* ICPR: Interrupt Clear Pending Registers */
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/* Note: 8 32bit Registers */
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/* Note: Single register on CM0 */
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#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \
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(icpr_id * 4))
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/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* IABR: Interrupt Active Bit Register */
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/* Note: 8 32bit Registers */
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#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \
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(iabr_id * 4))
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#endif
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/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
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/* IPR: Interrupt Priority Registers */
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/* Note: 240 8bit Registers */
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/* Note: 32 8bit Registers on CM0 */
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#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \
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ipr_id)
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* STIR: Software Trigger Interrupt Register */
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#define NVIC_STIR MMIO32(STIR_BASE)
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#endif
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/* --- IRQ channel numbers-------------------------------------------------- */
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/* Cortex M3 and M4 System Interrupts */
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/** @defgroup nvic_sysint Cortex M3/M4 System Interrupts
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/* Cortex M0, M3 and M4 System Interrupts */
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/** @defgroup nvic_sysint Cortex M0/M3/M4 System Interrupts
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@ingroup CM3_nvic_defines
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IRQ numbers -3 and -6 to -9 are reserved
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@{*/
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#define NVIC_NMI_IRQ -14
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#define NVIC_HARD_FAULT_IRQ -13
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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#define NVIC_MEM_MANAGE_IRQ -12
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#define NVIC_BUS_FAULT_IRQ -11
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#define NVIC_USAGE_FAULT_IRQ -10
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#endif
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/* irq numbers -6 to -9 are reserved */
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#define NVIC_SV_CALL_IRQ -5
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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#define DEBUG_MONITOR_IRQ -4
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#endif
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/* irq number -3 reserved */
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#define NVIC_PENDSV_IRQ -2
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#define NVIC_SYSTICK_IRQ -1
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@@ -123,21 +143,29 @@ void nvic_disable_irq(uint8_t irqn);
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uint8_t nvic_get_pending_irq(uint8_t irqn);
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void nvic_set_pending_irq(uint8_t irqn);
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void nvic_clear_pending_irq(uint8_t irqn);
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uint8_t nvic_get_active_irq(uint8_t irqn);
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uint8_t nvic_get_irq_enabled(uint8_t irqn);
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void nvic_set_priority(uint8_t irqn, uint8_t priority);
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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uint8_t nvic_get_active_irq(uint8_t irqn);
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void nvic_generate_software_interrupt(uint16_t irqn);
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#endif
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void WEAK reset_handler(void);
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void WEAK nmi_handler(void);
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void WEAK hard_fault_handler(void);
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void WEAK sv_call_handler(void);
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void WEAK pend_sv_handler(void);
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void WEAK sys_tick_handler(void);
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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void WEAK mem_manage_handler(void);
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void WEAK bus_fault_handler(void);
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void WEAK usage_fault_handler(void);
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void WEAK sv_call_handler(void);
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void WEAK debug_monitor_handler(void);
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void WEAK pend_sv_handler(void);
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void WEAK sys_tick_handler(void);
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#endif
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END_DECLS
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@@ -51,6 +51,8 @@
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#define SCB_SHPR2 MMIO8(SCB_BASE + 0x18 + 2)
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#define SCB_SHPR3 MMIO8(SCB_BASE + 0x18 + 3)
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/* Those defined only on ARMv7 and above */
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#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
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/* SHCSR: System Handler Control and State Register */
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#define SCB_SHCSR MMIO32(SCB_BASE + 0x24)
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@@ -128,61 +130,96 @@
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/* MVFR1: Media and Floating-Point Feature Register 1 */
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#define SCB_MVFR1 MMIO32(SCB_BASE + 0x244)
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#endif
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/* --- SCB values ---------------------------------------------------------- */
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/* --- SCB_CPUID values ---------------------------------------------------- */
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/* Implementer[31:24]: Implementer code */
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#define SCP_CPUID_IMPLEMENTER_LSB 24
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#define SCB_CPUID_IMPLEMENTER_LSB 24
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#define SCB_CPUID_IMPLEMENTER (0xFF << SCB_CPUID_IMPLEMENTER_LSB)
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/* Variant[23:20]: Variant number */
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#define SCP_CPUID_VARIANT_LSB 20
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/* Constant[19:16]: Reads as 0xF */
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#define SCP_CPUID_CONSTANT_LSB 16
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#define SCB_CPUID_VARIANT_LSB 20
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#define SCB_CPUID_VARIANT (0xF << SCB_CPUID_VARIANT_LSB)
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/* Constant[19:16]: Reads as 0xF (ARMv7-M) M3, M4 */
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/* Constant[19:16]: Reads as 0xC (ARMv6-M) M0, M0+ */
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#define SCB_CPUID_CONSTANT_LSB 16
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#define SCB_CPUID_CONSTANT (0xF << SCB_CPUID_CONSTANT_LSB)
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#define SCB_CPUID_CONSTANT_ARMV6 (0xC << SCB_CPUID_CONSTANT_LSB)
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#define SCB_CPUID_CONSTANT_ARMV7 (0xF << SCB_CPUID_CONSTANT_LSB)
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/* PartNo[15:4]: Part number of the processor */
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#define SCP_CPUID_PARTNO_LSB 4
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#define SCB_CPUID_PARTNO_LSB 4
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#define SCB_CPUID_PARTNO (0xFFF << SCB_CPUID_PARTNO_LSB)
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/* Revision[3:0]: Revision number */
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#define SCP_CPUID_REVISION_LSB 0
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#define SCB_CPUID_REVISION_LSB 0
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#define SCB_CPUID_REVISION (0xF << SCB_CPUID_REVISION_LSB)
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/* --- SCB_ICSR values ----------------------------------------------------- */
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/* NMIPENDSET: NMI set-pending bit */
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#define SCB_ICSR_NMIPENDSET (1 << 31)
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#define SCB_ICSR_NMIPENDSET (1 << 31)
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/* Bits [30:29]: reserved - must be kept cleared */
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/* PENDSVSET: PendSV set-pending bit */
|
||||
#define SCB_ICSR_PENDSVSET (1 << 28)
|
||||
#define SCB_ICSR_PENDSVSET (1 << 28)
|
||||
/* PENDSVCLR: PendSV clear-pending bit */
|
||||
#define SCB_ICSR_PENDSVCLR (1 << 27)
|
||||
#define SCB_ICSR_PENDSVCLR (1 << 27)
|
||||
/* PENDSTSET: SysTick exception set-pending bit */
|
||||
#define SCB_ICSR_PENDSTSET (1 << 26)
|
||||
#define SCB_ICSR_PENDSTSET (1 << 26)
|
||||
/* PENDSTCLR: SysTick exception clear-pending bit */
|
||||
#define SCB_ICSR_PENDSTCLR (1 << 25)
|
||||
#define SCB_ICSR_PENDSTCLR (1 << 25)
|
||||
/* Bit 24: reserved - must be kept cleared */
|
||||
/* Bit 23: reserved for debug - reads as 0 when not in debug mode */
|
||||
#define SCB_ICSR_ISRPREEMPT (1 << 23)
|
||||
/* ISRPENDING: Interrupt pending flag, excluding NMI and Faults */
|
||||
#define SCB_ICSR_ISRPENDING (1 << 22)
|
||||
#define SCB_ICSR_ISRPENDING (1 << 22)
|
||||
/* VECTPENDING[21:12] Pending vector */
|
||||
#define SCB_ICSR_VECTPENDING_LSB 12
|
||||
#define SCB_ICSR_VECTPENDING_LSB 12
|
||||
#define SCB_ICSR_VECTPENDING (0x1FF << SCB_ICSR_VECTPENDING_LSB)
|
||||
/* RETOBASE: Return to base level */
|
||||
#define SCB_ICSR_RETOBASE (1 << 11)
|
||||
#define SCB_ICSR_RETOBASE (1 << 11)
|
||||
/* Bits [10:9]: reserved - must be kept cleared */
|
||||
/* VECTACTIVE[8:0] Active vector */
|
||||
#define SCB_ICSR_VECTACTIVE_LSB 0
|
||||
#define SCB_ICSR_VECTACTIVE_LSB 0
|
||||
#define SCB_ICSR_VECTACTIVE (0x1FF << SCB_ICSR_VECTACTIVE_LSB)
|
||||
|
||||
|
||||
/* --- SCB_VTOR values ----------------------------------------------------- */
|
||||
|
||||
/* IMPLEMENTATION DEFINED */
|
||||
|
||||
#if defined(__ARM_ARCH_6M__)
|
||||
|
||||
#define SCB_VTOR_TBLOFF_LSB 7
|
||||
#define SCB_VTOR_TBLOFF (0x1FFFFFF << SCB_VTOR_TBLOFF_LSB)
|
||||
|
||||
#elif defined(CM1)
|
||||
/* VTOR not defined there */
|
||||
|
||||
#elif defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
|
||||
/* Bits [31:30]: reserved - must be kept cleared */
|
||||
/* TBLOFF[29:9]: Vector table base offset field */
|
||||
/* inconsistent datasheet - LSB could be 11 */
|
||||
#define SCB_VTOR_TBLOFF_LSB 9
|
||||
/* BUG: TBLOFF is in the ARMv6 Architecture reference manual defined from b7 */
|
||||
#define SCB_VTOR_TBLOFF_LSB 9
|
||||
#define SCB_VTOR_TBLOFF (0x7FFFFF << SCB_VTOR_TBLOFF_LSB)
|
||||
|
||||
#endif
|
||||
|
||||
/* --- SCB_AIRCR values ---------------------------------------------------- */
|
||||
|
||||
/* VECTKEYSTAT[31:16]/ VECTKEY[31:16] Register key */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_LSB 16
|
||||
#define SCB_AIRCR_VECTKEY 0x05FA0000
|
||||
#define SCB_AIRCR_VECTKEYSTAT_LSB 16
|
||||
#define SCB_AIRCR_VECTKEYSTAT (0xFFFF << SCB_AIRCR_VECTKEYSTAT_LSB)
|
||||
#define SCB_AIRCR_VECTKEY (0x05FA << SCB_AIRCR_VECTKEYSTAT_LSB)
|
||||
|
||||
/* ENDIANESS Data endianness bit */
|
||||
#define SCB_AIRCR_ENDIANESS (1 << 15)
|
||||
|
||||
/* Those defined only on ARMv7 and above */
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
/* Bits [14:11]: reserved - must be kept cleared */
|
||||
/* PRIGROUP[10:8]: Interrupt priority grouping field */
|
||||
#define SCB_AIRCR_PRIGROUP_GROUP16_NOSUB (0x3 << 8)
|
||||
@@ -193,12 +230,18 @@
|
||||
#define SCB_AIRCR_PRIGROUP_MASK (0x7 << 8)
|
||||
#define SCB_AIRCR_PRIGROUP_SHIFT 8
|
||||
/* Bits [7:3]: reserved - must be kept cleared */
|
||||
#endif
|
||||
|
||||
/* SYSRESETREQ System reset request */
|
||||
#define SCB_AIRCR_SYSRESETREQ (1 << 2)
|
||||
/* VECTCLRACTIVE */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE (1 << 1)
|
||||
|
||||
/* Those defined only on ARMv7 and above */
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
/* VECTRESET */
|
||||
#define SCB_AIRCR_VECTRESET (1 << 0)
|
||||
#endif
|
||||
|
||||
/* --- SCB_SCR values ------------------------------------------------------ */
|
||||
|
||||
@@ -217,18 +260,27 @@
|
||||
/* Bits [31:10]: reserved - must be kept cleared */
|
||||
/* STKALIGN */
|
||||
#define SCB_CCR_STKALIGN (1 << 9)
|
||||
|
||||
/* Those defined only on ARMv7 and above */
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
/* BFHFNMIGN */
|
||||
#define SCB_CCR_BFHFNMIGN (1 << 8)
|
||||
/* Bits [7:5]: reserved - must be kept cleared */
|
||||
/* DIV_0_TRP */
|
||||
#define SCB_CCR_DIV_0_TRP (1 << 4)
|
||||
#endif
|
||||
|
||||
/* UNALIGN_TRP */
|
||||
#define SCB_CCR_UNALIGN_TRP (1 << 3)
|
||||
|
||||
/* Those defined only on ARMv7 and above */
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
/* Bit 2: reserved - must be kept cleared */
|
||||
/* USERSETMPEND */
|
||||
#define SCB_CCR_USERSETMPEND (1 << 1)
|
||||
/* NONBASETHRDENA */
|
||||
#define SCB_CCR_NONBASETHRDENA (1 << 0)
|
||||
#endif
|
||||
|
||||
/* --- SCB_SHPR1 values ---------------------------------------------------- */
|
||||
|
||||
@@ -254,6 +306,8 @@
|
||||
#define SCB_SHPR3_PRI_14_LSB 16
|
||||
/* Bits [15:0]: reserved - must be kept cleared */
|
||||
|
||||
/* Those defined only on ARMv7 and above */
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
/* --- SCB_SHCSR values ---------------------------------------------------- */
|
||||
|
||||
/* Bits [31:19]: reserved - must be kept cleared */
|
||||
@@ -361,6 +415,7 @@
|
||||
#define SCB_CPACR_CP10 (1 << 20)
|
||||
/* CPACR [22:23]: Access privileges for coprocessor 11 */
|
||||
#define SCB_CPACR_CP11 (1 << 22)
|
||||
#endif
|
||||
|
||||
/* --- SCB functions ------------------------------------------------------- */
|
||||
|
||||
@@ -383,11 +438,13 @@ struct scb_exception_stack_frame {
|
||||
: [frameptr]"=r" (f)); \
|
||||
} while (0)
|
||||
|
||||
void scb_reset_core(void) __attribute__((noreturn, naked));
|
||||
void scb_reset_system(void) __attribute__((noreturn, naked));
|
||||
void scb_set_priority_grouping(uint32_t prigroup);
|
||||
|
||||
/* TODO: */
|
||||
/* Those defined only on ARMv7 and above */
|
||||
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
|
||||
void scb_reset_core(void) __attribute__((noreturn, naked));
|
||||
void scb_set_priority_grouping(uint32_t prigroup);
|
||||
#endif
|
||||
|
||||
END_DECLS
|
||||
|
||||
|
||||
@@ -22,6 +22,8 @@
|
||||
|
||||
#include "common.h"
|
||||
|
||||
void __dmb(void);
|
||||
|
||||
/* Implements synchronisation primitives as discussed in the ARM document
|
||||
* DHT0008A (ID081709) "ARM Synchronization Primitives" and the ARM v7-M
|
||||
* Architecture Reference Manual.
|
||||
@@ -29,9 +31,11 @@
|
||||
|
||||
/* --- Exclusive load and store instructions ------------------------------- */
|
||||
|
||||
/* Those are defined only on CM3 or CM4 */
|
||||
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
|
||||
|
||||
uint32_t __ldrex(volatile uint32_t *addr);
|
||||
uint32_t __strex(uint32_t val, volatile uint32_t *addr);
|
||||
void __dmb(void);
|
||||
|
||||
/* --- Convenience functions ----------------------------------------------- */
|
||||
|
||||
@@ -46,3 +50,5 @@ void mutex_lock(mutex_t *m);
|
||||
void mutex_unlock(mutex_t *m);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
@@ -18,18 +18,24 @@
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
/** @defgroup CM3_systick_defines SysTick Defines
|
||||
*
|
||||
* @brief <b>libopencm3 Defined Constants and Types for the Cortex SysTick </b>
|
||||
*
|
||||
* @ingroup CM3_defines
|
||||
*
|
||||
* @version 1.0.0
|
||||
*
|
||||
* @author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||
*
|
||||
* @date 19 August 2012
|
||||
*
|
||||
* LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
@brief <b>libopencm3 Defined Constants and Types for the Cortex SysTick </b>
|
||||
|
||||
@ingroup CM3_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||
|
||||
@date 19 August 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
/**
|
||||
* @note this file has been not following the register naming scheme, the
|
||||
* correct names defined, and the old ones stay there for compatibility with
|
||||
* old software (will be deprecated in the future)
|
||||
*/
|
||||
|
||||
/**@{*/
|
||||
@@ -44,44 +50,64 @@ LGPL License Terms @ref lgpl_license
|
||||
|
||||
/* Control and status register (STK_CTRL) */
|
||||
#define STK_CTRL MMIO32(SYS_TICK_BASE + 0x00)
|
||||
#define STK_CSR MMIO32(SYS_TICK_BASE + 0x00)
|
||||
|
||||
/* reload value register (STK_LOAD) */
|
||||
#define STK_LOAD MMIO32(SYS_TICK_BASE + 0x04)
|
||||
#define STK_RVR MMIO32(SYS_TICK_BASE + 0x04)
|
||||
|
||||
/* current value register (STK_VAL) */
|
||||
#define STK_VAL MMIO32(SYS_TICK_BASE + 0x08)
|
||||
#define STK_CVR MMIO32(SYS_TICK_BASE + 0x08)
|
||||
|
||||
/* calibration value register (STK_CALIB) */
|
||||
#define STK_CALIB MMIO32(SYS_TICK_BASE + 0x0C)
|
||||
|
||||
/* --- STK_CTRL values ----------------------------------------------------- */
|
||||
/* --- STK_CSR values ------------------------------------------------------ */
|
||||
/* Bits [31:17] Reserved, must be kept cleared. */
|
||||
/* COUNTFLAG: */
|
||||
#define STK_CTRL_COUNTFLAG (1 << 16)
|
||||
#define STK_CSR_COUNTFLAG (1 << 16)
|
||||
|
||||
/* Bits [15:3] Reserved, must be kept cleared. */
|
||||
/* CLKSOURCE: Clock source selection */
|
||||
#define STK_CTRL_CLKSOURCE (1 << 2)
|
||||
#define STK_CTRL_CLKSOURCE_LSB 2
|
||||
#define STK_CTRL_CLKSOURCE (1 << STK_CTRL_CLKSOURCE_LSB)
|
||||
|
||||
#define STK_CSR_CLKSOURCE_LSB 2
|
||||
#define STK_CSR_CLKSOURCE (1 << STK_CSR_CLKSOURCE_LSB)
|
||||
|
||||
/** @defgroup systick_clksource Clock source selection
|
||||
@ingroup CM3_systick_defines
|
||||
|
||||
@{*/
|
||||
#define STK_CTRL_CLKSOURCE_AHB_DIV8 0
|
||||
#define STK_CTRL_CLKSOURCE_AHB 1
|
||||
#if defined(__ARM_ARCH_6M__)
|
||||
#define STK_CSR_CLKSOURCE_EXT (0 << STK_CSR_CLKSOURCE_LSB)
|
||||
#define STK_CSR_CLKSOURCE_AHB (1 << STK_CSR_CLKSOURCE_LSB)
|
||||
#else
|
||||
#define STK_CTRL_CLKSOURCE_AHB_DIV8 (0 << STK_CTRL_CLKSOURCE_LSB)
|
||||
#define STK_CTRL_CLKSOURCE_AHB (1 << STK_CTRL_CLKSOURCE_LSB)
|
||||
#endif
|
||||
/**@}*/
|
||||
|
||||
/* TICKINT: SysTick exception request enable */
|
||||
#define STK_CTRL_TICKINT (1 << 1)
|
||||
#define STK_CSR_TICKINT (1 << 1)
|
||||
/* ENABLE: Counter enable */
|
||||
#define STK_CTRL_ENABLE (1 << 0)
|
||||
#define STK_CSR_ENABLE (1 << 0)
|
||||
|
||||
/* --- STK_LOAD values ----------------------------------------------------- */
|
||||
/* --- STK_RVR values ------------------------------------------------------ */
|
||||
/* Bits [31:24] Reserved, must be kept cleared. */
|
||||
/* RELOAD[23:0]: RELOAD value */
|
||||
#define STK_RVR_RELOAD 0x00FFFFFF
|
||||
|
||||
/* --- STK_VAL values ------------------------------------------------------ */
|
||||
|
||||
/* --- STK_CVR values ------------------------------------------------------ */
|
||||
/* Bits [31:24] Reserved, must be kept cleared. */
|
||||
/* CURRENT[23:0]: Current counter value */
|
||||
#define STK_CVR_CURRENT 0x00FFFFFF
|
||||
|
||||
|
||||
/* --- STK_CALIB values ---------------------------------------------------- */
|
||||
/* NOREF: NOREF flag */
|
||||
@@ -90,6 +116,7 @@ LGPL License Terms @ref lgpl_license
|
||||
#define STK_CALIB_SKEW (1 << 30)
|
||||
/* Bits [29:24] Reserved, must be kept cleared. */
|
||||
/* TENMS[23:0]: Calibration value */
|
||||
#define STK_CALIB_TENMS 0x00FFFFFF
|
||||
|
||||
/* --- Function Prototypes ------------------------------------------------- */
|
||||
|
||||
|
||||
@@ -22,6 +22,11 @@
|
||||
|
||||
/* Cortex-M3 Trace Port Interface Unit (TPIU) */
|
||||
|
||||
/* Those defined only on ARMv7 and above */
|
||||
#if !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__)
|
||||
#error "Trace Port Interface Unit not available in CM0"
|
||||
#endif
|
||||
|
||||
/* --- TPIU registers ------------------------------------------------------ */
|
||||
|
||||
/* Supported Synchronous Port Size (TPIU_SSPSR) */
|
||||
|
||||
@@ -49,12 +49,12 @@ typedef struct {
|
||||
vector_table_entry_t reset;
|
||||
vector_table_entry_t nmi;
|
||||
vector_table_entry_t hard_fault;
|
||||
vector_table_entry_t memory_manage_fault;
|
||||
vector_table_entry_t bus_fault;
|
||||
vector_table_entry_t usage_fault;
|
||||
vector_table_entry_t memory_manage_fault; /* not in CM0 */
|
||||
vector_table_entry_t bus_fault; /* not in CM0 */
|
||||
vector_table_entry_t usage_fault; /* not in CM0 */
|
||||
vector_table_entry_t reserved_x001c[4];
|
||||
vector_table_entry_t sv_call;
|
||||
vector_table_entry_t debug_monitor;
|
||||
vector_table_entry_t debug_monitor; /* not in CM0 */
|
||||
vector_table_entry_t reserved_x0034;
|
||||
vector_table_entry_t pend_sv;
|
||||
vector_table_entry_t systick;
|
||||
|
||||
Reference in New Issue
Block a user