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doxygen: fix many warnings on "end of file while in group"

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This commit is contained in:
Karl Palsson
2020-12-10 21:51:48 +00:00
parent 6f81e49290
commit e07f23bb70
13 changed files with 33 additions and 31 deletions
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2
include/libopencm3/stm32/common/dac_common_all.h
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@@ -388,7 +388,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
/** DAC channel 2 DMA underrun flag */
#define DAC_SR_DMAUDR2 (1 << 29)
/*@}*/
/**@}*/
/** DAC channel identifier */
typedef enum {

2
include/libopencm3/stm32/common/iwdg_common_all.h
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@@ -97,7 +97,7 @@ specific memorymap.h header before including this header file.*/
/** PVU: Watchdog prescaler value update */
#define IWDG_SR_PVU (1 << 0)
/*@}*/
/**@}*/
/* --- IWDG function prototypes---------------------------------------------- */

26
include/libopencm3/stm32/common/rtc_common_l1f024.h
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@@ -40,6 +40,8 @@ specific memorymap.h header before including this header file.*/
#ifndef LIBOPENCM3_RTC2_H
#define LIBOPENCM3_RTC2_H
/**@{*/
/** @defgroup rtc_registers RTC Registers
* @ingroup rtc_defines
* @brief Real Time Clock registers
@@ -100,7 +102,7 @@ specific memorymap.h header before including this header file.*/
/** RTC backup registers (RTC_BKPxR) */
#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4 * (reg)))
/*@}*/
/**@}*/
/** @defgroup rtc_tr_values RTC Time register (RTC_TR) values
@@ -133,7 +135,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_TR_SU_SHIFT (0)
/** Second units in BCD format mask */
#define RTC_TR_SU_MASK (0xf)
/*@}*/
/**@}*/
/** @defgroup rtc_dr_values RTC Date register (RTC_DR) values
* @ingroup rtc_registers
@@ -167,7 +169,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_DR_DU_SHIFT (0)
/** Date units in BCD format mask */
#define RTC_DR_DU_MASK (0xf)
/*@}*/
/**@}*/
/** @defgroup rtc_cr_values RTC control register (RTC_CR) values
* @ingroup rtc_registers
@@ -191,7 +193,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_CR_OSEL_ALARMA (0x1)
#define RTC_CR_OSEL_ALARMB (0x2)
#define RTC_CR_OSEL_WAKEUP (0x3)
/*@}*/
/**@}*/
/** Output polarity */
#define RTC_CR_POL (1<<20)
@@ -239,7 +241,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3)
#define RTC_CR_WUCLKSEL_SPRE (0x4)
#define RTC_CR_WUCLKSEL_SPRE_216 (0x6)
/*@}*/
/**@}*/
/** @defgroup rtc_isr_values RTC initialization and status register (RTC_ISR) values
* @ingroup rtc_registers
@@ -280,7 +282,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_ISR_ALRBWF (1<<1)
/** ALRAWF: Alarm A write flag */
#define RTC_ISR_ALRAWF (1<<0)
/*@}*/
/**@}*/
/** @defgroup rtc_prer_values RTC prescaler register (RTC_PRER) values
* @ingroup rtc_registers
@@ -293,7 +295,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_PRER_PREDIV_S_SHIFT (0)
/** Sync prescaler factor mask */
#define RTC_PRER_PREDIV_S_MASK (0x7fff)
/*@}*/
/**@}*/
/* RTC calibration register (RTC_CALIBR) ------------------------ */
#define RTC_CALIBR_DCS (1 << 7)
@@ -327,7 +329,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_ALRMXR_ST_MASK (0x7)
#define RTC_ALRMXR_SU_SHIFT (0)
#define RTC_ALRMXR_SU_MASK (0xf)
/*@}*/
/**@}*/
/* RTC shift control register (RTC_SHIFTR) ---------------------- */
#define RTC_SHIFTR_ADD1S (31)
@@ -351,7 +353,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_TSTR_ST_MASK (0x7)
#define RTC_TSTR_SU_SHIFT (0)
#define RTC_TSTR_SU_MASK (0xf)
/*@}*/
/**@}*/
/** @defgroup rtc_tsdr_values RTC time stamp date register (RTC_TSDR) values
* @ingroup rtc_registers
@@ -365,7 +367,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_TSDR_DT_MASK (0x3)
#define RTC_TSDR_DU_SHIFT (0)
#define RTC_TSDR_DU_MASK (0xf)
/*@}*/
/**@}*/
/** @defgroup rtc_calr_values RTC calibration register (RTC_CALR) values
* @ingroup rtc_registers
@@ -375,7 +377,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_CALR_CALW16 (1 << 13)
#define RTC_CALR_CALM_SHIFT (0)
#define RTC_CALR_CALM_MASK (0x1ff)
/*@}*/
/**@}*/
/** @defgroup rtc_tafcr_values RTC tamper and alternate function configuration register (RTC_TAFCR) values
* @ingroup rtc_registers
@@ -416,7 +418,7 @@ specific memorymap.h header before including this header file.*/
#define RTC_TAFCR_TAMPIE (1<<2)
#define RTC_TAFCR_TAMP1TRG (1<<1)
#define RTC_TAFCR_TAMP1E (1<<0)
/*@}*/
/**@}*/
/* RTC alarm X sub second register ------------------------------ */
/* Note: Applies to RTC_ALRMASSR and RTC_ALRMBSSR */

2
include/libopencm3/stm32/f3/rcc.h
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@@ -281,7 +281,7 @@
#define RCC_AHBENR_SRAMEN (1 << 2)
#define RCC_AHBENR_DMA2EN (1 << 1)
#define RCC_AHBENR_DMA1EN (1 << 0)
/*@}*/
/**@}*/
/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
@{*/

2
include/libopencm3/stm32/g4/crs.h
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@@ -1,6 +1,6 @@
/** @defgroup crs_defines CRS Defines
*
* @brief <b>Defined Constants and Types for the Clock Recovery System.</b>
* @brief <b>Defined Constants and Types for the Clock Recovery System</b>
*
* @ingroup STM32G4xx_defines
*

6
include/libopencm3/stm32/g4/dmamux.h
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@@ -26,8 +26,8 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_DMAMUX_H
#define LIBOPENCM3_DMAMUX_H
#pragma once
/**@{*/
#include <libopencm3/stm32/common/dmamux_common_all.h>
@@ -63,6 +63,7 @@ LGPL License Terms @ref lgpl_license
#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH2_EVT 18
#define DMAMUX_CxCR_SYNC_ID_DMAMUX_CH3_EVT 19
#define DMAMUX_CxCR_SYNC_ID_LPTIM1_OUT 20
/**@}*/
/** @defgroup dmamux_cxcr_dmareq_id DMAREQID DMA request line selected
@@ -213,4 +214,3 @@ LGPL License Terms @ref lgpl_license
/**@}*/
/**@}*/
#endif

9
include/libopencm3/stm32/g4/rcc.h
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@@ -177,7 +177,7 @@
#define RCC_CFGR_HPRE_DIV128 0xd
#define RCC_CFGR_HPRE_DIV256 0xe
#define RCC_CFGR_HPRE_DIV512 0xf
/*@}*/
/**@}*/
#define RCC_CFGR_HPRE_MASK 0xf
#define RCC_CFGR_HPRE_SHIFT 4
@@ -207,6 +207,7 @@
#define RCC_PLLCFGR_PLLR_DIV4 1
#define RCC_PLLCFGR_PLLR_DIV6 2
#define RCC_PLLCFGR_PLLR_DIV8 3
/**@}*/
#define RCC_PLLCFGR_PLLR_SHIFT 25
#define RCC_PLLCFGR_PLLR_MASK 0x3
@@ -446,15 +447,15 @@
#define RCC_APB1ENR1_TIM4EN (1 << 2)
#define RCC_APB1ENR1_TIM3EN (1 << 1)
#define RCC_APB1ENR1_TIM2EN (1 << 0)
/*@}*/
/**@}*/
/** @defgroup rcc_apb1enr2_en RCC_APB1ENR2 enable values
*@{*/
#define RCC_APB1ENR2_UCPD1EN (1 << 8)
#define RCC_APB1ENR2_I2C4EN (1 << 1)
#define RCC_APB1ENR2_LPUART1EN (1 << 0)
/*@}*/
/*@}*/
/**@}*/
/**@}*/
/** @defgroup rcc_apb2enr_en RCC_APB2ENR enable values
*@{*/

6
include/libopencm3/stm32/l1/rcc.h
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@@ -331,7 +331,7 @@
#define RCC_AHBENR_GPIOCEN (1 << 2)
#define RCC_AHBENR_GPIOBEN (1 << 1)
#define RCC_AHBENR_GPIOAEN (1 << 0)
/*@}*/
/**@}*/
/* --- RCC_APB2ENR values -------------------------------------------------- */
@@ -346,7 +346,7 @@
#define RCC_APB2ENR_TIM10EN (1 << 3)
#define RCC_APB2ENR_TIM9EN (1 << 2)
#define RCC_APB2ENR_SYSCFGEN (1 << 0)
/*@}*/
/**@}*/
/* --- RCC_APB1ENR values -------------------------------------------------- */
@@ -370,7 +370,7 @@
#define RCC_APB1ENR_TIM4EN (1 << 2)
#define RCC_APB1ENR_TIM3EN (1 << 1)
#define RCC_APB1ENR_TIM2EN (1 << 0)
/*@}*/
/**@}*/
/* --- RCC_AHBLPENR -------------------------------------------------------- */
#define RCC_AHBLPENR_DMA1LPEN (1 << 24)