Merge branch 'master' of git://github.com/libopencm3/libopencm3 into upstream-merge
This commit is contained in:
Jeff Ciesielski
@@ -28,10 +28,11 @@ CFLAGS = -Os -g -Wall -Wextra -I../../../include -fno-common \
|
||||
-ffunction-sections -fdata-sections -MD -DSTM32F1
|
||||
# ARFLAGS = rcsv
|
||||
ARFLAGS = rcs
|
||||
OBJS = vector.o rcc.o gpio.o usart.o adc.o spi.o flash.o nvic.o \
|
||||
rtc.o i2c.o dma.o systick.o exti.o scb.o ethernet.o \
|
||||
OBJS = rcc.o gpio.o usart.o adc.o spi.o flash.o \
|
||||
rtc.o i2c.o dma.o exti.o ethernet.o \
|
||||
usb_f103.o usb.o usb_control.o usb_standard.o can.o \
|
||||
timer.o usb_f107.o desig.o crc.o assert.o dac.o iwdg.o pwr.o
|
||||
timer.o usb_f107.o desig.o crc.o dac.o iwdg.o pwr.o \
|
||||
usb_fx07_common.o
|
||||
|
||||
VPATH += ../../usb:../:../../cm3
|
||||
|
||||
|
||||
@@ -1,323 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/can.h>
|
||||
#include <libopencm3/stm32/f1/rcc.h>
|
||||
|
||||
void can_reset(u32 canport)
|
||||
{
|
||||
if (canport == CAN1) {
|
||||
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
|
||||
rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN1RST);
|
||||
} else {
|
||||
rcc_peripheral_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST);
|
||||
rcc_peripheral_clear_reset(&RCC_APB1RSTR, RCC_APB1RSTR_CAN2RST);
|
||||
}
|
||||
}
|
||||
|
||||
int can_init(u32 canport, bool ttcm, bool abom, bool awum, bool nart,
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bool rflm, bool txfp, u32 sjw, u32 ts1, u32 ts2, u32 brp,
|
||||
bool loopback, bool silent)
|
||||
{
|
||||
u32 wait_ack = 0x00000000;
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u32 can_msr_inak_timeout = 0x0000FFFF;
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int ret = 0;
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||||
|
||||
/* Exit from sleep mode. */
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CAN_MCR(canport) &= ~CAN_MCR_SLEEP;
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|
||||
/* Request initialization "enter". */
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CAN_MCR(canport) |= CAN_MCR_INRQ;
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||||
|
||||
/* Wait for acknowledge. */
|
||||
while ((wait_ack != can_msr_inak_timeout) &&
|
||||
((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)) {
|
||||
wait_ack++;
|
||||
}
|
||||
|
||||
/* Check the acknowledge. */
|
||||
if ((CAN_MSR(canport) & CAN_MSR_INAK) != CAN_MSR_INAK)
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return 1;
|
||||
|
||||
/* clear can timing bits */
|
||||
CAN_BTR(canport) = 0;
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||||
|
||||
/* Set the automatic bus-off management. */
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||||
if (ttcm)
|
||||
CAN_MCR(canport) |= CAN_MCR_TTCM;
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||||
else
|
||||
CAN_MCR(canport) &= ~CAN_MCR_TTCM;
|
||||
|
||||
if (abom)
|
||||
CAN_MCR(canport) |= CAN_MCR_ABOM;
|
||||
else
|
||||
CAN_MCR(canport) &= ~CAN_MCR_ABOM;
|
||||
|
||||
if (awum)
|
||||
CAN_MCR(canport) |= CAN_MCR_AWUM;
|
||||
else
|
||||
CAN_MCR(canport) &= ~CAN_MCR_AWUM;
|
||||
|
||||
if (nart)
|
||||
CAN_MCR(canport) |= CAN_MCR_NART;
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||||
else
|
||||
CAN_MCR(canport) &= ~CAN_MCR_NART;
|
||||
|
||||
if (rflm)
|
||||
CAN_MCR(canport) |= CAN_MCR_RFLM;
|
||||
else
|
||||
CAN_MCR(canport) &= ~CAN_MCR_RFLM;
|
||||
|
||||
if (txfp)
|
||||
CAN_MCR(canport) |= CAN_MCR_TXFP;
|
||||
else
|
||||
CAN_MCR(canport) &= ~CAN_MCR_TXFP;
|
||||
|
||||
if (silent)
|
||||
CAN_BTR(canport) |= CAN_BTR_SILM;
|
||||
else
|
||||
CAN_BTR(canport) &= ~CAN_BTR_SILM;
|
||||
|
||||
if (loopback)
|
||||
CAN_BTR(canport) |= CAN_BTR_LBKM;
|
||||
else
|
||||
CAN_BTR(canport) &= ~CAN_BTR_LBKM;
|
||||
|
||||
|
||||
/* Set bit timings. */
|
||||
CAN_BTR(canport) |= sjw | ts2 | ts1 |
|
||||
(u32)(CAN_BTR_BRP_MASK & (brp - 1));
|
||||
|
||||
/* Request initialization "leave". */
|
||||
CAN_MCR(canport) &= ~CAN_MCR_INRQ;
|
||||
|
||||
/* Wait for acknowledge. */
|
||||
wait_ack = 0x00000000;
|
||||
while ((wait_ack != can_msr_inak_timeout) &&
|
||||
((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)) {
|
||||
wait_ack++;
|
||||
}
|
||||
|
||||
if ((CAN_MSR(canport) & CAN_MSR_INAK) == CAN_MSR_INAK)
|
||||
ret = 1;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void can_filter_init(u32 canport, u32 nr, bool scale_32bit, bool id_list_mode,
|
||||
u32 fr1, u32 fr2, u32 fifo, bool enable)
|
||||
{
|
||||
u32 filter_select_bit = 0x00000001 << nr;
|
||||
|
||||
/* Request initialization "enter". */
|
||||
CAN_FMR(canport) |= CAN_FMR_FINIT;
|
||||
|
||||
/* Deactivate the filter. */
|
||||
CAN_FA1R(canport) &= ~filter_select_bit;
|
||||
|
||||
if (scale_32bit) {
|
||||
/* Set 32-bit scale for the filter. */
|
||||
CAN_FS1R(canport) |= filter_select_bit;
|
||||
} else {
|
||||
/* Set 16-bit scale for the filter. */
|
||||
CAN_FS1R(canport) &= ~filter_select_bit;
|
||||
}
|
||||
|
||||
if (id_list_mode) {
|
||||
/* Set filter mode to ID list mode. */
|
||||
CAN_FM1R(canport) |= filter_select_bit;
|
||||
} else {
|
||||
/* Set filter mode to id/mask mode. */
|
||||
CAN_FM1R(canport) &= ~filter_select_bit;
|
||||
}
|
||||
|
||||
/* Set the first filter register. */
|
||||
CAN_FiR1(canport, nr) = fr1;
|
||||
|
||||
/* Set the second filter register. */
|
||||
CAN_FiR2(canport, nr) = fr2;
|
||||
|
||||
/* Select FIFO0 or FIFO1 as filter assignement. */
|
||||
if (fifo)
|
||||
CAN_FFA1R(canport) |= filter_select_bit; /* FIFO1 */
|
||||
else
|
||||
CAN_FFA1R(canport) &= ~filter_select_bit; /* FIFO0 */
|
||||
|
||||
if (enable)
|
||||
CAN_FA1R(canport) |= filter_select_bit; /* Activate filter. */
|
||||
|
||||
/* Request initialization "leave". */
|
||||
CAN_FMR(canport) &= ~CAN_FMR_FINIT;
|
||||
}
|
||||
|
||||
void can_filter_id_mask_16bit_init(u32 canport, u32 nr, u16 id1, u16 mask1,
|
||||
u16 id2, u16 mask2, u32 fifo, bool enable)
|
||||
{
|
||||
can_filter_init(canport, nr, false, false,
|
||||
((u32)id1 << 16) | (u32)mask1,
|
||||
((u32)id2 << 16) | (u32)mask2, fifo, enable);
|
||||
}
|
||||
|
||||
void can_filter_id_mask_32bit_init(u32 canport, u32 nr, u32 id, u32 mask,
|
||||
u32 fifo, bool enable)
|
||||
{
|
||||
can_filter_init(canport, nr, true, false, id, mask, fifo, enable);
|
||||
}
|
||||
|
||||
void can_filter_id_list_16bit_init(u32 canport, u32 nr, u16 id1, u16 id2,
|
||||
u16 id3, u16 id4, u32 fifo, bool enable)
|
||||
{
|
||||
can_filter_init(canport, nr, false, true,
|
||||
((u32)id1 << 16) | (u32)id2,
|
||||
((u32)id3 << 16) | (u32)id4, fifo, enable);
|
||||
}
|
||||
|
||||
void can_filter_id_list_32bit_init(u32 canport, u32 nr, u32 id1, u32 id2,
|
||||
u32 fifo, bool enable)
|
||||
{
|
||||
can_filter_init(canport, nr, true, true, id1, id2, fifo, enable);
|
||||
}
|
||||
|
||||
void can_enable_irq(u32 canport, u32 irq)
|
||||
{
|
||||
CAN_IER(canport) |= irq;
|
||||
}
|
||||
|
||||
void can_disable_irq(u32 canport, u32 irq)
|
||||
{
|
||||
CAN_IER(canport) &= ~irq;
|
||||
}
|
||||
|
||||
int can_transmit(u32 canport, u32 id, bool ext, bool rtr, u8 length, u8 *data)
|
||||
{
|
||||
int ret = 0, i;
|
||||
u32 mailbox = 0;
|
||||
|
||||
if ((CAN_TSR(canport) & CAN_TSR_TME0) == CAN_TSR_TME0) {
|
||||
ret = 0;
|
||||
mailbox = CAN_MBOX0;
|
||||
} else if ((CAN_TSR(canport) & CAN_TSR_TME1) == CAN_TSR_TME1) {
|
||||
ret = 1;
|
||||
mailbox = CAN_MBOX1;
|
||||
} else if ((CAN_TSR(canport) & CAN_TSR_TME2) == CAN_TSR_TME2) {
|
||||
ret = 2;
|
||||
mailbox = CAN_MBOX2;
|
||||
} else {
|
||||
ret = -1;
|
||||
}
|
||||
|
||||
/* Check if we have an empty mailbox. */
|
||||
if (ret == -1)
|
||||
return ret;
|
||||
|
||||
/* Clear stale register bits */
|
||||
CAN_TIxR(canport, mailbox) = 0;
|
||||
if (ext) {
|
||||
/* Set extended ID. */
|
||||
CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_EXID_SHIFT;
|
||||
/* Set extended ID indicator bit. */
|
||||
CAN_TIxR(canport, mailbox) |= CAN_TIxR_IDE;
|
||||
} else {
|
||||
/* Set standard ID. */
|
||||
CAN_TIxR(canport, mailbox) |= id << CAN_TIxR_STID_SHIFT;
|
||||
}
|
||||
|
||||
/* Set/clear remote transmission request bit. */
|
||||
if (rtr)
|
||||
CAN_TIxR(canport, mailbox) |= CAN_TIxR_RTR; /* Set */
|
||||
|
||||
/* Set the DLC. */
|
||||
CAN_TDTxR(canport, mailbox) &= 0xFFFFFFF0;
|
||||
CAN_TDTxR(canport, mailbox) |= length & CAN_TDTxR_DLC_MASK;
|
||||
|
||||
/* Set the data. */
|
||||
CAN_TDLxR(canport, mailbox) = 0;
|
||||
CAN_TDHxR(canport, mailbox) = 0;
|
||||
for (i = 0; (i < 4) && (i < length); i++)
|
||||
CAN_TDLxR(canport, mailbox) |= (u32)data[i] << (8 * i);
|
||||
for (i = 4; (i < 8) && (i < length); i++)
|
||||
CAN_TDHxR(canport, mailbox) |= (u32)data[i] << (8 * (i - 4));
|
||||
|
||||
/* Request transmission. */
|
||||
CAN_TIxR(canport, mailbox) |= CAN_TIxR_TXRQ;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void can_fifo_release(u32 canport, u8 fifo)
|
||||
{
|
||||
if (fifo == 0)
|
||||
CAN_RF0R(canport) |= CAN_RF1R_RFOM1;
|
||||
else
|
||||
CAN_RF1R(canport) |= CAN_RF1R_RFOM1;
|
||||
}
|
||||
|
||||
void can_receive(u32 canport, u8 fifo, bool release, u32 *id, bool *ext,
|
||||
bool *rtr, u32 *fmi, u8 *length, u8 *data)
|
||||
{
|
||||
u32 fifo_id = 0;
|
||||
int i;
|
||||
|
||||
if (fifo == 0)
|
||||
fifo_id = CAN_FIFO0;
|
||||
else
|
||||
fifo_id = CAN_FIFO1;
|
||||
|
||||
/* Get type of CAN ID and CAN ID. */
|
||||
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_IDE) {
|
||||
*ext = true;
|
||||
/* Get extended CAN ID. */
|
||||
*id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_EXID_MASK) >>
|
||||
CAN_RIxR_EXID_SHIFT);
|
||||
} else {
|
||||
*ext = false;
|
||||
/* Get standard CAN ID. */
|
||||
*id = ((CAN_RIxR(canport, fifo_id) & CAN_RIxR_STID_MASK) >>
|
||||
CAN_RIxR_STID_SHIFT);
|
||||
}
|
||||
|
||||
/* Get request transmit flag. */
|
||||
if (CAN_RIxR(canport, fifo_id) & CAN_RIxR_RTR)
|
||||
*rtr = true;
|
||||
else
|
||||
*rtr = false;
|
||||
|
||||
/* Get filter match ID. */
|
||||
*fmi = ((CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_FMI_MASK) >
|
||||
CAN_RDTxR_FMI_SHIFT);
|
||||
|
||||
/* Get data length. */
|
||||
*length = CAN_RDTxR(canport, fifo_id) & CAN_RDTxR_DLC_MASK;
|
||||
|
||||
/* Get data. */
|
||||
for (i = 0; (i < 4) && (i < *length); i++)
|
||||
data[i] = (CAN_RDLxR(canport, fifo_id) >> (8 * i)) & 0xFF;
|
||||
|
||||
for (i = 4; (i < 8) && (i < *length); i++)
|
||||
data[i] = (CAN_RDHxR(canport, fifo_id) >> (8 * (i - 4))) & 0xFF;
|
||||
|
||||
/* Release the FIFO. */
|
||||
if (release)
|
||||
can_fifo_release(CAN1, 0);
|
||||
}
|
||||
|
||||
bool can_available_mailbox(u32 canport)
|
||||
{
|
||||
return CAN_TSR(canport) & (CAN_TSR_TME0 | CAN_TSR_TME1 | CAN_TSR_TME2);
|
||||
}
|
||||
@@ -1,59 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Karl Palsson <karlp@ŧweak.net.au>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/f1/desig.h>
|
||||
|
||||
u16 desig_get_flash_size(void)
|
||||
{
|
||||
return DESIG_FLASH_SIZE;
|
||||
}
|
||||
|
||||
void desig_get_unique_id(u32 result[])
|
||||
{
|
||||
// Could also just return a pointer to the start? read it as they wish?
|
||||
u16 bits15_0 = DESIG_UID_15_0;
|
||||
u32 bits31_16 = DESIG_UID_31_16;
|
||||
u32 bits63_32 = DESIG_UID_63_32;
|
||||
u32 bits95_64 = DESIG_UID_95_64;
|
||||
result[0] = bits95_64;
|
||||
result[1] = bits63_32;
|
||||
result[2] = bits31_16 << 16 | bits15_0;
|
||||
}
|
||||
|
||||
void desig_get_unique_id_as_string(char *string,
|
||||
unsigned int string_len)
|
||||
{
|
||||
int i, len;
|
||||
u8 device_id[12];
|
||||
static const char chars[] = "0123456789ABCDEF";
|
||||
|
||||
desig_get_unique_id((u32 *)device_id);
|
||||
|
||||
/* Each byte produces two characters */
|
||||
len = (2 * sizeof(device_id) < string_len) ?
|
||||
2 * sizeof(device_id) : string_len - 1;
|
||||
|
||||
for (i = 0; i < len; i += 2) {
|
||||
string[i] = chars[(device_id[i / 2] >> 0) & 0x0F];
|
||||
string[i + 1] = chars[(device_id[i / 2] >> 4) & 0x0F];
|
||||
}
|
||||
|
||||
string[len] = '\0';
|
||||
}
|
||||
|
||||
@@ -10,12 +10,18 @@
|
||||
|
||||
@date 18 August 2012
|
||||
|
||||
This library supports the DMA
|
||||
Control System in the STM32F1xx series of ARM Cortex Microcontrollers
|
||||
by ST Microelectronics. It can provide for two DMA controllers,
|
||||
one with 7 channels and one with 5. Channels are hardware dedicated
|
||||
and each is shared with a number of different sources (only one can be
|
||||
used at a time, under the responsibility of the programmer).
|
||||
This library supports the DMA Control System in the STM32 series of ARM Cortex
|
||||
Microcontrollers by ST Microelectronics.
|
||||
|
||||
Up to two DMA controllers are supported. 12 DMA channels are allocated 7 to
|
||||
the first DMA controller and 5 to the second. Each channel is connected to
|
||||
between 3 and 6 hardware peripheral DMA signals in a logical OR arrangement.
|
||||
|
||||
DMA transfers can be configured to occur between peripheral and memory in
|
||||
any combination including memory to memory. Circular mode transfers are
|
||||
also supported in transfers involving a peripheral. An arbiter is provided
|
||||
to resolve priority DMA requests. Transfers can be made with 8, 16 or 32 bit
|
||||
words.
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
@@ -67,6 +73,42 @@ void dma_channel_reset(u32 dma, u8 channel)
|
||||
DMA_IFCR(dma) |= DMA_IFCR_CIF(channel);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief DMA Channel Clear Interrupt Flag
|
||||
|
||||
The interrupt flag for the channel is cleared. More than one interrupt for the
|
||||
same channel may be cleared by using the logical OR of the interrupt flags.
|
||||
|
||||
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
||||
@param[in] channel unsigned int8. Channel number: @ref dma_st_number
|
||||
@param[in] interrupts unsigned int32. Logical OR of interrupt numbers: @ref dma_if_offset
|
||||
*/
|
||||
|
||||
void dma_clear_interrupt_flags(u32 dma, u8 channel, u32 interrupts)
|
||||
{
|
||||
/* Get offset to interrupt flag location in channel field */
|
||||
u32 flags = (interrupts << DMA_FLAG_OFFSET(channel));
|
||||
DMA_IFCR(dma) = flags;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief DMA Channel Read Interrupt Flag
|
||||
|
||||
The interrupt flag for the channel is returned.
|
||||
|
||||
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
||||
@param[in] channel unsigned int8. Channel number: @ref dma_st_number
|
||||
@param[in] interrupt unsigned int32. Interrupt number: @ref dma_st_number
|
||||
@returns bool interrupt flag is set.
|
||||
*/
|
||||
|
||||
bool dma_get_interrupt_flag(u32 dma, u8 channel, u32 interrupt)
|
||||
{
|
||||
/* get offset to interrupt flag location in channel field. */
|
||||
u32 flag = (interrupt << DMA_FLAG_OFFSET(channel));
|
||||
return ((DMA_ISR(dma) & flag) > 0);
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief DMA Channel Enable Memory to Memory Transfers
|
||||
|
||||
@@ -160,11 +202,39 @@ void dma_enable_memory_increment_mode(u32 dma, u8 channel)
|
||||
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
|
||||
*/
|
||||
|
||||
void dma_disable_memory_increment_mode(u32 dma, u8 channel)
|
||||
{
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_MINC;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief DMA Channel Enable Peripheral Increment after Transfer
|
||||
|
||||
Following each transfer the current peripheral address is incremented by
|
||||
1, 2 or 4 depending on the data size set in @ref dma_set_peripheral_size. The
|
||||
value held by the base peripheral address register is unchanged.
|
||||
|
||||
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
||||
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
|
||||
*/
|
||||
|
||||
void dma_enable_peripheral_increment_mode(u32 dma, u8 channel)
|
||||
{
|
||||
DMA_CCR(dma, channel) |= DMA_CCR_PINC;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief DMA Channel Disable Peripheral Increment after Transfer
|
||||
|
||||
@param[in] dma unsigned int32. DMA controller base address: DMA1 or DMA2
|
||||
@param[in] channel unsigned int8. Channel number: 1-7 for DMA1 or 1-5 for DMA2
|
||||
*/
|
||||
|
||||
void dma_disable_peripheral_increment_mode(u32 dma, u8 channel)
|
||||
{
|
||||
DMA_CCR(dma, channel) &= ~DMA_CCR_PINC;
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------------------------*/
|
||||
/** @brief DMA Channel Enable Memory Circular Mode
|
||||
|
||||
|
||||
@@ -1,35 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#include <libopencm3/stm32/f1/scb.h>
|
||||
|
||||
void scb_reset_core(void)
|
||||
{
|
||||
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_VECTRESET;
|
||||
}
|
||||
|
||||
void scb_reset_system(void)
|
||||
{
|
||||
SCB_AIRCR = SCB_AIRCR_VECTKEY | SCB_AIRCR_SYSRESETREQ;
|
||||
}
|
||||
|
||||
void scb_set_priority_grouping(u32 prigroup)
|
||||
{
|
||||
SCB_AIRCR = SCB_AIRCR_VECTKEY | prigroup;
|
||||
}
|
||||
1948
lib/stm32/f1/timer.c
1948
lib/stm32/f1/timer.c
File diff suppressed because it is too large
Load Diff
@@ -1,316 +0,0 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Piotr Esden-Tempski <piotr@esden.net>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#define WEAK __attribute__ ((weak))
|
||||
#define NAKED __attribute__((naked))
|
||||
#include <stdint.h>
|
||||
/* Symbols exported by the linker script(s): */
|
||||
extern unsigned _data_loadaddr, _data, _edata, _ebss, _stack;
|
||||
|
||||
void main(void);
|
||||
void reset_handler(void);
|
||||
void blocking_handler(void);
|
||||
void null_handler(void);
|
||||
|
||||
void WEAK nmi_handler(void);
|
||||
void WEAK hard_fault_handler(void);
|
||||
void WEAK mem_manage_handler(void);
|
||||
void WEAK bus_fault_handler(void);
|
||||
void WEAK usage_fault_handler(void);
|
||||
void WEAK sv_call_handler(void);
|
||||
void WEAK debug_monitor_handler(void);
|
||||
void WEAK pend_sv_handler(void);
|
||||
void WEAK sys_tick_handler(void);
|
||||
void WEAK wwdg_isr(void);
|
||||
void WEAK pvd_isr(void);
|
||||
void WEAK tamper_isr(void);
|
||||
void WEAK rtc_isr(void);
|
||||
void WEAK flash_isr(void);
|
||||
void WEAK rcc_isr(void);
|
||||
void WEAK exti0_isr(void);
|
||||
void WEAK exti1_isr(void);
|
||||
void WEAK exti2_isr(void);
|
||||
void WEAK exti3_isr(void);
|
||||
void WEAK exti4_isr(void);
|
||||
void WEAK dma1_channel1_isr(void);
|
||||
void WEAK dma1_channel2_isr(void);
|
||||
void WEAK dma1_channel3_isr(void);
|
||||
void WEAK dma1_channel4_isr(void);
|
||||
void WEAK dma1_channel5_isr(void);
|
||||
void WEAK dma1_channel6_isr(void);
|
||||
void WEAK dma1_channel7_isr(void);
|
||||
void WEAK adc1_2_isr(void);
|
||||
void WEAK usb_hp_can_tx_isr(void);
|
||||
void WEAK usb_lp_can_rx0_isr(void);
|
||||
void WEAK can_rx1_isr(void);
|
||||
void WEAK can_sce_isr(void);
|
||||
void WEAK exti9_5_isr(void);
|
||||
void WEAK tim1_brk_isr(void);
|
||||
void WEAK tim1_up_isr(void);
|
||||
void WEAK tim1_trg_com_isr(void);
|
||||
void WEAK tim1_cc_isr(void);
|
||||
void WEAK tim2_isr(void);
|
||||
void WEAK tim3_isr(void);
|
||||
void WEAK tim4_isr(void);
|
||||
void WEAK i2c1_ev_isr(void);
|
||||
void WEAK i2c1_er_isr(void);
|
||||
void WEAK i2c2_ev_isr(void);
|
||||
void WEAK i2c2_er_isr(void);
|
||||
void WEAK spi1_isr(void);
|
||||
void WEAK spi2_isr(void);
|
||||
void WEAK usart1_isr(void);
|
||||
void WEAK usart2_isr(void);
|
||||
void WEAK usart3_isr(void);
|
||||
void WEAK exti15_10_isr(void);
|
||||
void WEAK rtc_alarm_isr(void);
|
||||
void WEAK usb_wakeup_isr(void);
|
||||
void WEAK tim8_brk_isr(void);
|
||||
void WEAK tim8_up_isr(void);
|
||||
void WEAK tim8_trg_com_isr(void);
|
||||
void WEAK tim8_cc_isr(void);
|
||||
void WEAK adc3_isr(void);
|
||||
void WEAK fsmc_isr(void);
|
||||
void WEAK sdio_isr(void);
|
||||
void WEAK tim5_isr(void);
|
||||
void WEAK spi3_isr(void);
|
||||
void WEAK uart4_isr(void);
|
||||
void WEAK uart5_isr(void);
|
||||
void WEAK tim6_isr(void);
|
||||
void WEAK tim7_isr(void);
|
||||
void WEAK dma2_channel1_isr(void);
|
||||
void WEAK dma2_channel2_isr(void);
|
||||
void WEAK dma2_channel3_isr(void);
|
||||
void WEAK dma2_channel4_5_isr(void);
|
||||
void WEAK dma2_channel5_isr(void);
|
||||
void WEAK eth_isr(void);
|
||||
void WEAK eth_wkup_isr(void);
|
||||
void WEAK can2_tx_isr(void);
|
||||
void WEAK can2_rx0_isr(void);
|
||||
void WEAK can2_rx1_isr(void);
|
||||
void WEAK can2_sce_isr(void);
|
||||
void WEAK otg_fs_isr(void);
|
||||
|
||||
|
||||
__attribute__ ((section(".vectors")))
|
||||
void (*const vector_table[]) (void) = {
|
||||
(void*)&_stack, /* Addr: 0x0000_0000 */
|
||||
reset_handler, /* Addr: 0x0000_0004 */
|
||||
nmi_handler, /* Addr: 0x0000_0008 */
|
||||
hard_fault_handler, /* Addr: 0x0000_000C */
|
||||
mem_manage_handler, /* Addr: 0x0000_0010 */
|
||||
bus_fault_handler, /* Addr: 0x0000_0014 */
|
||||
usage_fault_handler, /* Addr: 0x0000_0018 */
|
||||
0, 0, 0, 0, /* Reserved Addr: 0x0000_001C - 0x0000_002B */
|
||||
sv_call_handler, /* Addr: 0x0000_002C */
|
||||
debug_monitor_handler, /* Addr: 0x0000_0030*/
|
||||
0, /* Reserved Addr: 0x0000_00034 */
|
||||
pend_sv_handler, /* Addr: 0x0000_0038 */
|
||||
sys_tick_handler, /* Addr: 0x0000_003C */
|
||||
wwdg_isr, /* Addr: 0x0000_0040 */
|
||||
pvd_isr, /* Addr: 0x0000_0044 */
|
||||
tamper_isr, /* Addr: 0x0000_0048 */
|
||||
rtc_isr, /* Addr: 0x0000_004C */
|
||||
flash_isr, /* Addr: 0x0000_0050 */
|
||||
rcc_isr, /* Addr: 0x0000_0054 */
|
||||
exti0_isr, /* Addr: 0x0000_0058 */
|
||||
exti1_isr, /* Addr: 0x0000_005C */
|
||||
exti2_isr, /* Addr: 0x0000_0060 */
|
||||
exti3_isr, /* Addr: 0x0000_0064 */
|
||||
exti4_isr, /* Addr: 0x0000_0068 */
|
||||
dma1_channel1_isr, /* Addr: 0x0000_006C */
|
||||
dma1_channel2_isr, /* Addr: 0x0000_0070 */
|
||||
dma1_channel3_isr, /* Addr: 0x0000_0074 */
|
||||
dma1_channel4_isr, /* Addr: 0x0000_0078 */
|
||||
dma1_channel5_isr, /* Addr: 0x0000_007C */
|
||||
dma1_channel6_isr, /* Addr: 0x0000_0080 */
|
||||
dma1_channel7_isr, /* Addr: 0x0000_0084 */
|
||||
adc1_2_isr, /* Addr: 0x0000_0088 */
|
||||
usb_hp_can_tx_isr, /* Addr: 0x0000_008C */
|
||||
usb_lp_can_rx0_isr, /* Addr: 0x0000_0090 */
|
||||
can_rx1_isr, /* Addr: 0x0000_0094 */
|
||||
can_sce_isr, /* Addr: 0x0000_0098 */
|
||||
exti9_5_isr, /* Addr: 0x0000_009C */
|
||||
tim1_brk_isr, /* Addr: 0x0000_00A0 */
|
||||
tim1_up_isr, /* Addr: 0x0000_00A4 */
|
||||
tim1_trg_com_isr, /* Addr: 0x0000_00A8 */
|
||||
tim1_cc_isr, /* Addr: 0x0000_00AC */
|
||||
tim2_isr, /* Addr: 0x0000_00B0 */
|
||||
tim3_isr, /* Addr: 0x0000_00B4 */
|
||||
tim4_isr, /* Addr: 0x0000_00B8 */
|
||||
i2c1_ev_isr, /* Addr: 0x0000_00BC */
|
||||
i2c1_er_isr, /* Addr: 0x0000_00C0 */
|
||||
i2c2_ev_isr, /* Addr: 0x0000_00C4 */
|
||||
i2c2_er_isr, /* Addr: 0x0000_00C8 */
|
||||
spi1_isr, /* Addr: 0x0000_00CC */
|
||||
spi2_isr, /* Addr: 0x0000_00D0 */
|
||||
usart1_isr, /* Addr: 0x0000_00D4 */
|
||||
usart2_isr, /* Addr: 0x0000_00D8 */
|
||||
usart3_isr, /* Addr: 0x0000_00DC */
|
||||
exti15_10_isr, /* Addr: 0x0000_00E0 */
|
||||
rtc_alarm_isr, /* Addr: 0x0000_00E4 */
|
||||
usb_wakeup_isr, /* Addr: 0x0000_00E8 */
|
||||
tim8_brk_isr, /* Addr: 0x0000_00EC */
|
||||
tim8_up_isr, /* Addr: 0x0000_00F0 */
|
||||
tim8_trg_com_isr, /* Addr: 0x0000_00F4 */
|
||||
tim8_cc_isr, /* Addr: 0x0000_00F8 */
|
||||
adc3_isr, /* Addr: 0x0000_00FC */
|
||||
fsmc_isr, /* Addr: 0x0000_0100 */
|
||||
sdio_isr, /* Addr: 0x0000_0104 */
|
||||
tim5_isr, /* Addr: 0x0000_0108 */
|
||||
spi3_isr, /* Addr: 0x0000_010C */
|
||||
uart4_isr, /* Addr: 0x0000_0110 */
|
||||
uart5_isr, /* Addr: 0x0000_0114 */
|
||||
tim6_isr, /* Addr: 0x0000_0118 */
|
||||
tim7_isr, /* Addr: 0x0000_011C */
|
||||
dma2_channel1_isr, /* Addr: 0x0000_0120 */
|
||||
dma2_channel2_isr, /* Addr: 0x0000_0124 */
|
||||
dma2_channel3_isr, /* Addr: 0x0000_0128 */
|
||||
dma2_channel4_5_isr, /* Addr: 0x0000_012C */
|
||||
dma2_channel5_isr, /* Addr: 0x0000_0130 */
|
||||
eth_isr, /* Addr: 0x0000_0134 */
|
||||
eth_wkup_isr, /* Addr: 0x0000_0138 */
|
||||
can2_tx_isr, /* Addr: 0x0000_013C */
|
||||
can2_rx0_isr, /* Addr: 0x0000_0140 */
|
||||
can2_rx1_isr, /* Addr: 0x0000_0144 */
|
||||
can2_sce_isr, /* Addr: 0x0000_0148 */
|
||||
otg_fs_isr, /* Addr: 0x0000_014C */
|
||||
};
|
||||
|
||||
void WEAK user_reset_hook(void);
|
||||
|
||||
void handle_dfu_bootloader(void)
|
||||
{
|
||||
uint32_t reset_str = *((uint32_t *)0x2000FFF0);
|
||||
|
||||
if (reset_str == 0xDEADBEEF) {
|
||||
*((uint32_t *)0x2000FFF0) = 0x00;
|
||||
asm("ldr r0, =0x1fffb000");
|
||||
asm("ldr sp, [r0, #0]");
|
||||
asm("ldr r0, [r0, #4]");
|
||||
asm("bx r0");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void NAKED reset_handler(void)
|
||||
{
|
||||
volatile unsigned *src, *dest;
|
||||
|
||||
__asm__("MSR msp, %0" : : "r"(&_stack));
|
||||
|
||||
user_reset_hook();
|
||||
|
||||
for (src = &_data_loadaddr, dest = &_data; dest < &_edata; src++, dest++)
|
||||
*dest = *src;
|
||||
|
||||
while (dest < &_ebss)
|
||||
*dest++ = 0;
|
||||
|
||||
/* Call the application's entry point. */
|
||||
main();
|
||||
}
|
||||
|
||||
void blocking_handler(void)
|
||||
{
|
||||
while (1) ;
|
||||
}
|
||||
|
||||
void null_handler(void)
|
||||
{
|
||||
/* Do nothing. */
|
||||
}
|
||||
|
||||
#pragma weak user_reset_hook = handle_dfu_bootloader
|
||||
#pragma weak nmi_handler = null_handler
|
||||
#pragma weak hard_fault_handler = blocking_handler
|
||||
#pragma weak mem_manage_handler = blocking_handler
|
||||
#pragma weak bus_fault_handler = blocking_handler
|
||||
#pragma weak usage_fault_handler = blocking_handler
|
||||
#pragma weak sv_call_handler = null_handler
|
||||
#pragma weak debug_monitor_handler = null_handler
|
||||
#pragma weak pend_sv_handler = null_handler
|
||||
#pragma weak sys_tick_handler = null_handler
|
||||
#pragma weak wwdg_isr = null_handler
|
||||
#pragma weak pvd_isr = null_handler
|
||||
#pragma weak tamper_isr = null_handler
|
||||
#pragma weak rtc_isr = null_handler
|
||||
#pragma weak flash_isr = null_handler
|
||||
#pragma weak rcc_isr = null_handler
|
||||
#pragma weak exti0_isr = null_handler
|
||||
#pragma weak exti1_isr = null_handler
|
||||
#pragma weak exti2_isr = null_handler
|
||||
#pragma weak exti3_isr = null_handler
|
||||
#pragma weak exti4_isr = null_handler
|
||||
#pragma weak dma1_channel1_isr = null_handler
|
||||
#pragma weak dma1_channel2_isr = null_handler
|
||||
#pragma weak dma1_channel3_isr = null_handler
|
||||
#pragma weak dma1_channel4_isr = null_handler
|
||||
#pragma weak dma1_channel5_isr = null_handler
|
||||
#pragma weak dma1_channel6_isr = null_handler
|
||||
#pragma weak dma1_channel7_isr = null_handler
|
||||
#pragma weak adc1_2_isr = null_handler
|
||||
#pragma weak usb_hp_can_tx_isr = null_handler
|
||||
#pragma weak usb_lp_can_rx0_isr = null_handler
|
||||
#pragma weak can_rx1_isr = null_handler
|
||||
#pragma weak can_sce_isr = null_handler
|
||||
#pragma weak exti9_5_isr = null_handler
|
||||
#pragma weak tim1_brk_isr = null_handler
|
||||
#pragma weak tim1_up_isr = null_handler
|
||||
#pragma weak tim1_trg_com_isr = null_handler
|
||||
#pragma weak tim1_cc_isr = null_handler
|
||||
#pragma weak tim2_isr = null_handler
|
||||
#pragma weak tim3_isr = null_handler
|
||||
#pragma weak tim4_isr = null_handler
|
||||
#pragma weak i2c1_ev_isr = null_handler
|
||||
#pragma weak i2c1_er_isr = null_handler
|
||||
#pragma weak i2c2_ev_isr = null_handler
|
||||
#pragma weak i2c2_er_isr = null_handler
|
||||
#pragma weak spi1_isr = null_handler
|
||||
#pragma weak spi2_isr = null_handler
|
||||
#pragma weak usart1_isr = null_handler
|
||||
#pragma weak usart2_isr = null_handler
|
||||
#pragma weak usart3_isr = null_handler
|
||||
#pragma weak exti15_10_isr = null_handler
|
||||
#pragma weak rtc_alarm_isr = null_handler
|
||||
#pragma weak usb_wakeup_isr = null_handler
|
||||
#pragma weak tim8_brk_isr = null_handler
|
||||
#pragma weak tim8_up_isr = null_handler
|
||||
#pragma weak tim8_trg_com_isr = null_handler
|
||||
#pragma weak tim8_cc_isr = null_handler
|
||||
#pragma weak adc3_isr = null_handler
|
||||
#pragma weak fsmc_isr = null_handler
|
||||
#pragma weak sdio_isr = null_handler
|
||||
#pragma weak tim5_isr = null_handler
|
||||
#pragma weak spi3_isr = null_handler
|
||||
#pragma weak uart4_isr = null_handler
|
||||
#pragma weak uart5_isr = null_handler
|
||||
#pragma weak tim6_isr = null_handler
|
||||
#pragma weak tim7_isr = null_handler
|
||||
#pragma weak dma2_channel1_isr = null_handler
|
||||
#pragma weak dma2_channel2_isr = null_handler
|
||||
#pragma weak dma2_channel3_isr = null_handler
|
||||
#pragma weak dma2_channel4_5_isr = null_handler
|
||||
#pragma weak dma2_channel5_isr
|
||||
#pragma weak eth_isr = null_handler
|
||||
#pragma weak eth_wkup_isr = null_handler
|
||||
#pragma weak can2_tx_isr = null_handler
|
||||
#pragma weak can2_rx0_isr = null_handler
|
||||
#pragma weak can2_rx1_isr = null_handler
|
||||
#pragma weak can2_sce_isr = null_handler
|
||||
#pragma weak otg_fs_isr = null_handler
|
||||
Reference in New Issue
Block a user