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Merging pull request #76 "LM4F clock api"

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Merge remote-tracking branch 'mrnuke/lm4f_clock_api'
This commit is contained in:
Piotr Esden-Tempski
2013-02-18 13:53:57 -08:00
parent 9193d3d273 7ba100f569
commit daf4cc0feb
7 changed files with 1109 additions and 40 deletions
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126
include/libopencm3/lm4f/rcc.h Normal file
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@@ -0,0 +1,126 @@
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2012 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**
* @defgroup rcc_defines RCC Defines
*
* @ingroup LM4F_defines
*
* \brief <b>Defined Constants and Types for the LM4F Clock control API</b>
* @{
*/
#ifndef LM4F_RCC_H
#define LM4F_RCC_H
#include <libopencm3/lm4f/systemcontrol.h>
/**
* \brief Oscillator source values
*
* Possible values of the oscillator source.
*/
typedef enum {
OSCSRC_MOSC = SYSCTL_RCC2_OSCSRC2_MOSC,
OSCSRC_PIOSC = SYSCTL_RCC2_OSCSRC2_PIOSC,
OSCSRC_PIOSC_D4 = SYSCTL_RCC2_OSCSRC2_PIOSC_D4,
OSCSRC_30K_INT = SYSCTL_RCC2_OSCSRC2_30K,
OSCSRC_32K_EXT = SYSCTL_RCC2_OSCSRC2_32K768,
} osc_src_t;
/**
* \brief PWM clock divisor values
*
* Possible values of the binary divisor used to predivide the system clock down
* for use as the timing reference for the PWM module.
*/
typedef enum {
PWMDIV_2 = SYSCTL_RCC_PWMDIV_2,
PWMDIV_4 = SYSCTL_RCC_PWMDIV_4,
PWMDIV_8 = SYSCTL_RCC_PWMDIV_8,
PWMDIV_16 = SYSCTL_RCC_PWMDIV_16,
PWMDIV_32 = SYSCTL_RCC_PWMDIV_32,
PWMDIV_64 = SYSCTL_RCC_PWMDIV_64,
} pwm_clkdiv_t;
/**
* \brief Predefined crystal values
*
* Predefined crystal values for the XTAL field in SYSCTL_RCC.
* Using these predefined values in the XTAL field, the SYSCTL_PLLFREQ0 and
* SYSCTL_PLLFREQ1 are automatically adjusted in hardware to provide a PLL clock
* of 400MHz.
*/
typedef enum {
XTAL_4M = SYSCTL_RCC_XTAL_4M,
XTAL_4M_096 = SYSCTL_RCC_XTAL_4M_096,
XTAL_4M_9152 = SYSCTL_RCC_XTAL_4M_9152,
XTAL_5M = SYSCTL_RCC_XTAL_5M,
XTAL_5M_12 = SYSCTL_RCC_XTAL_5M_12,
XTAL_6M = SYSCTL_RCC_XTAL_6M,
XTAL_6M_144 = SYSCTL_RCC_XTAL_6M_144,
XTAL_7M_3728 = SYSCTL_RCC_XTAL_7M_3728,
XTAL_8M = SYSCTL_RCC_XTAL_8M,
XTAL_8M_192 = SYSCTL_RCC_XTAL_8M_192,
XTAL_10M = SYSCTL_RCC_XTAL_10M,
XTAL_12M = SYSCTL_RCC_XTAL_12M,
XTAL_12M_288 = SYSCTL_RCC_XTAL_12M_288,
XTAL_13M_56 = SYSCTL_RCC_XTAL_13M_56,
XTAL_14M_31818 = SYSCTL_RCC_XTAL_14M_31818,
XTAL_16M = SYSCTL_RCC_XTAL_16M,
XTAL_16M_384 = SYSCTL_RCC_XTAL_16M_384,
XTAL_18M = SYSCTL_RCC_XTAL_18M,
XTAL_20M = SYSCTL_RCC_XTAL_20M,
XTAL_24M = SYSCTL_RCC_XTAL_24M,
XTAL_25M = SYSCTL_RCC_XTAL_25M,
} xtal_t;
/**
* @}
*/
/* =============================================================================
* Function prototypes
* ---------------------------------------------------------------------------*/
BEGIN_DECLS
/* Low-level clock API */
void rcc_configure_xtal(xtal_t xtal);
void rcc_disable_main_osc(void);
void rcc_disable_interal_osc(void);
void rcc_enable_main_osc(void);
void rcc_enable_interal_osc(void);
void rcc_enable_rcc2(void);
void rcc_pll_off(void);
void rcc_pll_on(void);
void rcc_set_osc_source(osc_src_t src);
void rcc_pll_bypass_disable(void);
void rcc_pll_bypass_enable(void);
void rcc_set_pll_divisor(u8 div400);
void rcc_set_pwm_divisor(pwm_clkdiv_t div);
void rcc_usb_pll_off(void);
void rcc_usb_pll_on(void);
void rcc_wait_for_pll_ready(void);
/* High-level clock API */
void rcc_change_pll_divisor(u8 plldiv400);
u32 rcc_get_system_clock_frequency(void);
void rcc_sysclk_config(osc_src_t src, xtal_t xtal, u8 pll_div400);
END_DECLS
#endif /* LM4F_RCC_H */

272
include/libopencm3/lm4f/systemcontrol.h
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@@ -21,6 +21,7 @@
#define LM4F_SYSTEMCONTROL_H
#include <libopencm3/cm3/common.h>
#include <libopencm3/lm4f/memorymap.h>
#define SYSCTL_DID0 MMIO32(SYSCTL_BASE + 0x000)
#define SYSCTL_DID1 MMIO32(SYSCTL_BASE + 0x004)
@@ -369,9 +370,11 @@
/** Auto Clock Gating */
#define SYSCTL_RCC2_ACG (1 << 27)
/** System Clock Divisor 2 */
#define SYSCTL_RCC2_SYSDIV2_MASK (0xF << 23)
#define SYSCTL_RCC2_SYSDIV2_MASK (0x3F << 23)
/** Additional LSB for SYSDIV2 */
#define SYSCTL_RCC2_SYSDIV2LSB (1 << 22)
/** System clock divisor mask when RCC2_DIV400 is set */
#define SYSCTL_RCC2_SYSDIV400_MASK (0x7F << 22)
/** Power-Down USB PLL */
#define SYSCTL_RCC2_USBPWRDN (1 << 14)
/** PLL Power Down 2 */
@@ -450,6 +453,273 @@
/** PLL lock */
#define SYSCTL_PLLSTAT_LOCK (1 << 0)
/* =============================================================================
* Convenience definitions for a readable API
* ---------------------------------------------------------------------------*/
/**
* \brief Clock enable definitions
*
* The definitions are specified in the form
* 31:5 register offset from SYSCTL_BASE for the clock register
* 4:0 bit offset for the given peripheral
*
* The names have the form [clock_type]_[periph_type]_[periph_number]
* Where clock_type is
* RCC for run clock
* SCC for sleep clock
* DCC for deep-sleep clock
*/
typedef enum {
/*
* Run clock control
*/
RCC_WD0 = ((u32)&SYSCTL_RCGCWD - SYSCTL_BASE) << 5,
RCC_WD1,
RCC_TIMER0 = ((u32)&SYSCTL_RCGCTIMER - SYSCTL_BASE) << 5,
RCC_TIMER1,
RCC_TIMER2,
RCC_TIMER3,
RCC_TIMER4,
RCC_TIMER5,
RCC_GPIOA = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
RCC_GPIOB,
RCC_GPIOC,
RCC_GPIOD,
RCC_GPIOE,
RCC_GPIOF,
RCC_GPIOG,
RCC_GPIOH,
RCC_GPIOJ,
RCC_GPIOK,
RCC_GPIOL,
RCC_GPIOM,
RCC_GPION,
RCC_GPIOP,
RCC_GPIOQ,
RCC_DMA = ((u32)&SYSCTL_RCGCDMA - SYSCTL_BASE) << 5,
RCC_HIB = ((u32)&SYSCTL_RCGCGPIO - SYSCTL_BASE) << 5,
RCC_UART0 = ((u32)&SYSCTL_RCGCUART - SYSCTL_BASE) << 5,
RCC_UART1,
RCC_UART2,
RCC_UART3,
RCC_UART4,
RCC_UART5,
RCC_UART6,
RCC_UART7,
RCC_SSI0 = ((u32)&SYSCTL_RCGCSSI - SYSCTL_BASE) << 5,
RCC_SSI1,
RCC_SSI2,
RCC_SSI3,
RCC_I2C0 = ((u32)&SYSCTL_RCGCI2C - SYSCTL_BASE) << 5,
RCC_I2C1,
RCC_I2C2,
RCC_I2C3,
RCC_I2C4,
RCC_I2C5,
RCC_USB0 = ((u32)&SYSCTL_RCGCUSB - SYSCTL_BASE) << 5,
RCC_CAN0 = ((u32)&SYSCTL_RCGCCAN - SYSCTL_BASE) << 5,
RCC_CAN1,
RCC_ADC0 = ((u32)&SYSCTL_RCGCADC - SYSCTL_BASE) << 5,
RCC_ADC1,
RCC_ACMP0 = ((u32)&SYSCTL_RCGCACMP - SYSCTL_BASE) << 5,
RCC_PWM0 = ((u32)&SYSCTL_RCGCPWM - SYSCTL_BASE) << 5,
RCC_PWM1,
RCC_QEI0 = ((u32)&SYSCTL_RCGCQEI - SYSCTL_BASE) << 5,
RCC_QEI1,
RCC_EEPROM0 = ((u32)&SYSCTL_RCGCEEPROM - SYSCTL_BASE) << 5,
RCC_WTIMER0 = ((u32)&SYSCTL_RCGCWTIMER - SYSCTL_BASE) << 5,
RCC_WTIMER1,
RCC_WTIMER2,
RCC_WTIMER3,
RCC_WTIMER4,
RCC_WTIMER5,
/*
* Sleep clock control
*/
SCC_WD0 = ((u32)&SYSCTL_SCGCWD - SYSCTL_BASE) << 5,
SCC_WD1,
SCC_TIMER0 = ((u32)&SYSCTL_SCGCTIMER - SYSCTL_BASE) << 5,
SCC_TIMER1,
SCC_TIMER2,
SCC_TIMER3,
SCC_TIMER4,
SCC_TIMER5,
SCC_GPIOA = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
SCC_GPIOB,
SCC_GPIOC,
SCC_GPIOD,
SCC_GPIOE,
SCC_GPIOF,
SCC_GPIOG,
SCC_GPIOH,
SCC_GPIOJ,
SCC_GPIOK,
SCC_GPIOL,
SCC_GPIOM,
SCC_GPION,
SCC_GPIOP,
SCC_GPIOQ,
SCC_DMA = ((u32)&SYSCTL_SCGCDMA - SYSCTL_BASE) << 5,
SCC_HIB = ((u32)&SYSCTL_SCGCGPIO - SYSCTL_BASE) << 5,
SCC_UART0 = ((u32)&SYSCTL_SCGCUART - SYSCTL_BASE) << 5,
SCC_UART1,
SCC_UART2,
SCC_UART3,
SCC_UART4,
SCC_UART5,
SCC_UART6,
SCC_UART7,
SCC_SSI0 = ((u32)&SYSCTL_SCGCSSI - SYSCTL_BASE) << 5,
SCC_SSI1,
SCC_SSI2,
SCC_SSI3,
SCC_I2C0 = ((u32)&SYSCTL_SCGCI2C - SYSCTL_BASE) << 5,
SCC_I2C1,
SCC_I2C2,
SCC_I2C3,
SCC_I2C4,
SCC_I2C5,
SCC_USB0 = ((u32)&SYSCTL_SCGCUSB - SYSCTL_BASE) << 5,
SCC_CAN0 = ((u32)&SYSCTL_SCGCCAN - SYSCTL_BASE) << 5,
SCC_CAN1,
SCC_ADC0 = ((u32)&SYSCTL_SCGCADC - SYSCTL_BASE) << 5,
SCC_ADC1,
SCC_ACMP0 = ((u32)&SYSCTL_SCGCACMP - SYSCTL_BASE) << 5,
SCC_PWM0 = ((u32)&SYSCTL_SCGCPWM - SYSCTL_BASE) << 5,
SCC_PWM1,
SCC_QEI0 = ((u32)&SYSCTL_SCGCQEI - SYSCTL_BASE) << 5,
SCC_QEI1,
SCC_EEPROM0 = ((u32)&SYSCTL_SCGCEEPROM - SYSCTL_BASE) << 5,
SCC_WTIMER0 = ((u32)&SYSCTL_SCGCWTIMER - SYSCTL_BASE) << 5,
SCC_WTIMER1,
SCC_WTIMER2,
SCC_WTIMER3,
SCC_WTIMER4,
SCC_WTIMER5,
/*
* Deep-sleep clock control
*/
DCC_WD0 = ((u32)&SYSCTL_DCGCWD - SYSCTL_BASE) << 5,
DCC_WD1,
DCC_TIMER0 = ((u32)&SYSCTL_DCGCTIMER - SYSCTL_BASE) << 5,
DCC_TIMER1,
DCC_TIMER2,
DCC_TIMER3,
DCC_TIMER4,
DCC_TIMER5,
DCC_GPIOA = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
DCC_GPIOB,
DCC_GPIOC,
DCC_GPIOD,
DCC_GPIOE,
DCC_GPIOF,
DCC_GPIOG,
DCC_GPIOH,
DCC_GPIOJ,
DCC_GPIOK,
DCC_GPIOL,
DCC_GPIOM,
DCC_GPION,
DCC_GPIOP,
DCC_GPIOQ,
DCC_DMA = ((u32)&SYSCTL_DCGCDMA - SYSCTL_BASE) << 5,
DCC_HIB = ((u32)&SYSCTL_DCGCGPIO - SYSCTL_BASE) << 5,
DCC_UART0 = ((u32)&SYSCTL_DCGCUART - SYSCTL_BASE) << 5,
DCC_UART1,
DCC_UART2,
DCC_UART3,
DCC_UART4,
DCC_UART5,
DCC_UART6,
DCC_UART7,
DCC_SSI0 = ((u32)&SYSCTL_DCGCSSI - SYSCTL_BASE) << 5,
DCC_SSI1,
DCC_SSI2,
DCC_SSI3,
DCC_I2C0 = ((u32)&SYSCTL_DCGCI2C - SYSCTL_BASE) << 5,
DCC_I2C1,
DCC_I2C2,
DCC_I2C3,
DCC_I2C4,
DCC_I2C5,
DCC_USB0 = ((u32)&SYSCTL_DCGCUSB - SYSCTL_BASE) << 5,
DCC_CAN0 = ((u32)&SYSCTL_DCGCCAN - SYSCTL_BASE) << 5,
DCC_CAN1,
DCC_ADC0 = ((u32)&SYSCTL_DCGCADC - SYSCTL_BASE) << 5,
DCC_ADC1,
DCC_ACMP0 = ((u32)&SYSCTL_DCGCACMP - SYSCTL_BASE) << 5,
DCC_PWM0 = ((u32)&SYSCTL_DCGCPWM - SYSCTL_BASE) << 5,
DCC_PWM1,
DCC_QEI0 = ((u32)&SYSCTL_DCGCQEI - SYSCTL_BASE) << 5,
DCC_QEI1,
DCC_EEPROM0 = ((u32)&SYSCTL_DCGCEEPROM - SYSCTL_BASE) << 5,
DCC_WTIMER0 = ((u32)&SYSCTL_DCGCWTIMER - SYSCTL_BASE) << 5,
DCC_WTIMER1,
DCC_WTIMER2,
DCC_WTIMER3,
DCC_WTIMER4,
DCC_WTIMER5,
} clken_t;
/* =============================================================================
* Function prototypes
* ---------------------------------------------------------------------------*/
BEGIN_DECLS
void periph_clock_enable(clken_t periph);
void periph_clock_disable(clken_t periph);
END_DECLS
#endif /* LM4F_SYSTEMCONTROL_H */