Merging pull request #23 Changed markup to get more control over documentation.

Merge remote-tracking branch 'ksarkies/doc'
2012-08-25 15:16:50 -07:00
parent f71742c5da 52533a6e3d
commit d98dab6ae2
19 changed files with 1588 additions and 290 deletions
--- a/include/libopencm3/cm3/docmain.h
+++ b/include/libopencm3/cm3/docmain.h
@@ -1,6 +1,12 @@
 /**
 * @mainpage libopencm3 Developer Documentation
- *
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+
+@date 18 August 2012
+
 * The libopencm3 project (previously known as libopenstm32) aims to create
 * a free/libre/open-source (GPL v3, or later) firmware library for various
 * ARM Cortex-M3 microcontrollers, including ST STM32, Toshiba TX03,
@@ -31,33 +37,33 @@ program.  If not, see <http://www.gnu.org/licenses/>.

 */

-/** @defgroup LM3S
+/** @defgroup LM3S LM3S
 Libraries for Texas instruments LM3S series.
 */

-/** @defgroup LPC13xx
+/** @defgroup LPC13xx LPC13xx
 Libraries for NXP Semiconductor LPC13xx series.
 */

-/** @defgroup LPC17xx
+/** @defgroup LPC17xx LPC17xx
 Libraries for NXP Semiconductor LPC17xx series.
 */

-/** @defgroup STM32F
+/** @defgroup STM32F STM32F
 Libraries for ST Microelectronics STM32F series.
 */

-/** @defgroup STM32F1xx
+/** @defgroup STM32F1xx STM32F1xx
@ingroup STM32F
 Libraries for ST Microelectronics STM32F1xx series.
 */

-/** @defgroup STM32F2xx
+/** @defgroup STM32F2xx STM32F2xx
@ingroup STM32F
 Libraries for ST Microelectronics STM32F2xx series.
 */

-/** @defgroup STM32F4xx
+/** @defgroup STM32F4xx STM32F4xx
@ingroup STM32F
 Libraries for ST Microelectronics STM32F4xx series.
 */
--- a/include/libopencm3/stm32/dac.h
+++ b/include/libopencm3/stm32/dac.h
@@ -1,27 +1,19 @@
-/** @file
+/** @defgroup STM32F_dac_defines DAC Defines

-@ingroup STM32F
+@brief <b>libopencm3 Defined Constants and Types for the STM32F Digital to Analog Converter </b>

-@brief <b>libopencm3 STM32F Digital to Analog Converter</b>
+@ingroup STM32F_defines

@version 1.0.0

@author @htmlonly &copy; @endhtmlonly 2012 Felix Held <felix-libopencm3@felixheld.de>
@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies

-@date 30 June 2012
+@date 18 August 2012

 LGPL License Terms @ref lgpl_license
 */
-/** @defgroup STM32F_dac_defines

-@brief Defined Constants and Types for the STM32F Digital to Analog Converter 
-
-@ingroup STM32F_defines
-
-LGPL License Terms @ref lgpl_license
-
- */
 /*
 * This file is part of the libopencm3 project.
 *
@@ -41,6 +33,8 @@ LGPL License Terms @ref lgpl_license
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */

+/**@{*/
+
 #ifndef LIBOPENCM3_DAC_H
 #define LIBOPENCM3_DAC_H

@@ -121,7 +115,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
 #define DAC_CR_MAMP2_10			(0x9 << DAC_CR_MAMP2_SHIFT)
 #define DAC_CR_MAMP2_11			(0xA << DAC_CR_MAMP2_SHIFT)
 #define DAC_CR_MAMP2_12			(0xB << DAC_CR_MAMP2_SHIFT)
-/*@}*/
+/**@}*/

 /* WAVE2[1:0]: DAC channel2 noise/triangle wave generation enable */
 /* Legend:
@@ -143,7 +137,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
@{*/
 #define DAC_CR_WAVE2_NOISE		(0x1 << DAC_CR_WAVE2_SHIFT)
 #define DAC_CR_WAVE2_TRI		(0x2 << DAC_CR_WAVE2_SHIFT)
-/*@}*/
+/**@}*/

 /* TSEL2[2:0]: DAC channel2 trigger selection */
 /* Legend:
@@ -193,7 +187,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n)-1
 #define DAC_CR_TSEL2_T4			(0x5 << DAC_CR_TSEL2_SHIFT)
 #define DAC_CR_TSEL2_E9			(0x6 << DAC_CR_TSEL2_SHIFT)
 #define DAC_CR_TSEL2_SW			(0x7 << DAC_CR_TSEL2_SHIFT)
-/*@}*/
+/**@}*/

 /* TEN2: DAC channel2 trigger enable */
 #define DAC_CR_TEN2			(1 << 18)
@@ -233,7 +227,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
 #define DAC_CR_MAMP1_10			(0x9 << DAC_CR_MAMP1_SHIFT)
 #define DAC_CR_MAMP1_11			(0xA << DAC_CR_MAMP1_SHIFT)
 #define DAC_CR_MAMP1_12			(0xB << DAC_CR_MAMP1_SHIFT)
-/*@}*/
+/**@}*/

 /* WAVE1[1:0]: DAC channel1 noise/triangle wave generation enable */
 /* Legend:
@@ -256,7 +250,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
@{*/
 #define DAC_CR_WAVE1_NOISE		(0x1 << DAC_CR_WAVE1_SHIFT)
 #define DAC_CR_WAVE1_TRI		(0x2 << DAC_CR_WAVE1_SHIFT)
-/*@}*/
+/**@}*/

 /* TSEL1[2:0]: DAC channel1 trigger selection */
 /* Legend:
@@ -306,7 +300,7 @@ Unmask bits [(n-1)..0] of LFSR/Triangle Amplitude equal to (2**(n+1)-1
 #define DAC_CR_TSEL1_T4			(0x5 << DAC_CR_TSEL1_SHIFT)
 #define DAC_CR_TSEL1_E9			(0x6 << DAC_CR_TSEL1_SHIFT)
 #define DAC_CR_TSEL1_SW			(0x7 << DAC_CR_TSEL1_SHIFT)
-/*@}*/
+/**@}*/

 /* TEN1: DAC channel1 trigger enable */
 #define DAC_CR_TEN1			(1 << 2)
@@ -416,3 +410,5 @@ void dac_load_data_buffer_dual(u32 dac_data1, u32 dac_data2, data_align dac_data
 void dac_software_trigger(data_channel dac_channel);

 #endif
+/**@}*/
+
--- a/include/libopencm3/stm32/doc-stm32f.h
+++ b/include/libopencm3/stm32/doc-stm32f.h
@@ -1,13 +1,24 @@
-/** @defgroup STM32F_defines
+/** @defgroup STM32F_defines STM32F Top Level Defines

@brief Defined Constants and Types for the STM32F series

@ingroup STM32F

+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+
@version 1.0.0

-@date 8 July 2012
+@date 18 August 2012

 LGPL License Terms @ref lgpl_license
 */

+/** @defgroup STM32F-files STM32F Top Level Files
+
+@brief Common Files for ST Microelectronics STM32F series.
+
+@ingroup STM32F
+
+*/
+
+
--- a/include/libopencm3/stm32/f1/dma.h
+++ b/include/libopencm3/stm32/f1/dma.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F1xx_dma_defines DMA Defines
+
+@ingroup STM32F1xx_defines
+
+@brief Defined Constants and Types for the STM32F1xx DMA Controller
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
 /*
 * This file is part of the libopencm3 project.
 *
@@ -18,6 +32,8 @@
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */

+/**@{*/
+
 #ifndef LIBOPENCM3_DMA_H
 #define LIBOPENCM3_DMA_H

@@ -241,24 +257,39 @@
 #define DMA_CCR_MEM2MEM			(1 << 14)

 /* PL[13:12]: Channel priority level */
+/** @defgroup dma_ch_pri DMA Channel Priority Levels
+@ingroup STM32F1xx_dma_defines
+
+@{*/
 #define DMA_CCR_PL_LOW			(0x0 << 12)
 #define DMA_CCR_PL_MEDIUM		(0x1 << 12)
 #define DMA_CCR_PL_HIGH			(0x2 << 12)
 #define DMA_CCR_PL_VERY_HIGH		(0x3 << 12)
+/**@}*/
 #define DMA_CCR_PL_MASK			(0x3 << 12)
 #define DMA_CCR_PL_SHIFT		12

 /* MSIZE[11:10]: Memory size */
+/** @defgroup dma_ch_memwidth DMA Channel Memory Word Width
+@ingroup STM32F1xx_dma_defines
+
+@{*/
 #define DMA_CCR_MSIZE_8BIT		(0x0 << 10)
 #define DMA_CCR_MSIZE_16BIT		(0x1 << 10)
 #define DMA_CCR_MSIZE_32BIT		(0x2 << 10)
+/**@}*/
 #define DMA_CCR_MSIZE_MASK		(0x3 << 10)
 #define DMA_CCR_MSIZE_SHIFT		10

 /* PSIZE[9:8]: Peripheral size */
+/** @defgroup dma_ch_perwidth DMA Channel Peripheral Word Width
+@ingroup STM32F1xx_dma_defines
+
+@{*/
 #define DMA_CCR_PSIZE_8BIT		(0x0 << 8)
 #define DMA_CCR_PSIZE_16BIT		(0x1 << 8)
 #define DMA_CCR_PSIZE_32BIT		(0x2 << 8)
+/**@}*/
 #define DMA_CCR_PSIZE_MASK		(0x3 << 8)
 #define DMA_CCR_PSIZE_SHIFT		8

@@ -300,6 +331,10 @@

 /* --- Generic values ------------------------------------------------------ */

+/** @defgroup dma_ch DMA Channel Number
+@ingroup STM32F1xx_dma_defines
+
+@{*/
 #define DMA_CHANNEL1			1
 #define DMA_CHANNEL2			2
 #define DMA_CHANNEL3			3
@@ -307,6 +342,7 @@
 #define DMA_CHANNEL5			5
 #define DMA_CHANNEL6			6
 #define DMA_CHANNEL7			7
+/**@}*/

 /* --- function prototypes ------------------------------------------------- */

@@ -333,3 +369,5 @@ void dma_set_memory_address(u32 dma, u8 channel, u32 address);
 void dma_set_number_of_data(u32 dma, u8 channel, u16 number);

 #endif
+/**@}*/
+
--- a/include/libopencm3/stm32/f1/doc-stm32f1.h
+++ b/include/libopencm3/stm32/f1/doc-stm32f1.h
@@ -1,12 +1,14 @@
-/** @defgroup STM32F1xx_defines
+/** @defgroup STM32F1xx_defines STM32F1xx Defines

@brief Defined Constants and Types for the STM32F1xx series

@ingroup STM32F1xx

+@author @htmlonly &copy; @endhtmlonly 2012 Ken Sarkies ksarkies@internode.on.net
+
@version 1.0.0

-@date 24 May 2012
+@date 18 August 2012

 LGPL License Terms @ref lgpl_license
 */
--- a/include/libopencm3/stm32/f1/gpio.h
+++ b/include/libopencm3/stm32/f1/gpio.h
@@ -1,3 +1,18 @@
+/** @defgroup STM32F1xx_gpio_defines GPIO Defines
+
+@brief <b>Defined Constants and Types for the STM32F1xx General Purpose I/O</b>
+
+@ingroup STM32F1xx_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>
+@author @htmlonly &copy; @endhtmlonly 2012 Piotr Esden-Tempski <piotr@esden.net>
+
+@date 1 July 2012
+
+LGPL License Terms @ref lgpl_license
+ */
 /*
 * This file is part of the libopencm3 project.
 *
@@ -17,6 +32,7 @@
 * You should have received a copy of the GNU Lesser General Public License
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */
+/**@{*/

 #ifndef LIBOPENCM3_GPIO_H
 #define LIBOPENCM3_GPIO_H
@@ -27,6 +43,10 @@
 /* --- Convenience macros -------------------------------------------------- */

 /* GPIO port base addresses (for convenience) */
+/** @defgroup gpio_port_id GPIO Port IDs
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define GPIOA				GPIO_PORT_A_BASE
 #define GPIOB				GPIO_PORT_B_BASE
 #define GPIOC				GPIO_PORT_C_BASE
@@ -34,8 +54,13 @@
 #define GPIOE				GPIO_PORT_E_BASE
 #define GPIOF				GPIO_PORT_F_BASE
 #define GPIOG				GPIO_PORT_G_BASE
+/**@}*/

 /* GPIO number definitions (for convenience) */
+/** @defgroup gpio_pin_id GPIO Pin Identifiers
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define GPIO0				(1 << 0)
 #define GPIO1				(1 << 1)
 #define GPIO2				(1 << 2)
@@ -53,6 +78,7 @@
 #define GPIO14				(1 << 14)
 #define GPIO15				(1 << 15)
 #define GPIO_ALL			0xffff
+/**@}*/

 /* --- Alternate function GPIOs -------------------------------------------- */

@@ -593,22 +619,50 @@

 /* --- GPIO_CRL/GPIO_CRH values -------------------------------------------- */

-/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
-#define GPIO_CNF_INPUT_ANALOG		0x00
-#define GPIO_CNF_INPUT_FLOAT		0x01	/* Default */
-#define GPIO_CNF_INPUT_PULL_UPDOWN	0x02
+/** @defgroup gpio_cnf GPIO Pin Configuration
+@ingroup STM32F1xx_gpio_defines
+If mode specifies input, configuration can be
+@li Analog input
+@li Floating input
+@li Pull up/down input

-/* Output mode (MODE[1:0]) values */
-#define GPIO_MODE_INPUT			0x00	/* Default */
+If mode specifies output, configuration can be
+@li Digital push-pull
+@li Digital open drain
+@li Alternate function push-pull or analog output
+@li Alternate function open drain or analog output
+@{*/
+/* CNF[1:0] values when MODE[1:0] is 00 (input mode) */
+/** Analog Input */
+#define GPIO_CNF_INPUT_ANALOG		0x00
+/** Digital Input Floating */
+#define GPIO_CNF_INPUT_FLOAT		0x01	/* Default */
+/** Digital Input Pull Up and Down */
+#define GPIO_CNF_INPUT_PULL_UPDOWN	0x02
+/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
+/** Digital Output Pushpull */
+#define GPIO_CNF_OUTPUT_PUSHPULL	0x00
+/** Digital Output Open Drain */
+#define GPIO_CNF_OUTPUT_OPENDRAIN	0x01
+/** Alternate Function Output Pushpull */
+#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL	0x02
+/** Alternate Function Output Open Drain */
+#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN	0x03
+/**@}*/
+
+/* Pin mode (MODE[1:0]) values */
+/** @defgroup gpio_mode GPIO Pin Mode
+@ingroup STM32F1xx_gpio_defines
+@li Input (default after reset)
+@li Output mode at 10 MHz maximum speed
+@li Output mode at 2 MHz maximum speed
+@li Output mode at 50 MHz maximum speed
+@{*/
+#define GPIO_MODE_INPUT				0x00	/* Default */
 #define GPIO_MODE_OUTPUT_10_MHZ		0x01
 #define GPIO_MODE_OUTPUT_2_MHZ		0x02
 #define GPIO_MODE_OUTPUT_50_MHZ		0x03
-
-/* CNF[1:0] values when MODE[1:0] is != 00 (one of the output modes) */
-#define GPIO_CNF_OUTPUT_PUSHPULL	0x00
-#define GPIO_CNF_OUTPUT_OPENDRAIN	0x01
-#define GPIO_CNF_OUTPUT_ALTFN_PUSHPULL	0x02
-#define GPIO_CNF_OUTPUT_ALTFN_OPENDRAIN	0x03
+/**@}*/

 /* --- GPIO_IDR values ----------------------------------------------------- */

@@ -652,19 +706,31 @@
 /* External interrupt configuration register 4 (AFIO_EXTICR4) */
 #define AFIO_EXTICR4			MMIO32(AFIO_BASE + 0x14)

+/* AF remap and debug I/O configuration register (AFIO_MAPR) */
+#define AFIO_MAPR2			MMIO32(AFIO_BASE + 0x1C)
+
 /* --- AFIO_EVCR values ---------------------------------------------------- */

 /* EVOE: Event output enable */
 #define AFIO_EVCR_EVOE			(1 << 7)

 /* PORT[2:0]: Port selection */
+/** @defgroup afio_evcr_port EVENTOUT Port selection
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define AFIO_EVCR_PORT_PA		(0x0 << 4)
 #define AFIO_EVCR_PORT_PB		(0x1 << 4)
 #define AFIO_EVCR_PORT_PC		(0x2 << 4)
 #define AFIO_EVCR_PORT_PD		(0x3 << 4)
 #define AFIO_EVCR_PORT_PE		(0x4 << 4)
+/**@}*/

 /* PIN[3:0]: Pin selection */
+/** @defgroup afio_evcr_pin EVENTOUT Pin selection
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define AFIO_EVCR_PIN_Px0		(0x0 << 0)
 #define AFIO_EVCR_PIN_Px1		(0x1 << 0)
 #define AFIO_EVCR_PIN_Px2		(0x2 << 0)
@@ -681,117 +747,206 @@
 #define AFIO_EVCR_PIN_Px13		(0xD << 0)
 #define AFIO_EVCR_PIN_Px14		(0xE << 0)
 #define AFIO_EVCR_PIN_Px15		(0xF << 0)
+/**@}*/

 /* --- AFIO_MAPR values ---------------------------------------------------- */

 /* 31 reserved */

-/* PTP_PPS_REMAP: Ethernet PTP PPS remapping
+/** @defgroup afio_remap_cld Alternate Function Remap Controls for Connectivity
+Line Devices only
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
+/* PTP_PPS_REMAP: *//** Ethernet PTP PPS remapping
 * (only connectivity line devices) */
 #define AFIO_MAPR_PTP_PPS_REMAP			(1 << 30)

-/* TIM2ITR1_IREMAP: TIM2 internal trigger 1 remapping
+/* TIM2ITR1_IREMAP: *//** TIM2 internal trigger 1 remapping
 * (only connectivity line devices) */
 #define AFIO_MAPR_TIM2ITR1_IREMAP		(1 << 29)

-/* SPI3_REMAP: SPI3/I2S3 remapping
+/* SPI3_REMAP: *//** SPI3/I2S3 remapping
 * (only connectivity line devices) */
 #define AFIO_MAPR_SPI3_REMAP			(1 << 28)

+/* MII_REMAP: */ /** MII or RMII selection
+ * (only connectivity line devices) */
+#define AFIO_MAPR_MII_RMII_SEL			(1 << 23)
+
+/* CAN2_REMAP: */ /**  CAN2 I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_CAN2_REMAP			(1 << 22)
+
+/* ETH_REMAP: */ /**  Ethernet MAC I/O remapping
+ * (only connectivity line devices) */
+#define AFIO_MAPR_ETH_REMAP			(1 << 21)
+
+/**@}*/
+
 /* 27 reserved */

 /* SWJ_CFG[2:0]: Serial wire JTAG configuration */
+/** @defgroup afio_swj_disable Serial Wire JTAG disables
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define AFIO_MAPR_SWJ_MASK			(0x7 << 24)
+/** Full Serial Wire JTAG capability */ 
 #define AFIO_MAPR_SWJ_CFG_FULL_SWJ		(0x0 << 24)
+/** Full Serial Wire JTAG capability without JNTRST */ 
 #define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_JNTRST	(0x1 << 24)
+/** JTAG-DP disabled with SW-DP enabled */
 #define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_ON	(0x2 << 24)
+/** JTAG-DP disabled and SW-DP disabled */
 #define AFIO_MAPR_SWJ_CFG_JTAG_OFF_SW_OFF	(0x4 << 24)
+/**@}*/

-/* MII_REMAP: MII or RMII selection
- * (only connectivity line devices) */
-#define AFIO_MAPR_MII_RMII_SEL			(1 << 23)
+/** @defgroup afio_remap Alternate Function Remap Controls
+@ingroup STM32F1xx_gpio_defines

-/* CAN2_REMAP: CAN2 I/O remapping
- * (only connectivity line devices) */
-#define AFIO_MAPR_CAN2_REMAP			(1 << 22)
-
-/* ETH_REMAP: Ethernet MAC I/O remapping
- * (only connectivity line devices) */
-#define AFIO_MAPR_ETH_REMAP			(1 << 21)
-
-/* ADC2_ETRGREG_REMAP: ADC2 external trigger regulator conversion remapping
+@{*/
+/* ADC2_ETRGREG_REMAP: */ /**  ADC2 external trigger regulator conversion remapping
 * (only low-, medium-, high- and XL-densitiy devices) */
 #define AFIO_MAPR_ADC2_ETRGREG_REMAP		(1 << 20)

-/* ADC2_ETRGINJ_REMAP: ADC2 external trigger injected conversion remapping
+/* ADC2_ETRGINJ_REMAP: */ /**  ADC2 external trigger injected conversion remapping
 * (only low-, medium-, high- and XL-densitiy devices) */
 #define AFIO_MAPR_ADC2_ETRGINJ_REMAP		(1 << 19)

-/* ADC1_ETRGREG_REMAP: ADC1 external trigger regulator conversion remapping
+/* ADC1_ETRGREG_REMAP: */ /**  ADC1 external trigger regulator conversion remapping
 * (only low-, medium-, high- and XL-densitiy devices) */
 #define AFIO_MAPR_ADC1_ETRGREG_REMAP		(1 << 18)

-/* ADC1_ETRGINJ_REMAP: ADC1 external trigger injected conversion remapping
+/* ADC1_ETRGINJ_REMAP: */ /**  ADC1 external trigger injected conversion remapping
 * (only low-, medium-, high- and XL-densitiy devices) */
 #define AFIO_MAPR_ADC1_ETRGINJ_REMAP		(1 << 17)

-/* TIM5CH4_IREMAP: TIM5 channel4 internal remap */
+/* TIM5CH4_IREMAP: */ /**  TIM5 channel4 internal remap */
 #define AFIO_MAPR_TIM5CH4_IREMAP		(1 << 16)

-/* PD01_REMAP: Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+/* PD01_REMAP: */ /**  Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
 #define AFIO_MAPR_PD01_REMAP			(1 << 15)

+/* TIM4_REMAP: */ /**  TIM4 remapping */
+#define AFIO_MAPR_TIM4_REMAP			(1 << 12)
+
+/* USART2_REMAP[1:0]: */ /**  USART2 remapping */
+#define AFIO_MAPR_USART2_REMAP			(1 << 3)
+
+/* USART1_REMAP[1:0]: */ /**  USART1 remapping */
+#define AFIO_MAPR_USART1_REMAP			(1 << 2)
+
+/* I2C1_REMAP[1:0]: */ /**  I2C1 remapping */
+#define AFIO_MAPR_I2C1_REMAP			(1 << 1)
+
+/* SPI1_REMAP[1:0]: */ /**  SPI1 remapping */
+#define AFIO_MAPR_SPI1_REMAP			(1 << 0)
+/**@}*/
+
 /* CAN_REMAP[1:0]: CAN1 alternate function remapping */
+/** @defgroup afio_remap_can1 Alternate Function Remap Controls for CAN 1
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define AFIO_MAPR_CAN1_REMAP_PORTA		(0x0 << 13)
 #define AFIO_MAPR_CAN1_REMAP_PORTB		(0x2 << 13) /* Not on 36pin pkg */
 #define AFIO_MAPR_CAN1_REMAP_PORTD		(0x3 << 13)
-
-/* TIM4_REMAP: TIM4 remapping */
-#define AFIO_MAPR_TIM4_REMAP			(1 << 12)
+/**@}*/

 /* TIM3_REMAP[1:0]: TIM3 remapping */
+/** @defgroup afio_remap_tim3 Alternate Function Remap Controls for Timer 3
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define AFIO_MAPR_TIM3_REMAP_NO_REMAP		(0x0 << 10)
 #define AFIO_MAPR_TIM3_REMAP_PARTIAL_REMAP	(0x2 << 10)
 #define AFIO_MAPR_TIM3_REMAP_FULL_REMAP		(0x3 << 10)
+/**@}*/

 /* TIM2_REMAP[1:0]: TIM2 remapping */
+/** @defgroup afio_remap_tim2 Alternate Function Remap Controls for Timer 2
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define AFIO_MAPR_TIM2_REMAP_NO_REMAP		(0x0 << 8)
 #define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP1	(0x1 << 8)
 #define AFIO_MAPR_TIM2_REMAP_PARTIAL_REMAP2	(0x2 << 8)
 #define AFIO_MAPR_TIM2_REMAP_FULL_REMAP		(0x3 << 8)
+/**@}*/

 /* TIM1_REMAP[1:0]: TIM1 remapping */
+/** @defgroup afio_remap_tim1 Alternate Function Remap Controls for Timer 1
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define AFIO_MAPR_TIM1_REMAP_NO_REMAP		(0x0 << 6)
 #define AFIO_MAPR_TIM1_REMAP_PARTIAL_REMAP	(0x1 << 6)
 #define AFIO_MAPR_TIM1_REMAP_FULL_REMAP		(0x3 << 6)
+/**@}*/

 /* USART3_REMAP[1:0]: USART3 remapping */
+/** @defgroup afio_remap_usart3 Alternate Function Remap Controls for USART 3
+@ingroup STM32F1xx_gpio_defines
+
+@{*/
 #define AFIO_MAPR_USART3_REMAP_NO_REMAP		(0x0 << 4)
 #define AFIO_MAPR_USART3_REMAP_PARTIAL_REMAP	(0x1 << 4)
 #define AFIO_MAPR_USART3_REMAP_FULL_REMAP	(0x3 << 4)
+/**@}*/

-/* USART2_REMAP[1:0]: USART2 remapping */
-#define AFIO_MAPR_USART2_REMAP			(1 << 3)
+/** @defgroup afio_remap2 Alternate Function Remap Controls Secondary Set
+@ingroup STM32F1xx_gpio_defines

-/* USART1_REMAP[1:0]: USART1 remapping */
-#define AFIO_MAPR_USART1_REMAP			(1 << 2)
+@{*/
+/* FSMC_NADV_DISCONNECT: */ /** The NADV is disconnected from its allocated pin */
+#define AFIO_MAPR2_FSMC_NADV_DISCONNECT			(1 << 10)

-/* I2C1_REMAP[1:0]: I2C1 remapping */
-#define AFIO_MAPR_I2C1_REMAP			(1 << 1)
+/* TIM14_REMAP: */ /**  TIM14 remapping */
+#define AFIO_MAPR2_TIM14_REMAP			(1 << 9)

-/* SPI1_REMAP[1:0]: SPI1 remapping */
-#define AFIO_MAPR_SPI1_REMAP			(1 << 0)
+/* TIM13_REMAP: */ /**  TIM13 remapping */
+#define AFIO_MAPR2_TIM13_REMAP			(1 << 8)
+
+/* TIM11_REMAP: */ /**  TIM11 remapping */
+#define AFIO_MAPR2_TIM11_REMAP			(1 << 7)
+
+/* TIM10_REMAP: */ /**  TIM10 remapping */
+#define AFIO_MAPR2_TIM10_REMAP			(1 << 6)
+
+/* TIM9_REMAP: */ /**  TIM9 remapping */
+#define AFIO_MAPR2_TIM9_REMAP			(1 << 5)
+
+/**@}*/

 /* --- AFIO_EXTICR1 values ------------------------------------------------- */
 /* --- AFIO_EXTICR2 values ------------------------------------------------- */
 /* --- AFIO_EXTICR3 values ------------------------------------------------- */
 /* --- AFIO_EXTICR4 values ------------------------------------------------- */

-/* EXTI0 - EXTI15 interrupt source selection registers */
+/** @defgroup afio_exti Alternate Function EXTI pin number
+@ingroup STM32F1xx_gpio_defines

-/* Note: For using them we should define a function that calculates the right
- *       registers, using definitions is probably not a good idea.
- */
+@{*/
+
+#define AFIO_EXTI0                 0
+#define AFIO_EXTI1                 1
+#define AFIO_EXTI2                 2
+#define AFIO_EXTI3                 3
+#define AFIO_EXTI4                 4
+#define AFIO_EXTI5                 5
+#define AFIO_EXTI6                 6
+#define AFIO_EXTI7                 7
+#define AFIO_EXTI8                 8
+#define AFIO_EXTI9                 9
+#define AFIO_EXTI10               10
+#define AFIO_EXTI11               11
+#define AFIO_EXTI12               12
+#define AFIO_EXTI13               13
+#define AFIO_EXTI14               14
+#define AFIO_EXTI15               15
+
+/**@}*/

 /* --- Function prototypes ------------------------------------------------- */

@@ -803,5 +958,10 @@ void gpio_toggle(u32 gpioport, u16 gpios);
 u16 gpio_port_read(u32 gpioport);
 void gpio_port_write(u32 gpioport, u16 data);
 void gpio_port_config_lock(u32 gpioport, u16 gpios);
+void gpio_set_eventout(u8 evoutport, u8 evoutpin);
+void gpio_primary_remap(u8 swjenable, u32 maps);
+void gpio_secondary_remap(u32 maps);

 #endif
+/**@}*/
+
--- a/include/libopencm3/stm32/f1/rcc.h
+++ b/include/libopencm3/stm32/f1/rcc.h
@@ -1,26 +1,17 @@
-/** @file
-
-@ingroup STM32F1xx
+/** @defgroup STM32F1xx_rcc_defines RCC Defines

@brief <b>libopencm3 STM32F1xx Reset and Clock Control</b>

+@ingroup STM32F1xx_defines
+
@version 1.0.0

@author @htmlonly &copy; @endhtmlonly 2009 Federico Ruiz-Ugalde \<memeruiz at gmail dot com\>
@author @htmlonly &copy; @endhtmlonly 2009 Uwe Hermann <uwe@hermann-uwe.de>

-@date 18 May 2012
+@date 18 August 2012

 LGPL License Terms @ref lgpl_license
- */
-/** @defgroup STM32F1xx_rcc_defines
-
-@brief Defined Constants and Types for the STM32F1xx Reset and Clock Control
-
-@ingroup STM32F1xx_defines
-
-LGPL License Terms @ref lgpl_license
-
 */
 /*
 * This file is part of the libopencm3 project.
@@ -41,6 +32,7 @@ LGPL License Terms @ref lgpl_license
 * You should have received a copy of the GNU Lesser General Public License
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */
+/**@{*/

 #ifndef LIBOPENCM3_RCC_H
 #define LIBOPENCM3_RCC_H
@@ -86,6 +78,10 @@ LGPL License Terms @ref lgpl_license
 /* --- RCC_CFGR values ----------------------------------------------------- */

 /* MCO: Microcontroller clock output */
+/** @defgroup rcc_cfgr_co RCC_CFGR Microcontroller Clock Output Source
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_MCO_NOCLK			0x0
 #define RCC_CFGR_MCO_SYSCLK			0x4
 #define RCC_CFGR_MCO_HSICLK			0x5
@@ -95,16 +91,26 @@ LGPL License Terms @ref lgpl_license
 #define RCC_CFGR_MCO_PLL3CLK_DIV2		0x9 /* (**) */
 #define RCC_CFGR_MCO_XT1			0xa /* (**) */
 #define RCC_CFGR_MCO_PLL3			0xb /* (**) */
+/**@}*/

 /* USBPRE: USB prescaler (RCC_CFGR[22]) */
+/** @defgroup rcc_cfgr_usbpre RCC_CFGR USB prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_USBPRE_PLL_CLK_DIV1_5		0x0
 #define RCC_CFGR_USBPRE_PLL_CLK_NODIV		0x1
+/**@}*/

 /* OTGFSPRE: USB OTG FS prescaler (RCC_CFGR[22]; only in conn. line STM32s) */
 #define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV3	0x0
 #define RCC_CFGR_USBPRE_PLL_VCO_CLK_DIV2	0x1

 /* PLLMUL: PLL multiplication factor */
+/** @defgroup rcc_cfgr_pmf RCC_CFGR PLL Multiplication Factor
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL2		0x0 /* (XX) */
 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL3		0x1 /* (XX) */
 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL4		0x2
@@ -122,38 +128,69 @@ LGPL License Terms @ref lgpl_license
 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL6_5		0xd /* 0xd: PLL x 6.5 for conn. line */
 #define RCC_CFGR_PLLMUL_PLL_CLK_MUL16		0xe /* (XX) */
 // #define PLLMUL_PLL_CLK_MUL16		0xf /* (XX) */ /* Errata? 17? */
+/**@}*/

 /* TODO: conn. line differs. */
 /* PLLXTPRE: HSE divider for PLL entry */
+/** @defgroup rcc_cfgr_hsepre RCC_CFGR HSE Divider for PLL
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_PLLXTPRE_HSE_CLK		0x0
 #define RCC_CFGR_PLLXTPRE_HSE_CLK_DIV2		0x1
+/**@}*/

 /* PLLSRC: PLL entry clock source */
+/** @defgroup rcc_cfgr_pcs RCC_CFGR PLL Clock Source
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_PLLSRC_HSI_CLK_DIV2		0x0
 #define RCC_CFGR_PLLSRC_HSE_CLK			0x1
 #define RCC_CFGR_PLLSRC_PREDIV1_CLK		0x1 /* On conn. line */
+/**@}*/

 /* ADCPRE: ADC prescaler */
+/****************************************************************************/
+/** @defgroup rcc_cfgr_adcpre RCC ADC Clock Prescaler enable values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_ADCPRE_PCLK2_DIV2		0x0
 #define RCC_CFGR_ADCPRE_PCLK2_DIV4		0x1
 #define RCC_CFGR_ADCPRE_PCLK2_DIV6		0x2
 #define RCC_CFGR_ADCPRE_PCLK2_DIV8		0x3
+/**@}*/

 /* PPRE2: APB high-speed prescaler (APB2) */
+/** @defgroup rcc_cfgr_apb2pre RCC_CFGR APB2 Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_PPRE2_HCLK_NODIV		0x0
 #define RCC_CFGR_PPRE2_HCLK_DIV2		0x4
 #define RCC_CFGR_PPRE2_HCLK_DIV4		0x5
 #define RCC_CFGR_PPRE2_HCLK_DIV8		0x6
 #define RCC_CFGR_PPRE2_HCLK_DIV16		0x7
+/**@}*/

 /* PPRE1: APB low-speed prescaler (APB1) */
+/** @defgroup rcc_cfgr_apb1pre RCC_CFGR APB1 Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_PPRE1_HCLK_NODIV		0x0
 #define RCC_CFGR_PPRE1_HCLK_DIV2		0x4
 #define RCC_CFGR_PPRE1_HCLK_DIV4		0x5
 #define RCC_CFGR_PPRE1_HCLK_DIV8		0x6
 #define RCC_CFGR_PPRE1_HCLK_DIV16		0x7
+/**@}*/

 /* HPRE: AHB prescaler */
+/** @defgroup rcc_cfgr_ahbpre RCC_CFGR AHB Prescale Factors
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_HPRE_SYSCLK_NODIV		0x0
 #define RCC_CFGR_HPRE_SYSCLK_DIV2		0x8
 #define RCC_CFGR_HPRE_SYSCLK_DIV4		0x9
@@ -163,6 +200,7 @@ LGPL License Terms @ref lgpl_license
 #define RCC_CFGR_HPRE_SYSCLK_DIV128		0xd
 #define RCC_CFGR_HPRE_SYSCLK_DIV256		0xe
 #define RCC_CFGR_HPRE_SYSCLK_DIV512		0xf
+/**@}*/

 /* SWS: System clock switch status */
 #define RCC_CFGR_SWS_SYSCLKSEL_HSICLK		0x0
@@ -170,9 +208,14 @@ LGPL License Terms @ref lgpl_license
 #define RCC_CFGR_SWS_SYSCLKSEL_PLLCLK		0x2

 /* SW: System clock switch */
+/** @defgroup rcc_cfgr_scs RCC_CFGR System Clock Selection
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_CFGR_SW_SYSCLKSEL_HSICLK		0x0
 #define RCC_CFGR_SW_SYSCLKSEL_HSECLK		0x1
 #define RCC_CFGR_SW_SYSCLKSEL_PLLCLK		0x2
+/**@}*/

 /* --- RCC_CIR values ------------------------------------------------------ */

@@ -211,6 +254,10 @@ LGPL License Terms @ref lgpl_license

 /* --- RCC_APB2RSTR values ------------------------------------------------- */

+/** @defgroup rcc_apb2rstr_rst RCC_APB2RSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_APB2RSTR_ADC3RST			(1 << 15) /* (XX) */
 #define RCC_APB2RSTR_USART1RST			(1 << 14)
 #define RCC_APB2RSTR_TIM8RST			(1 << 13) /* (XX) */
@@ -226,9 +273,14 @@ LGPL License Terms @ref lgpl_license
 #define RCC_APB2RSTR_IOPBRST			(1 << 3)
 #define RCC_APB2RSTR_IOPARST			(1 << 2)
 #define RCC_APB2RSTR_AFIORST			(1 << 0)
+/**@}*/

 /* --- RCC_APB1RSTR values ------------------------------------------------- */

+/** @defgroup rcc_apb1rstr_rst RCC_APB1RSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_APB1RSTR_DACRST			(1 << 29)
 #define RCC_APB1RSTR_PWRRST			(1 << 28)
 #define RCC_APB1RSTR_BKPRST			(1 << 27)
@@ -251,6 +303,7 @@ LGPL License Terms @ref lgpl_license
 #define RCC_APB1RSTR_TIM4RST			(1 << 2)
 #define RCC_APB1RSTR_TIM3RST			(1 << 1)
 #define RCC_APB1RSTR_TIM2RST			(1 << 0)
+/**@}*/

 /* --- RCC_AHBENR values --------------------------------------------------- */

@@ -269,7 +322,7 @@ LGPL License Terms @ref lgpl_license
 #define RCC_AHBENR_SRAMEN			(1 << 2)
 #define RCC_AHBENR_DMA2EN			(1 << 1)
 #define RCC_AHBENR_DMA1EN			(1 << 0)
-/*@}*/
+/**@}*/

 /* --- RCC_APB2ENR values -------------------------------------------------- */

@@ -292,7 +345,7 @@ LGPL License Terms @ref lgpl_license
 #define RCC_APB2ENR_IOPBEN			(1 << 3)
 #define RCC_APB2ENR_IOPAEN			(1 << 2)
 #define RCC_APB2ENR_AFIOEN			(1 << 0)
-/*@}*/
+/**@}*/

 /* --- RCC_APB1ENR values -------------------------------------------------- */

@@ -322,7 +375,7 @@ LGPL License Terms @ref lgpl_license
 #define RCC_APB1ENR_TIM4EN			(1 << 2)
 #define RCC_APB1ENR_TIM3EN			(1 << 1)
 #define RCC_APB1ENR_TIM2EN			(1 << 0)
-/*@}*/
+/**@}*/

 /* --- RCC_BDCR values ----------------------------------------------------- */

@@ -347,8 +400,13 @@ LGPL License Terms @ref lgpl_license

 /* --- RCC_AHBRSTR values -------------------------------------------------- */

+/** @defgroup rcc_ahbrstr_rst RCC_AHBRSTR reset values
+@ingroup STM32F1xx_rcc_defines
+
+@{*/
 #define RCC_AHBRSTR_ETHMACRST			(1 << 14)
 #define RCC_AHBRSTR_OTGFSRST			(1 << 12)
+/**@}*/

 /* --- RCC_CFGR2 values ---------------------------------------------------- */

@@ -447,10 +505,6 @@ void rcc_set_usbpre(u32 usbpre);
 u32 rcc_get_system_clock_source(int i);
 void rcc_clock_setup_in_hsi_out_64mhz(void);
 void rcc_clock_setup_in_hsi_out_48mhz(void);
-
-/**
- * Maximum speed possible for F100 (Value Line) on HSI
- */
 void rcc_clock_setup_in_hsi_out_24mhz(void);
 void rcc_clock_setup_in_hse_8mhz_out_24mhz(void);
 void rcc_clock_setup_in_hse_8mhz_out_72mhz(void);
@@ -459,3 +513,5 @@ void rcc_clock_setup_in_hse_16mhz_out_72mhz(void);
 void rcc_backupdomain_reset(void);

 #endif
+/**@}*/
+
--- a/include/libopencm3/stm32/iwdg.h
+++ b/include/libopencm3/stm32/iwdg.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F_iwdg_defines IWDG Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F Independent Watchdog Timer</b>
+
+@ingroup STM32F_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 18 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
 /*
 * This file is part of the libopencm3 project.
 *
@@ -17,6 +31,8 @@
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */

+/**@{*/
+
 #ifndef LIBOPENCM3_IWDG_H
 #define LIBOPENCM3_IWDG_H

@@ -42,9 +58,14 @@
 /* Bits [31:16]: Reserved. */

 /* KEY[15:0]: Key value (write-only, reads as 0x0000) */
+/** @defgroup iwdg_key IWDG Key Values
+@ingroup STM32F_iwdg_defines
+
+@{*/
 #define IWDG_KR_RESET			0xaaaa
 #define IWDG_KR_UNLOCK			0x5555
 #define IWDG_KR_START			0xcccc
+/**@}*/

 /* --- IWDG_PR values ------------------------------------------------------ */

@@ -52,6 +73,10 @@

 /* PR[2:0]: Prescaler divider */
 #define IWDG_PR_LSB			0
+/** @defgroup iwdg_prediv IWDG Prescaler divider
+@ingroup STM32F_iwdg_defines
+
+@{*/
 #define IWDG_PR_DIV4			0x0
 #define IWDG_PR_DIV8			0x1
 #define IWDG_PR_DIV16			0x2
@@ -59,6 +84,7 @@
 #define IWDG_PR_DIV64			0x4
 #define IWDG_PR_DIV128			0x5
 #define IWDG_PR_DIV256			0x6
+/**@}*/
 /* Double definition: 0x06 and 0x07 both mean DIV256 as per datasheet. */
 /* #define IWDG_PR_DIV256			0x7 */

@@ -87,3 +113,5 @@ bool iwdg_prescaler_busy(void);
 void iwdg_reset(void);

 #endif
+/**@}*/
+
--- a/include/libopencm3/stm32/pwr.h
+++ b/include/libopencm3/stm32/pwr.h
@@ -1,3 +1,17 @@
+/** @defgroup STM32F1xx_pwr_defines PWR Defines
+
+@ingroup STM32F_defines
+
+@brief <b>libopencm3 STM32F Power Control</b>
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 17 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
 /*
 * This file is part of the libopencm3 project.
 *
@@ -17,6 +31,8 @@
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */

+/**@{*/
+
 #ifndef LIBOPENCM3_PWR_H
 #define LIBOPENCM3_PWR_H

@@ -40,14 +56,20 @@

 /* PLS[7:5]: PVD level selection */
 #define PWR_CR_PLS_LSB			5
-#define PWR_CR_PLS_2V2			0x0
-#define PWR_CR_PLS_2V3			0x1
-#define PWR_CR_PLS_2V4			0x2
-#define PWR_CR_PLS_2V5			0x3
-#define PWR_CR_PLS_2V6			0x4
-#define PWR_CR_PLS_2V7			0x5
-#define PWR_CR_PLS_2V8			0x6
-#define PWR_CR_PLS_2V9			0x7
+/** @defgroup pwr_pls PVD level selection
+@ingroup STM32F_pwr_defines
+
+@{*/
+#define PWR_CR_PLS_2V2			(0x0 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V3			(0x1 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V4			(0x2 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V5			(0x3 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V6			(0x4 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V7			(0x5 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V8			(0x6 << PWR_CR_PLS_LSB)
+#define PWR_CR_PLS_2V9			(0x7 << PWR_CR_PLS_LSB)
+/**@}*/
+#define PWR_CR_PLS_MASK			(0x7 << PWR_CR_PLS_LSB)

 /* PVDE: Power voltage detector enable */
 #define PWR_CR_PVDE			(1 << 4)
@@ -84,6 +106,22 @@

 /* --- PWR function prototypes ------------------------------------------- */

-/* TODO */
+void pwr_disable_backup_domain_write_protect(void);
+void pwr_enable_backup_domain_write_protect(void);
+void pwr_enable_power_voltage_detect(u32 pvd_level);
+void pwr_disable_power_voltage_detect(void);
+void pwr_clear_standby_flag(void);
+void pwr_clear_wakeup_flag(void);
+void pwr_set_standby_mode(void);
+void pwr_set_stop_mode(void);
+void pwr_voltage_regulator_on_in_stop(void);
+void pwr_voltage_regulator_low_power_in_stop(void);
+void pwr_enable_wakeup_pin(void);
+void pwr_disable_wakeup_pin(void);
+bool pwr_voltage_high(void);
+bool pwr_get_standby_flag(void);
+bool pwr_get_wakeup_flag(void);

 #endif
+/**@}*/
+
--- a/include/libopencm3/stm32/systick.h
+++ b/include/libopencm3/stm32/systick.h
@@ -1,3 +1,18 @@
+/** @defgroup STM32F_systick_defines SysTick Defines
+
+@brief <b>libopencm3 Defined Constants and Types for the STM32F SysTick </b>
+
+@ingroup STM32F_defines
+
+@version 1.0.0
+
+@author @htmlonly &copy; @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
+
+@date 19 August 2012
+
+LGPL License Terms @ref lgpl_license
+ */
+
 /*
 * This file is part of the libopencm3 project.
 *
@@ -17,6 +32,8 @@
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */

+/**@{*/
+
 #ifndef LIBOPENCM3_SYSTICK_H
 #define LIBOPENCM3_SYSTICK_H

@@ -45,8 +62,14 @@
 /* CLKSOURCE: Clock source selection */
 #define STK_CTRL_CLKSOURCE		(1 << 2)
 #define STK_CTRL_CLKSOURCE_LSB		2
+/** @defgroup systick_clksource Clock source selection
+@ingroup STM32F_systick_defines
+
+@{*/
 #define STK_CTRL_CLKSOURCE_AHB_DIV8	0
 #define STK_CTRL_CLKSOURCE_AHB		1
+/**@}*/
+
 /* TICKINT: SysTick exception request enable */
 #define STK_CTRL_TICKINT		(1 << 1)
 /* ENABLE: Counter enable */
@@ -80,3 +103,5 @@ void systick_counter_disable(void);
 u8 systick_get_countflag(void);

 #endif
+/**@}*/
+
--- a/include/libopencm3/stm32/timer.h
+++ b/include/libopencm3/stm32/timer.h
@@ -1,8 +1,8 @@
-/** @file
+/** @defgroup STM32F_tim_defines Timers Defines

-@ingroup STM32F1xx
+@brief <b>libopencm3 Defined Constants and Types for the STM32F1xx Timers</b>

-@brief <b>libopencm3 STM32F1xx Timers</b>
+@ingroup STM32F_defines

@version 1.0.0

@@ -11,15 +11,6 @@
@date 18 May 2012

 LGPL License Terms @ref lgpl_license
- */
-/** @defgroup STM32F1xx_tim_defines
-
-@brief Defined Constants and Types for the STM32F1xx Timers
-
-@ingroup STM32F1xx_defines
-
-LGPL License Terms @ref lgpl_license
-
 */
 /*
 * This file is part of the libopencm3 project.
@@ -40,6 +31,8 @@ LGPL License Terms @ref lgpl_license
 * along with this library.  If not, see <http://www.gnu.org/licenses/>.
 */

+/**@{*/
+
 #ifndef LIBOPENCM3_TIMER_H
 #define LIBOPENCM3_TIMER_H

@@ -62,7 +55,7 @@ LGPL License Terms @ref lgpl_license
 #define TIM6				TIM6_BASE
 #define TIM7				TIM7_BASE
 #define TIM8				TIM8_BASE
-/*@}*/
+/**@}*/

 /* --- Timer registers ----------------------------------------------------- */

@@ -266,7 +259,7 @@ LGPL License Terms @ref lgpl_license
 #define TIM_CR1_CKD_CK_INT_MUL_2	(0x1 << 8)
 #define TIM_CR1_CKD_CK_INT_MUL_4	(0x2 << 8)
 #define TIM_CR1_CKD_CK_INT_MASK		(0x3 << 8)
-/*@}*/
+/**@}*/

 /* ARPE: Auto-reload preload enable */
 #define TIM_CR1_ARPE			(1 << 7)
@@ -282,7 +275,7 @@ LGPL License Terms @ref lgpl_license
 #define TIM_CR1_CMS_CENTER_2		(0x2 << 5)
 #define TIM_CR1_CMS_CENTER_3		(0x3 << 5)
 #define TIM_CR1_CMS_MASK		(0x3 << 5)
-/*@}*/
+/**@}*/

 /* DIR: Direction */
 /****************************************************************************/
@@ -292,7 +285,7 @@ LGPL License Terms @ref lgpl_license
@{*/
 #define TIM_CR1_DIR_UP			(0 << 4)
 #define TIM_CR1_DIR_DOWN		(1 << 4)
-/*@}*/
+/**@}*/

 /* OPM: One pulse mode */
 #define TIM_CR1_OPM			(1 << 3)
@@ -334,7 +327,7 @@ LGPL License Terms @ref lgpl_license
 /* OIS1:*//** Output idle state 1 (OC1 output) */
 #define TIM_CR2_OIS1			(1 << 8)
 #define TIM_CR2_OIS_MASK		(0x7f << 8)
-/*@}*/
+/**@}*/

 /* TI1S: TI1 selection */
 #define TIM_CR2_TI1S			(1 << 7)
@@ -354,7 +347,7 @@ LGPL License Terms @ref lgpl_license
 #define TIM_CR2_MMS_COMPARE_OC3REF	(0x6 << 4)
 #define TIM_CR2_MMS_COMPARE_OC4REF	(0x7 << 4)
 #define TIM_CR2_MMS_MASK		(0x7 << 4)
-/*@}*/
+/**@}*/

 /* CCDS: Capture/compare DMA selection */
 #define TIM_CR2_CCDS			(1 << 3)
@@ -424,7 +417,7 @@ LGPL License Terms @ref lgpl_license
 /** External Trigger input (ETRF) */
 #define TIM_SMCR_TS_ETRF		(0x7 << 4)
 #define TIM_SMCR_TS_MASK		(0x7 << 4)
-/*@}*/
+/**@}*/

 /* SMS[2:0]: Slave mode selection */
 /** @defgroup tim_sms SMS Slave mode selection
@@ -452,7 +445,7 @@ and generates an update of the registers. */
 /** External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. */
 #define TIM_SMCR_SMS_ECM1		(0x7 << 0)
 #define TIM_SMCR_SMS_MASK		(0x7 << 0)
-/*@}*/
+/**@}*/

 /* --- TIMx_DIER values ---------------------------------------------------- */

@@ -505,7 +498,7 @@ and generates an update of the registers. */

 /* UIE:*//** Update interrupt enable */
 #define TIM_DIER_UIE			(1 << 0)
-/*@}*/
+/**@}*/

 /* --- TIMx_SR values ------------------------------------------------------ */
 /****************************************************************************/
@@ -549,7 +542,7 @@ and generates an update of the registers. */

 /* UIF:*//** Update interrupt flag */
 #define TIM_SR_UIF			(1 << 0)
-/*@}*/
+/**@}*/

 /* --- TIMx_EGR values ----------------------------------------------------- */

@@ -582,7 +575,7 @@ and generates an update of the registers. */

 /* UG:*//** Update generation */
 #define TIM_EGR_UG			(1 << 0)
-/*@}*/
+/**@}*/

 /* --- TIMx_CCMR1 values --------------------------------------------------- */

@@ -923,7 +916,7 @@ and generates an update of the registers. */
 #define TIM_BDTR_LOCK_LEVEL_2		(0x2 << 8)
 #define TIM_BDTR_LOCK_LEVEL_3		(0x3 << 8)
 #define TIM_BDTR_LOCK_MASK		(0x3 << 8)
-/*@}*/
+/**@}*/

 /* DTG[7:0]: Dead-time generator set-up */
 #define TIM_BDTR_DTG_MASK		0x00FF
@@ -1107,6 +1100,7 @@ void timer_slave_set_prescaler(u32 timer, enum tim_ic_psc psc);
 void timer_slave_set_polarity(u32 timer, enum tim_ic_pol pol);
 void timer_slave_set_mode(u32 timer, u8 mode);
 void timer_slave_set_trigger(u32 timer, u8 trigger);
-void timer_force_event(u32 timer, u8 event);

 #endif
+/**@}*/
+