diff --git a/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders b/include/libopencm3/efm32/tinygecko/cmu.convenienceheaders new file mode 100644 index 00000000..e69de29b diff --git a/include/libopencm3/efm32/tinygecko/cmu.h b/include/libopencm3/efm32/tinygecko/cmu.h index 19accd59..09145614 100644 --- a/include/libopencm3/efm32/tinygecko/cmu.h +++ b/include/libopencm3/efm32/tinygecko/cmu.h @@ -21,12 +21,12 @@ * @see EFM32TG_CMU */ -/** Definitions for the CMU (Clock Management Unit). +/** Definitions for the CMU subsystem (Clock Management Unit). * * This corresponds to the description in d0034_efm32tg_reference_manual.pdf * section 11. * - * @defgroup EFM32TG_CMU EFM32 Tiny Geco CMU + * @defgroup EFM32TG_CMU EFM32 Tiny Gecko CMU * @{ */ @@ -42,64 +42,514 @@ * @{ */ -/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4. +/** These definitions reflect d0034_efm32tg_reference_manual.pdf section 11.4 * * @defgroup EFM32TG_CMU_registers EFM32 Tiny Gecko CMU registers * @{ */ -#define CMU_CTRL MMIO32(CMU_BASE + 0x000) -#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) -#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) -#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00C) -#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) -#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) -#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) -#define CMU_CALCNT MMIO32(CMU_BASE + 0x01C) -#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) -#define CMU_CMD MMIO32(CMU_BASE + 0x024) -#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) -#define CMU_STATUS MMIO32(CMU_BASE + 0x02C) -#define CMU_IF MMIO32(CMU_BASE + 0x030) -#define CMU_IFS MMIO32(CMU_BASE + 0x034) -#define CMU_IFC MMIO32(CMU_BASE + 0x038) -#define CMU_IEN MMIO32(CMU_BASE + 0x03C) -#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) -#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) -#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) -#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) -#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) -#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) -#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) -#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) -#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) -#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07C) -#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) -#define CMU_LOCK MMIO32(CMU_BASE + 0x084) +#define CMU_CTRL MMIO32(CMU_BASE + 0x000) /**< @see EFM32TG_CMU_CTRL_bits */ +#define CMU_HFCORECLKDIV MMIO32(CMU_BASE + 0x004) /**< @see EFM32TG_CMU_HFCORECLKDIV_values */ +#define CMU_HFPERCLKDIV MMIO32(CMU_BASE + 0x008) /**< @see EFM32TG_CMU_HFPERCLKDIV_bits */ +#define CMU_HFRCOCTRL MMIO32(CMU_BASE + 0x00c) /**< @see EFM32TG_CMU_HFRCOCTRL_bits */ +#define CMU_LFRCOCTRL MMIO32(CMU_BASE + 0x010) /**< @see EFM32TG_CMU_LFRCOCTRL_bits */ +#define CMU_AUXHFRCOCTRL MMIO32(CMU_BASE + 0x014) /**< @see EFM32TG_CMU_AUXHFRCOCTRL_bits */ +#define CMU_CALCTRL MMIO32(CMU_BASE + 0x018) /**< @see EFM32TG_CMU_CALCTRL_bits */ +#define CMU_CALCNT MMIO32(CMU_BASE + 0x01c) /**< @see EFM32TG_CMU_CALCNT_bits */ +#define CMU_OSCENCMD MMIO32(CMU_BASE + 0x020) /**< @see EFM32TG_CMU_OSCENCMD_bits */ +#define CMU_CMD MMIO32(CMU_BASE + 0x024) /**< @see EFM32TG_CMU_CMD_bits */ +#define CMU_LFCLKSEL MMIO32(CMU_BASE + 0x028) /**< @see EFM32TG_CMU_LFCLKSEL_bits */ +#define CMU_STATUS MMIO32(CMU_BASE + 0x02c) /**< @see EFM32TG_CMU_STATUS_bits */ +#define CMU_IF MMIO32(CMU_BASE + 0x030) /**< @see EFM32TG_CMU_IF_bits */ +#define CMU_IFS MMIO32(CMU_BASE + 0x034) /**< @see EFM32TG_CMU_IFS_bits */ +#define CMU_IFC MMIO32(CMU_BASE + 0x038) /**< @see EFM32TG_CMU_IFC_bits */ +#define CMU_IEN MMIO32(CMU_BASE + 0x03c) /**< @see EFM32TG_CMU_IEN_bits */ +#define CMU_HFCORECLKEN0 MMIO32(CMU_BASE + 0x040) /**< @see EFM32TG_CMU_HFCORECLKEN0_bits */ +#define CMU_HFPERCLKEN0 MMIO32(CMU_BASE + 0x044) /**< @see EFM32TG_CMU_HFPERCLKEN0_bits */ +#define CMU_SYNCBUSY MMIO32(CMU_BASE + 0x050) /**< @see EFM32TG_CMU_SYNCBUSY_bits */ +#define CMU_FREEZE MMIO32(CMU_BASE + 0x054) /**< @see EFM32TG_CMU_FREEZE_bits */ +#define CMU_LFACLKEN0 MMIO32(CMU_BASE + 0x058) /**< @see EFM32TG_CMU_LFACLKEN0_bits */ +#define CMU_LFBCLKEN0 MMIO32(CMU_BASE + 0x060) /**< @see EFM32TG_CMU_LFBCLKEN0_bits */ +#define CMU_LFAPRESC0 MMIO32(CMU_BASE + 0x068) /**< @see EFM32TG_CMU_LFAPRESC0_bits */ +#define CMU_LFBPRESC0 MMIO32(CMU_BASE + 0x070) /**< @see EFM32TG_CMU_LFBPRESC0_bits */ +#define CMU_PCNTCTRL MMIO32(CMU_BASE + 0x078) /**< @see EFM32TG_CMU_PCNTCTRL_bits */ +#define CMU_LCDCTRL MMIO32(CMU_BASE + 0x07c) /**< @see EFM32TG_CMU_LCDCTRL_bits */ +#define CMU_ROUTE MMIO32(CMU_BASE + 0x080) /**< @see EFM32TG_CMU_ROUTE_bits */ +#define CMU_LOCK MMIO32(CMU_BASE + 0x084) /**< @see EFM32TG_CMU_LOCK_values */ /** @} */ -/** @} */ - -/** @} */ - -/** - * This section is incomplete because i'm impatient and want a working result - * quickly +/** Bit states for the CMU_CTRL register * - * @todo Include all bits and bit groups from the manual. + * See d0034_efm32tg_reference_manual.pdf section 11.5.1 for definitions. + * + * @defgroup EFM32TG_CMU_CTRL_bits EFM32 Tiny Gecko CMU CTRL bits + * @{ */ -#define CMU_HFPERCLKEN0_GPIO (1<<6) -#define CMU_LFCLKSEL_LFB_DISABLED (0<<2) -#define CMU_LFCLKSEL_LFB_LFRCO (1<<2) -#define CMU_LFCLKSEL_LFB_LFXO (2<<2) -#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (3<<2) -#define CMU_LFCLKSEL_LFB_MASK (0x03<<2) -#define CMU_LFCLKSEL_LFA_DISABLED 0 -#define CMU_LFCLKSEL_LFA_LFRCO 1 -#define CMU_LFCLKSEL_LFA_LFXO 2 -#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 3 -#define CMU_LFCLKSEL_LFA_MASK 0x03 +#define CMU_CTRL_DBGCLK_AUXHFRCO (0<<28) +#define CMU_CTRL_DBGCLK_HFCLK (1<<28) +#define CMU_CTRL_CLKOUTSEL1_LFRCO (0<<23) +#define CMU_CTRL_CLKOUTSEL1_LFXO (1<<23) +#define CMU_CTRL_CLKOUTSEL1_HFCLK (2<<23) +#define CMU_CTRL_CLKOUTSEL1_LFXOQ (3<<23) +#define CMU_CTRL_CLKOUTSEL1_HFXOQ (4<<23) +#define CMU_CTRL_CLKOUTSEL1_LFRCOQ (5<<23) +#define CMU_CTRL_CLKOUTSEL1_HFRCOQ (6<<23) +#define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (7<<23) +#define CMU_CTRL_CLKOUTSEL0_LFRCO (0<<20) +#define CMU_CTRL_CLKOUTSEL0_LFXO (1<<20) +#define CMU_CTRL_CLKOUTSEL0_HFCLK (2<<20) +#define CMU_CTRL_CLKOUTSEL0_LFXOQ (3<<20) +#define CMU_CTRL_CLKOUTSEL0_HFXOQ (4<<20) +#define CMU_CTRL_CLKOUTSEL0_LFRCOQ (5<<20) +#define CMU_CTRL_CLKOUTSEL0_HFRCOQ (6<<20) +#define CMU_CTRL_CLKOUTSEL0_AUXHFRCOQ (7<<20) +#define CMU_CTRL_LFXOTIMEOUT_8CYCLES (0<<18) +#define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (1<<18) +#define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (2<<18) +#define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (3<<18) +#define CMU_CTRL_LFXOBUFCUR (1<<17) +#define CMU_CTRL_LXFOBOOST_70PCENT (0<<13) +#define CMU_CTRL_LXFOBOOST_100PCENT (1<<13) +#define CMU_CTRL_LFXOMODE_XTAL (0<<11) +#define CMU_CTRL_LFXOMODE_BUFEXTCLK (1<<11) +#define CMU_CTRL_LFXOMODE_DIGEXTCLK (2<<11) +#define CMU_CTRL_HFXOTIMEOUT_8CYCLES (0<<9) +#define CMU_CTRL_HFXOTIMEOUT_256CYCLES (1<<9) +#define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (2<<9) +#define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (3<<9) +#define CMU_CTRL_HFXOGLITCHDETEN (1<<7) +/* No values defined for the field HFXOBUFCUR */ +#define CMU_CTRL_HFXOBOOST_50PCENT (0<<2) +#define CMU_CTRL_HFXOBOOST_70PCENT (1<<2) +#define CMU_CTRL_HFXOBOOST_80PCENT (2<<2) +#define CMU_CTRL_HFXOBOOST_100PCENT (3<<2) +#define CMU_CTRL_HFXOMODE_XTAL (0<<0) +#define CMU_CTRL_HFXOMODE_BUFEXTCLK (1<<0) +#define CMU_CTRL_HFXOMODE_DIGEXTCLK (2<<0) + +/** @} */ + +/** Values for the CMU_HFCORECLKDIV register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.2 for definitions. + * + * @defgroup EFM32TG_CMU_HFCORECLKDIV_values EFM32 Tiny Gecko CMU HFCORECLKDIV + * values + * @{ + */ + +#define CMU_HFCORECLKDIV_HFCLK 0 +#define CMU_HFCORECLKDIV_HFCLK2 1 +#define CMU_HFCORECLKDIV_HFCLK4 2 +#define CMU_HFCORECLKDIV_HFCLK8 3 +#define CMU_HFCORECLKDIV_HFCLK16 4 +#define CMU_HFCORECLKDIV_HFCLK32 5 +#define CMU_HFCORECLKDIV_HFCLK64 6 +#define CMU_HFCORECLKDIV_HFCLK128 7 +#define CMU_HFCORECLKDIV_HFCLK256 8 +#define CMU_HFCORECLKDIV_HFCLK512 9 + +/** @} */ + +/** Bit states for the CMU_HFPERCLKDIV register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.3 for definitions. + * + * @defgroup EFM32TG_CMU_HFPERCLKDIV_bits EFM32 Tiny Gecko CMU HFPERCLKDIV bits + * @{ + */ + +#define CMU_HFPERCLKDIV_HFPERCLKEN (1<<8) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (0<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (1<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (2<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (3<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (4<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (5<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (6<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (7<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (8<<0) +#define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (9<<0) + +/** @} */ + +/** Bit states for the CMU_HFRCOCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.4 for definitions. + * + * @defgroup EFM32TG_CMU_HFRCOCTRL_bits EFM32 Tiny Gecko CMU HFRCOCTRL bits + * @{ + */ + +/* No values defined for the field SUDELAY */ +#define CMU_HFRCOCTRL_BAND_1MHZ (0<<8) +#define CMU_HFRCOCTRL_BAND_7MHZ (1<<8) +#define CMU_HFRCOCTRL_BAND_11MHZ (2<<8) +#define CMU_HFRCOCTRL_BAND_14MHZ (3<<8) +#define CMU_HFRCOCTRL_BAND_21MHZ (4<<8) +#define CMU_HFRCOCTRL_BAND_28MHZ (5<<8) +/* No values defined for the field TUNING */ + +/** @} */ + +/** Bit states for the CMU_AUXHFRCOCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.6 for definitions. + * + * @defgroup EFM32TG_CMU_AUXHFRCOCTRL_bits EFM32 Tiny Gecko CMU AUXHFRCOCTRL + * bits + * @{ + */ + +#define CMU_AUXHFRCOCTRL_BAND_14MHZ (0<<8) +#define CMU_AUXHFRCOCTRL_BAND_11MHZ (1<<8) +#define CMU_AUXHFRCOCTRL_BAND_7MHZ (2<<8) +#define CMU_AUXHFRCOCTRL_BAND_1MHZ (3<<8) +#define CMU_AUXHFRCOCTRL_BAND_28MHZ (6<<8) +#define CMU_AUXHFRCOCTRL_BAND_21MHZ (7<<8) +/* No values defined for the field TUNING */ + +/** @} */ + +/** Bit states for the CMU_CALCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.6.7 for definitions. + * + * @defgroup EFM32TG_CMU_CALCTRL_bits EFM32 Tiny Gecko CMU CALCTRL bits + * @{ + */ + +#define CMU_CALCTRL_CONT (1<<6) +#define CMU_CALCTRL_DOWNSEL_HFCLK (0<<3) +#define CMU_CALCTRL_DOWNSEL_HFXO (1<<3) +#define CMU_CALCTRL_DOWNSEL_LFXO (2<<3) +#define CMU_CALCTRL_DOWNSEL_HFRCO (3<<3) +#define CMU_CALCTRL_DOWNSEL_LFRCO (4<<3) +#define CMU_CALCTRL_DOWNSEL_AUXHFRCO (5<<3) +#define CMU_CALCTRL_UPSEL_HFXO (0<<0) +#define CMU_CALCTRL_UPSEL_LFXO (1<<0) +#define CMU_CALCTRL_UPSEL_HFRCO (2<<0) +#define CMU_CALCTRL_UPSEL_LFRCO (3<<0) +#define CMU_CALCTRL_UPSEL_AUXHFRCO (4<<0) + +/** @} */ + +/** Bit states for the CMU_OSCENCMD register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.9 for definitions. + * + * @defgroup EFM32TG_CMU_OSCENCMD_bits EFM32 Tiny Gecko CMU OSCENCMD bits + * @{ + */ + +#define CMU_OSCENCMD_LFXODIS (1<<9) +#define CMU_OSCENCMD_LFXOEN (1<<8) +#define CMU_OSCENCMD_LFRCODIS (1<<7) +#define CMU_OSCENCMD_LFRCOEN (1<<6) +#define CMU_OSCENCMD_AUXHFRCODIS (1<<5) +#define CMU_OSCENCMD_AUXHFRCOEN (1<<4) +#define CMU_OSCENCMD_HFXODIS (1<<3) +#define CMU_OSCENCMD_HFXOEN (1<<2) +#define CMU_OSCENCMD_HFRCODIS (1<<1) +#define CMU_OSCENCMD_HFRCOEN (1<<0) + +/** @} */ + +/** Bit states for the CMU_CMD register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.10 for definitions. + * + * @defgroup EFM32TG_CMU_CMD_bits EFM32 Tiny Gecko CMU CMD bits + * @{ + */ + +#define CMU_CMD_CALSTOP (1<<4) +#define CMU_CMD_CALSTART (1<<3) +#define CMU_CMD_HFCLKSEL_HFRCO (1<<0) +#define CMU_CMD_HFCLKSEL_HFXO (2<<0) +#define CMU_CMD_HFCLKSEL_LFRCO (3<<0) +#define CMU_CMD_HFCLKSEL_LFXO (4<<0) + +/** @} */ + +/** Bit states for the CMU_LFCLKSEL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.11 for definitions. + * + * @defgroup EFM32TG_CMU_LFCLKSEL_bits EFM32 Tiny Gecko CMU LFCLKSEL bits + * @{ + */ + +#define CMU_LFCLKSEL_LFBE_DISABLED (0<<20) +#define CMU_LFCLKSEL_LFBE_ULFRCO (1<<20) +#define CMU_LFCLKSEL_LFAE_DISABLED (0<<16) +#define CMU_LFCLKSEL_LFAE_ULFRCO (1<<16) +#define CMU_LFCLKSEL_LFB_DISABLED (0<<2) +#define CMU_LFCLKSEL_LFB_LFRCO (1<<2) +#define CMU_LFCLKSEL_LFB_LFXO (2<<2) +#define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (3<<2) +#define CMU_LFCLKSEL_LFA_DISABLED (0<<0) +#define CMU_LFCLKSEL_LFA_LFRCO (1<<0) +#define CMU_LFCLKSEL_LFA_LFXO (2<<0) +#define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (3<<0) + +/** @} */ + +/** Bit states for the CMU_STATUS register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.12 for definitions. + * + * @defgroup EFM32TG_CMU_STATUS_bits EFM32 Tiny Gecko CMU STATUS bits + * @{ + */ + +#define CMU_STATUS_CALBSY (1<<14) +#define CMU_STATUS_LFXOSEL (1<<13) +#define CMU_STATUS_LFRCOSEL (1<<12) +#define CMU_STATUS_HFXOSEL (1<<11) +#define CMU_STATUS_HFRCOSEL (1<<10) +#define CMU_STATUS_LFXORDY (1<<9) +#define CMU_STATUS_LFXOENS (1<<8) +#define CMU_STATUS_LFRCORDY (1<<7) +#define CMU_STATUS_LFRCOENS (1<<6) +#define CMU_STATUS_AUXHFRCORDY (1<<5) +#define CMU_STATUS_AUXHFRCOENS (1<<4) +#define CMU_STATUS_HFXORDY (1<<3) +#define CMU_STATUS_HFXOENS (1<<2) +#define CMU_STATUS_HFRCORDY (1<<1) +#define CMU_STATUS_HFRCOENS (1<<0) + +/** @} */ + +/** Bit states for the CMU_HFCORECLKEN0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.17 for definitions. + * + * @defgroup EFM32TG_CMU_HFCORECLKEN0_bits EFM32 Tiny Gecko CMU HFCORECLKEN0 + * bits + * @{ + */ + +#define CMU_HFCORECLKEN0_LE (1<<2) +#define CMU_HFCORECLKEN0_DMA (1<<1) +#define CMU_HFCORECLKEN0_AES (1<<0) + +/** @} */ + +/** Bit states for the CMU_HFPERCLKEN0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.18 for definitions. + * + * @defgroup EFM32TG_CMU_HFPERCLKEN0_bits EFM32 Tiny Gecko CMU HFPERCLKEN0 bits + * @{ + */ + +#define CMU_HFPERCLKEN0_I2C0 (1<<11) +#define CMU_HFPERCLKEN0_DAC0 (1<<10) +#define CMU_HFPERCLKEN0_ADC0 (1<<9) +#define CMU_HFPERCLKEN0_PRS (1<<8) +#define CMU_HFPERCLKEN0_VCMP (1<<7) +#define CMU_HFPERCLKEN0_GPIO (1<<6) +#define CMU_HFPERCLKEN0_TIMER1 (1<<5) +#define CMU_HFPERCLKEN0_TIMER0 (1<<4) +#define CMU_HFPERCLKEN0_USART1 (1<<3) +#define CMU_HFPERCLKEN0_USART0 (1<<2) +#define CMU_HFPERCLKEN0_ACMP1 (1<<1) +#define CMU_HFPERCLKEN0_ACMP0 (1<<0) + +/** @} */ + +/** Bit states for the CMU_SYNCBUSY register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.19 for definitions. + * + * @defgroup EFM32TG_CMU_SYNCBUSY_bits EFM32 Tiny Gecko CMU SYNCBUSY bits + * @{ + */ + +#define CMU_SYNCBUSY_LFBPRESC0 (1<<6) +#define CMU_SYNCBUSY_LFBCLKEN0 (1<<4) +#define CMU_SYNCBUSY_LFAPRESC0 (1<<2) +#define CMU_SYNCBUSY_LFACLKEN0 (1<<0) + +/** @} */ + +/** Bit states for the CMU_FREEZE register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.20 for definitions. + * + * @defgroup EFM32TG_CMU_FREEZE_bits EFM32 Tiny Gecko CMU FREEZE bits + * @{ + */ + +#define CMU_FREEZE_REGFREEZE_UPDATE (0<<0) +#define CMU_FREEZE_REGFREEZE_FREEZE (1<<0) + +/** @} */ + +/** Bit states for the CMU_LFACLKEN0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.21 for definitions. + * + * @defgroup EFM32TG_CMU_LFACLKEN0_bits EFM32 Tiny Gecko CMU LFACLKEN0 bits + * @{ + */ + +#define CMU_LFACLKEN0_LCD (1<<3) +#define CMU_LFACLKEN0_LETIMER0 (1<<2) +#define CMU_LFACLKEN0_RTC (1<<1) +#define CMU_LFACLKEN0_LESENSE (1<<0) + +/** @} */ + +/** Bit states for the CMU_LFBCLKEN0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.22 for definitions. + * + * @defgroup EFM32TG_CMU_LFBCLKEN0_bits EFM32 Tiny Gecko CMU LFBCLKEN0 bits + * @{ + */ + +#define CMU_LFBCLKEN0_LEUART0 (1<<0) + +/** @} */ + +/** Bit states for the CMU_LFAPRESC0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.23 for definitions. + * + * @defgroup EFM32TG_CMU_LFAPRESC0_bits EFM32 Tiny Gecko CMU LFAPRESC0 bits + * @{ + */ + +#define CMU_LFAPRESC0_LCD_DIV16 (0<<12) +#define CMU_LFAPRESC0_LCD_DIV32 (1<<12) +#define CMU_LFAPRESC0_LCD_DIV64 (2<<12) +#define CMU_LFAPRESC0_LCD_DIV128 (3<<12) +#define CMU_LFAPRESC0_LETIMER0_DIV1 (0<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV2 (1<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV4 (2<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV8 (3<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV16 (4<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV32 (5<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV64 (6<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV128 (7<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV256 (8<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV512 (9<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV1024 (10<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV2048 (11<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV4096 (12<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV8192 (13<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV16384 (14<<8) +#define CMU_LFAPRESC0_LETIMER0_DIV32768 (15<<8) +#define CMU_LFAPRESC0_RTC_DIV1 (0<<4) +#define CMU_LFAPRESC0_RTC_DIV2 (1<<4) +#define CMU_LFAPRESC0_RTC_DIV4 (2<<4) +#define CMU_LFAPRESC0_RTC_DIV8 (3<<4) +#define CMU_LFAPRESC0_RTC_DIV16 (4<<4) +#define CMU_LFAPRESC0_RTC_DIV32 (5<<4) +#define CMU_LFAPRESC0_RTC_DIV64 (6<<4) +#define CMU_LFAPRESC0_RTC_DIV128 (7<<4) +#define CMU_LFAPRESC0_RTC_DIV256 (8<<4) +#define CMU_LFAPRESC0_RTC_DIV512 (9<<4) +#define CMU_LFAPRESC0_RTC_DIV1024 (10<<4) +#define CMU_LFAPRESC0_RTC_DIV2048 (11<<4) +#define CMU_LFAPRESC0_RTC_DIV4096 (12<<4) +#define CMU_LFAPRESC0_RTC_DIV8192 (13<<4) +#define CMU_LFAPRESC0_RTC_DIV16384 (14<<4) +#define CMU_LFAPRESC0_RTC_DIV32768 (15<<4) +#define CMU_LFAPRESC0_LESENSE_DIV1 (0<<0) +#define CMU_LFAPRESC0_LESENSE_DIV2 (1<<0) +#define CMU_LFAPRESC0_LESENSE_DIV4 (2<<0) +#define CMU_LFAPRESC0_LESENSE_DIV8 (3<<0) + +/** @} */ + +/** Bit states for the CMU_LFBPRESC0 register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.24 for definitions. + * + * @defgroup EFM32TG_CMU_LFBPRESC0_bits EFM32 Tiny Gecko CMU LFBPRESC0 bits + * @{ + */ + +#define CMU_LFBPRESC0_LEUART0_DIV1 (0<<0) +#define CMU_LFBPRESC0_LEUART0_DIV2 (1<<0) +#define CMU_LFBPRESC0_LEUART0_DIV4 (2<<0) +#define CMU_LFBPRESC0_LEUART0_DIV8 (3<<0) + +/** @} */ + +/** Bit states for the CMU_PCNTCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.25 for definitions. + * + * @defgroup EFM32TG_CMU_PCNTCTRL_bits EFM32 Tiny Gecko CMU PCNTCTRL bits + * @{ + */ + +#define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (0<<1) +#define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (1<<1) +#define CMU_PCNTCTRL_PCNT0CLKEN (1<<0) + +/** @} */ + +/** Bit states for the CMU_LCDCTRL register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.26 for definitions. + * + * @defgroup EFM32TG_CMU_LCDCTRL_bits EFM32 Tiny Gecko CMU LCDCTRL bits + * @{ + */ + +#define CMU_LCDCTRL_VBFDIV_DIV1 (0<<4) +#define CMU_LCDCTRL_VBFDIV_DIV2 (1<<4) +#define CMU_LCDCTRL_VBFDIV_DIV4 (2<<4) +#define CMU_LCDCTRL_VBFDIV_DIV8 (3<<4) +#define CMU_LCDCTRL_VBFDIV_DIV16 (4<<4) +#define CMU_LCDCTRL_VBFDIV_DIV32 (5<<4) +#define CMU_LCDCTRL_VBFDIV_DIV64 (6<<4) +#define CMU_LCDCTRL_VBFDIV_DIV128 (7<<4) +#define CMU_LCDCTRL_VBOOSTEN (1<<3) +/* No values defined for the field FDIV */ + +/** @} */ + +/** Bit states for the CMU_ROUTE register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.27 for definitions. + * + * @defgroup EFM32TG_CMU_ROUTE_bits EFM32 Tiny Gecko CMU ROUTE bits + * @{ + */ + +#define CMU_ROUTE_LOCATION_LOC0 (0<<4) +#define CMU_ROUTE_LOCATION_LOC1 (1<<4) +#define CMU_ROUTE_CLKOUT1PEN (1<<1) +#define CMU_ROUTE_CLKOUT0PEN (1<<0) + +/** @} */ + +/** Values for the CMU_LOCK register + * + * See d0034_efm32tg_reference_manual.pdf section 11.5.28 for definitions. + * + * @defgroup EFM32TG_CMU_LOCK_values EFM32 Tiny Gecko CMU LOCK values + * @{ + */ + +#define CMU_LOCK_IS_UNLOCKED 0 +#define CMU_LOCK_IS_LOCKED 1 +#define CMU_LOCK_SET_LOCKED 0 +#define CMU_LOCK_SET_UNLOCKED 0x580E + +/** @} */ + +/** @} */ + + +/** @} */ #endif diff --git a/include/libopencm3/efm32/tinygecko/cmu.yaml b/include/libopencm3/efm32/tinygecko/cmu.yaml new file mode 100644 index 00000000..52906f76 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/cmu.yaml @@ -0,0 +1,437 @@ +copyright: "2012 chrysn " +license: lgpl-3+ +shortdocname: EFM32TG_CMU +longdocname: EFM32 Tiny Gecko CMU +shortname: CMU +longname: Clock Management Unit +baseref: d0034_efm32tg_reference_manual.pdf section 11 +registers_baserefext: ".4" +registers: + - name: CTRL + offset: 0x000 + definition_baserefext: ".5.1" + fields: + - name: DBGCLK + shift: 28 + values: + - {name: AUXHFRCO, value: 0} + - {name: HFCLK, value: 1} + - name: CLKOUTSEL1 + shift: 23 + length: 3 + values: &CLKOUTSEL1_values + - {name: LFRCO, value: 0} + - {name: LFXO, value: 1} + - {name: HFCLK, value: 2} + - {name: LFXOQ, value: 3} + - {name: HFXOQ, value: 4} + - {name: LFRCOQ, value: 5} + - {name: HFRCOQ, value: 6} + - {name: AUXHFRCOQ, value: 7} + - name: CLKOUTSEL0 + shift: 20 + length: 3 + values: *CLKOUTSEL1_values + - name: LFXOTIMEOUT + shift: 18 + length: 2 + values: + - {name: 8CYCLES, value: 0} + - {name: 1KCYCLES, value: 1} + - {name: 16KCYCLES, value: 2} + - {name: 32KCYCLES, value: 3} + - name: LFXOBUFCUR + shift: 17 + - name: LXFOBOOST + shift: 13 + values: + - {name: 70PCENT, value: 0} + - {name: 100PCENT, value: 1} + - name: LFXOMODE + shift: 11 + length: 2 + values: + - {name: XTAL, value: 0} + - {name: BUFEXTCLK, value: 1} + - {name: DIGEXTCLK, value: 2} + - name: HFXOTIMEOUT + shift: 9 + length: 2 + values: + - {name: 8CYCLES, value: 0} + - {name: 256CYCLES, value: 1} + - {name: 1KCYCLES, value: 2} + - {name: 16KCYCLES, value: 3} + - name: HFXOGLITCHDETEN + shift: 7 + - name: HFXOBUFCUR + shift: 5 + length: 2 + type: undocumented + - name: HFXOBOOST + shift: 2 + length: 2 + values: + - {name: 50PCENT, value: 0} + - {name: 70PCENT, value: 1} + - {name: 80PCENT, value: 2} + - {name: 100PCENT, value: 3} + - name: HFXOMODE + shift: 0 + length: 2 + values: + - {name: XTAL, value: 0} + - {name: BUFEXTCLK, value: 1} + - {name: DIGEXTCLK, value: 2} + - name: HFCORECLKDIV + offset: 0x004 + definition_baserefext: ".5.2" + values: &HFCORECLKDIV_values + - {value: 0, name: HFCLK} + - {value: 1, name: HFCLK2} + - {value: 2, name: HFCLK4} + - {value: 3, name: HFCLK8} + - {value: 4, name: HFCLK16} + - {value: 5, name: HFCLK32} + - {value: 6, name: HFCLK64} + - {value: 7, name: HFCLK128} + - {value: 8, name: HFCLK256} + - {value: 9, name: HFCLK512} + - name: HFPERCLKDIV + offset: 0x008 + definition_baserefext: ".5.3" + fields: + - name: HFPERCLKEN + shift: 8 + - name: HFPERCLKDIV + shift: 0 + length: 3 + # not using generically named values here due to different register structure + values: *HFCORECLKDIV_values + - name: HFRCOCTRL + offset: 0x00c + definition_baserefext: ".5.4" + fields: + - name: SUDELAY + shift: 12 + length: 5 + type: undocumented + - name: BAND + shift: 8 + length: 3 + values: + - {value: 0, name: 1MHZ} + - {value: 1, name: 7MHZ} + - {value: 2, name: 11MHZ} + - {value: 3, name: 14MHZ} + - {value: 4, name: 21MHZ} + - {value: 5, name: 28MHZ} + - name: TUNING + shift: 0 + length: 8 + type: uint + - name: LFRCOCTRL + offset: 0x010 + definition_baserefext: ".5.5" + length: 7 + - name: AUXHFRCOCTRL + offset: 0x014 + definition_baserefext: ".5.6" + fields: + - name: BAND + shift: 8 + length: 3 + values: + - {value: 0, name: 14MHZ} + - {value: 1, name: 11MHZ} + - {value: 2, name: 7MHZ} + - {value: 3, name: 1MHZ} + - {value: 6, name: 28MHZ} + - {value: 7, name: 21MHZ} + - name: TUNING + shift: 0 + length: 8 + type: uint + - name: CALCTRL + offset: 0x018 + definition_baserefext: ".6.7" + fields: + - name: CONT + shift: 6 + - name: DOWNSEL + shift: 3 + length: 3 + values: + - {value: 0, name: HFCLK} + - {value: 1, name: HFXO} + - {value: 2, name: LFXO} + - {value: 3, name: HFRCO} + - {value: 4, name: LFRCO} + - {value: 5, name: AUXHFRCO} + - name: UPSEL + shift: 0 + length: 3 + values: + - {value: 0, name: HFXO} + - {value: 1, name: LFXO} + - {value: 2, name: HFRCO} + - {value: 3, name: LFRCO} + - {value: 4, name: AUXHFRCO} + - name: CALCNT + offset: 0x01c + definition_baserefext: ".5.8" + length: 19 + - name: OSCENCMD + offset: 0x020 + definition_baserefext: ".5.9" + fields: + - {name: LFXODIS, shift: 9} + - {name: LFXOEN, shift: 8} + - {name: LFRCODIS, shift: 7} + - {name: LFRCOEN, shift: 6} + - {name: AUXHFRCODIS, shift: 5} + - {name: AUXHFRCOEN, shift: 4} + - {name: HFXODIS, shift: 3} + - {name: HFXOEN, shift: 2} + - {name: HFRCODIS, shift: 1} + - {name: HFRCOEN, shift: 0} + - name: CMD + offset: 0x024 + definition_baserefext: ".5.10" + fields: + - name: CALSTOP + shift: 4 + - name: CALSTART + shift: 3 + - name: HFCLKSEL + shift: 0 + length: 3 + values: + - {value: 1, name: HFRCO} + - {value: 2, name: HFXO} + - {value: 3, name: LFRCO} + - {value: 4, name: LFXO} + - name: LFCLKSEL + offset: 0x028 + definition_baserefext: ".5.11" + fields: + - name: LFBE + shift: 20 + values: &LFCLKSEL_LFBE + - {value: 0, name: DISABLED} + - {value: 1, name: ULFRCO} + - name: LFAE + shift: 16 + values: *LFCLKSEL_LFBE + - name: LFB + shift: 2 + length: 2 + values: &LFCLKSEL_LFB + - {value: 0, name: DISABLED} + - {value: 1, name: LFRCO} + - {value: 2, name: LFXO} + - {value: 3, name: HFCORECLKLEDIV2} + - name: LFA + shift: 0 + length: 2 + values: *LFCLKSEL_LFB + - name: STATUS + offset: 0x02c + definition_baserefext: ".5.12" + fields: + - {name: CALBSY, shift: 14} + - {name: LFXOSEL, shift: 13} + - {name: LFRCOSEL, shift: 12} + - {name: HFXOSEL, shift: 11} + - {name: HFRCOSEL, shift: 10} + - {name: LFXORDY, shift: 9} + - {name: LFXOENS, shift: 8} + - {name: LFRCORDY, shift: 7} + - {name: LFRCOENS, shift: 6} + - {name: AUXHFRCORDY, shift: 5} + - {name: AUXHFRCOENS, shift: 4} + - {name: HFXORDY, shift: 3} + - {name: HFXOENS, shift: 2} + - {name: HFRCORDY, shift: 1} + - {name: HFRCOENS, shift: 0} + - name: IF + offset: 0x030 + definition_baserefext: ".5.13" + #fields: I + - name: IFS + offset: 0x034 + definition_baserefext: ".5.14" + #fields: I + - name: IFC + offset: 0x038 + definition_baserefext: ".5.15" + #fields: I + - name: IEN + offset: 0x03c + definition_baserefext: ".5.16" + #fields: I + - name: HFCORECLKEN0 + offset: 0x040 + definition_baserefext: ".5.17" + fields: + - {name: LE, shift: 2} + - {name: DMA, shift: 1} + - {name: AES, shift: 0} + - name: HFPERCLKEN0 + offset: 0x044 + definition_baserefext: ".5.18" + fields: + - {name: I2C0, shift: 11} + - {name: DAC0, shift: 10} + - {name: ADC0, shift: 9} + - {name: PRS, shift: 8} + - {name: VCMP, shift: 7} + - {name: GPIO, shift: 6} + - {name: TIMER1, shift: 5} + - {name: TIMER0, shift: 4} + - {name: USART1, shift: 3} + - {name: USART0, shift: 2} + - {name: ACMP1, shift: 1} + - {name: ACMP0, shift: 0} + - name: SYNCBUSY + offset: 0x050 + definition_baserefext: ".5.19" + fields: + - {name: LFBPRESC0, shift: 6} + - {name: LFBCLKEN0, shift: 4} + - {name: LFAPRESC0, shift: 2} + - {name: LFACLKEN0, shift: 0} + - name: FREEZE + offset: 0x054 + definition_baserefext: ".5.20" + fields: + - name: REGFREEZE + shift: 0 + values: + - {value: 0, name: UPDATE} + - {value: 1, name: FREEZE} + - name: LFACLKEN0 + offset: 0x058 + definition_baserefext: ".5.21" + fields: + - {name: LCD, shift: 3} + - {name: LETIMER0, shift: 2} + - {name: RTC, shift: 1} + - {name: LESENSE, shift: 0} + - name: LFBCLKEN0 + offset: 0x060 + definition_baserefext: ".5.22" + fields: + - {name: LEUART0, shift: 0} + - name: LFAPRESC0 + offset: 0x068 + definition_baserefext: ".5.23" + fields: + - name: LCD + shift: 12 + length: 2 + values: + - {value: 0, name: DIV16} + - {value: 1, name: DIV32} + - {value: 2, name: DIV64} + - {value: 3, name: DIV128} + - name: LETIMER0 + shift: 8 + length: 4 + values: &LFAPRESC0_LETIMER0_values + - {value: 0, name: DIV1} + - {value: 1, name: DIV2} + - {value: 2, name: DIV4} + - {value: 3, name: DIV8} + - {value: 4, name: DIV16} + - {value: 5, name: DIV32} + - {value: 6, name: DIV64} + - {value: 7, name: DIV128} + - {value: 8, name: DIV256} + - {value: 9, name: DIV512} + - {value: 10, name: DIV1024} + - {value: 11, name: DIV2048} + - {value: 12, name: DIV4096} + - {value: 13, name: DIV8192} + - {value: 14, name: DIV16384} + - {value: 15, name: DIV32768} + - name: RTC + shift: 4 + length: 4 + values: *LFAPRESC0_LETIMER0_values + - name: LESENSE + shift: 0 + length: 2 + values: + - {value: 0, name: DIV1} + - {value: 1, name: DIV2} + - {value: 2, name: DIV4} + - {value: 3, name: DIV8} + - name: LFBPRESC0 + offset: 0x070 + definition_baserefext: ".5.24" + fields: + - name: LEUART0 + shift: 0 + length: 2 + values: + - {value: 0, name: DIV1} + - {value: 1, name: DIV2} + - {value: 2, name: DIV4} + - {value: 3, name: DIV8} + - name: PCNTCTRL + offset: 0x078 + definition_baserefext: ".5.25" + fields: + - name: PCNT0CLKSEL + shift: 1 + values: + - {value: 0, name: LFACLK} + - {value: 1, name: PCNT0S0} + - name: PCNT0CLKEN + shift: 0 + - name: LCDCTRL + offset: 0x07c + definition_baserefext: ".5.26" + fields: + - name: VBFDIV + shift: 4 + length: 3 + values: + - {value: 0, name: DIV1} + - {value: 1, name: DIV2} + - {value: 2, name: DIV4} + - {value: 3, name: DIV8} + - {value: 4, name: DIV16} + - {value: 5, name: DIV32} + - {value: 6, name: DIV64} + - {value: 7, name: DIV128} + - name: VBOOSTEN + shift: 3 + - name: FDIV + shift: 0 + length: 3 + type: uint + - name: ROUTE + offset: 0x080 + definition_baserefext: ".5.27" + fields: + - name: LOCATION + shift: 4 + length: 3 + values: + - {value: 0, name: LOC0} + - {value: 1, name: LOC1} + - name: CLKOUT1PEN + shift: 1 + - name: CLKOUT0PEN + shift: 0 + - name: LOCK + offset: 0x084 + definition_baserefext: ".5.28" + length: 16 + values: + - {name: IS_UNLOCKED, value: 0} + - {name: IS_LOCKED, value: 1} + - {name: SET_LOCKED, value: 0} + - {name: SET_UNLOCKED, value: "0x580E"} diff --git a/include/libopencm3/efm32/tinygecko/emu.convenienceheaders b/include/libopencm3/efm32/tinygecko/emu.convenienceheaders new file mode 100644 index 00000000..4be5b30e --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/emu.convenienceheaders @@ -0,0 +1,18 @@ +/** EMU convenience functions + * + * These functions can be used to send the chip to low energy modes. + * + * @todo Implement other sleep modes than EM1. Implement WFI vs WFE waits. + * + * @defgroup EFM32TG_EMU_convenience EFM32 Tiny Gecko EMU convenience functions + * @{ + */ + +/** Put the system into EM1 low energy mode. */ +static void emu_sleep_em1(void) +{ + /* FIXME: set SLEEPDEEP to 0 */ + __asm__("wfi"); +} + +/** @} */ diff --git a/include/libopencm3/efm32/tinygecko/emu.h b/include/libopencm3/efm32/tinygecko/emu.h index 307d1d60..0a97679e 100644 --- a/include/libopencm3/efm32/tinygecko/emu.h +++ b/include/libopencm3/efm32/tinygecko/emu.h @@ -48,9 +48,9 @@ * @{ */ -#define EMU_CTRL MMIO32(EMU_BASE + 0x000) /**< @see EFM32TG_EMU_CTRL_bits */ -#define EMU_LOCK MMIO32(EMU_BASE + 0x008) /**< @see EFM32TG_EMU_LOCK_values */ -#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) /**< @see EFM32TG_EMU_AUXCTRL_bits */ +#define EMU_CTRL MMIO32(EMU_BASE + 0x000) /**< @see EFM32TG_EMU_CTRL_bits */ +#define EMU_LOCK MMIO32(EMU_BASE + 0x008) /**< @see EFM32TG_EMU_LOCK_values */ +#define EMU_AUXCTRL MMIO32(EMU_BASE + 0x024) /**< @see EFM32TG_EMU_AUXCTRL_bits */ /** @} */ @@ -63,39 +63,39 @@ * @{ */ -#define EMU_CTRL_EM4CTRL_TWO (2<<2) -#define EMU_CTRL_EM4CTRL_THREE (3<<2) -#define EMU_CTRL_EM2BLOCK (1<<1) /**< When this bit is set, no mode lower than EM1 will be entered */ -#define EMU_CTRL_EMVREG (1<<0) /**< When this bit is set, the voltage regulator will stay on in modes lower than EM1 */ +#define EMU_CTRL_EM4CTRL_TWO (2<<2) +#define EMU_CTRL_EM4CTRL_THREE (3<<2) +#define EMU_CTRL_EM2BLOCK (1<<1) /**< When this bit is set, no mode lower than EM1 will be entered */ +#define EMU_CTRL_EMVREG (1<<0) /**< When this bit is set, the voltage regulator will stay on in modes lower than EM1 */ /** @} */ /** Values for the EMU_LOCK register * - * See d0034_efm32tg_reference_manual.pdf section 10.5.2. There seems not to be - * another mention of it. + * See d0034_efm32tg_reference_manual.pdf section 10.5.2 for definitions. There + * seems not to be another mention of it. * * @defgroup EFM32TG_EMU_LOCK_values EFM32 Tiny Gecko EMU LOCK values * @{ */ -#define EMU_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */ -#define EMU_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */ -#define EMU_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock the EMU */ -#define EMU_LOCK_SET_UNLOCKED 0xade8 /**< Write this to the LOCK register to unlock the EMU */ +#define EMU_LOCK_IS_UNLOCKED 0 /**< When the LOCK register reads as this value, it is open */ +#define EMU_LOCK_IS_LOCKED 1 /**< When the LOCK register reads as this value, it is locked */ +#define EMU_LOCK_SET_LOCKED 0 /**< Write this to the LOCK register to lock the EMU */ +#define EMU_LOCK_SET_UNLOCKED 0xade8 /**< Write this to the LOCK register to unlock the EMU */ /** @} */ /** Bit states for the EMU_AUXCTRL register * - * See d0034_efm32tg_reference_manual.pdf section 10.5.3 for definition, and + * See d0034_efm32tg_reference_manual.pdf section 10.5.3 for definitions, and * 9.5.3 for details. * * @defgroup EFM32TG_EMU_AUXCTRL_bits EFM32 Tiny Gecko EMU AUXCTRL bits * @{ */ -#define EMU_AUXCTRL_HRCCLR (1<<0) +#define EMU_AUXCTRL_HRCCLR (1<<0) /** @} */ diff --git a/include/libopencm3/efm32/tinygecko/emu.yaml b/include/libopencm3/efm32/tinygecko/emu.yaml new file mode 100644 index 00000000..376c76ca --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/emu.yaml @@ -0,0 +1,50 @@ +copyright: "2012 chrysn " +license: lgpl-3+ +shortdocname: EFM32TG_EMU +longdocname: EFM32 Tiny Gecko EMU +shortname: EMU +longname: Energy Management Unit +baseref: d0034_efm32tg_reference_manual.pdf section 10 +registers_baserefext: ".4" +registers: + - name: CTRL + definition_baserefext: .5.1 + details: ", and 10.3.2 for details (especially on why EM4CTRL_TWO and _THREE are defined)." + offset: 0x000 + fields: + - name: EM4CTRL + shift: 2 + length: 2 + values: + - {name: TWO, value: 2} + - {name: THREE, value: 3} + - name: EM2BLOCK + shift: 1 + doc: When this bit is set, no mode lower than EM1 will be entered + - name: EMVREG + shift: 0 + doc: When this bit is set, the voltage regulator will stay on in modes lower than EM1 + - name: LOCK + definition_baserefext: .5.2 + details: ". There seems not to be another mention of it." + offset: 0x008 + values: + - name: IS_UNLOCKED + value: 0 + doc: When the LOCK register reads as this value, it is open + - name: IS_LOCKED + value: 1 + doc: When the LOCK register reads as this value, it is locked + - name: SET_LOCKED + value: 0 + doc: Write this to the LOCK register to lock the EMU + - name: SET_UNLOCKED + value: "0xade8" + doc: Write this to the LOCK register to unlock the EMU + - name: AUXCTRL + definition_baserefext: .5.3 + details: ", and 9.5.3 for details." + offset: 0x024 + fields: + - name: HRCCLR + shift: 0 diff --git a/include/libopencm3/efm32/tinygecko/generate-license.yaml b/include/libopencm3/efm32/tinygecko/generate-license.yaml new file mode 100644 index 00000000..baeef880 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/generate-license.yaml @@ -0,0 +1,19 @@ +"lgpl-3+": | + /* + * This file is part of the {projectname} project. + * + * Copyright (C) {copyright} + * + * This library is free software: you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public License + * along with this library. If not, see . + */ diff --git a/include/libopencm3/efm32/tinygecko/generate.py b/include/libopencm3/efm32/tinygecko/generate.py new file mode 100644 index 00000000..8bd81843 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/generate.py @@ -0,0 +1,112 @@ +#!/usr/bin/env python + +import yaml +import logging +import textwrap + +def commentblock(*textblocks, **formatargs): + ret = [] + ret.extend(textwrap.wrap(textblocks[0].format(**formatargs), 80, initial_indent="/** ", subsequent_indent=" * ")) + last_block_was_at = textblocks[0].startswith('@') + for b in textblocks[1:]: + if not (last_block_was_at and b.startswith('@')): + ret.append(" *") + # FIXME: some blocks don't like being wrapped, eg @defgroup + ret.extend(textwrap.wrap(b.format(**formatargs), 80, initial_indent=" * ", subsequent_indent=" * ")) + last_block_was_at = b.startswith('@') + return "\n".join(ret) + "\n */\n" + +def yaml2h(filenamebase): + headername = "%s.h"%filenamebase + yamlname = "%s.yaml"%filenamebase + conveniencename = "%s.convenienceheaders"%filenamebase + + logging.info("Generating %s from %s", headername, yamlname) + + data = yaml.load(open(yamlname)) + # some defaults + data.setdefault("projectname", "libopencm3") + data.setdefault("includeguard", "LIBOPENCM3_EFM32_TINYGECKO_%s_H"%data['shortname']) + + with open(headername, 'w') as outfile: + def wc(*args, **kwargs): # wrap "outfile" and "data" (as default) arguments -- i'm a lazy typer + final_kwargs = data.copy() + final_kwargs.update(kwargs) + outfile.write(commentblock(*args, **final_kwargs)) + def wc_close(): + outfile.write("/** @} */\n") + def nl(): outfile.write("\n") + def define(key, value, comment=None): + outfile.write("#define ") + outfile.write(key) + outfile.write(" "*max(24-len(key), 1)) + outfile.write(str(value)) + if comment is not None: + outfile.write(" /**< %s */"%comment) + nl() + + outfile.write(licensedata[data['license']].format(**data)) + nl() + wc("@file", "@see {shortdocname}") + nl() + wc("Definitions for the {shortname} subsystem ({longname}).", "This corresponds to the description in {baseref}.", "@defgroup {shortdocname} {longdocname}", "@{{") + nl() + outfile.write("#ifndef {includeguard}\n#define {includeguard}\n".format(**data)) + nl() + outfile.write("#include \n#include \n") + nl() + wc("Register definitions and register value definitions for the {shortname} subsystem", "@defgroup {shortdocname}_regsandvals {longdocname} registers and values", "@{{") + nl() + + regs = data['registers'] + wc("These definitions reflect {baseref}{registers_baserefext}", "@defgroup {shortdocname}_registers {longdocname} registers", "@{{") + nl() + for regdata in regs: + define("%s_%s"%(data['shortname'], regdata['name']), "MMIO32(%s_BASE + %#.003x)"%(data['shortname'], regdata['offset']), "@see %s_%s_%s"%(data['shortdocname'], regdata['name'], 'values' if 'values' in regdata else 'bits')) + nl() + wc_close() # close register definitions + nl() + for regdata in regs: + has_bits = "fields" in regdata + has_values = "values" in regdata + if not has_bits and not has_values: + continue + + wc("%s for the {shortname}_{name} register"%("Bit states" if has_bits else "Values"), "See {baseref}{definition_baserefext} for definitions"+regdata.get("details", "."), '@defgroup {shortdocname}_{name}_%s {longdocname} {name} %s'%(('bits' if has_bits else 'values',)*2), '@{{', **regdata) + nl() + + if has_bits: + for field in regdata['fields']: + #shiftdefine = "_%s_%s_%s_shift"%(shortname, regdata['name'], field['name']) + #define(shiftdefine, field['shift']) + if "values" in field: + for value in field.get("values"): + define("%s_%s_%s_%s"%(data['shortname'], regdata['name'], field['name'], value['name']), "(%s<<%s)"%(value['value'], field['shift']), value.get('doc', None)) + else: + if field.get('length', 1) == 1: + define("%s_%s_%s"%(data['shortname'], regdata['name'], field['name']), "(1<<%s)"%field['shift'], field.get('doc', None)) + else: + # FIXME: this should require the 'type' parameter to be set on this field + outfile.write("/* No values defined for the field %s */\n"%field['name']) + # FIXME: define mask + else: + for value in regdata['values']: + define("%s_%s_%s"%(data['shortname'], regdata['name'], value['name']), value['value'], value.get('doc', None)) + + nl() + wc_close() + nl() + wc_close() # close registers and values + nl() + + outfile.write(open(conveniencename).read()) + + nl() + wc_close() # close convenience + nl() + outfile.write("#endif\n") + +if __name__ == "__main__": + licensedata = yaml.load(open("generate-license.yaml")) + for basename in yaml.load(open('generate.yaml')): + yaml2h(basename) diff --git a/include/libopencm3/efm32/tinygecko/generate.yaml b/include/libopencm3/efm32/tinygecko/generate.yaml new file mode 100644 index 00000000..878d0ad8 --- /dev/null +++ b/include/libopencm3/efm32/tinygecko/generate.yaml @@ -0,0 +1,2 @@ +- emu +- cmu