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stm32g4/g0: adc: fix clock prescalers

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CCR register definitions were completely wrong, both decimal/hex mixups,
and straightup transcriptions from the reference manual errors.

Unify the styles for both g0 and g4, using the same (duplicated)
function for both implmentations.

Reviewed-by: Karl Palsson <karlp@tweak.au>
This commit is contained in:
neoxic
2023-02-01 21:40:56 +00:00
committed by Karl Palsson
parent 88f4d111ba
commit d262e70fc3
3 changed files with 27 additions and 24 deletions
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11
lib/stm32/g4/adc.c
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@@ -540,13 +540,14 @@ void adc_set_clk_source(uint32_t adc, uint32_t source)
* The ADC clock taken from the APB2 clock can be scaled down by 2, 4, 6 or 8.
*
* @param adc peripheral of choice @ref adc_reg_base
* @param[in] prescale Unsigned int32. Prescale value for ADC Clock @ref
* adc_ccr_adcpre
* @param[in] prescale Prescale value for ADC Clock @ref adc_ccr_presc
*/
void adc_set_clk_prescale(uint32_t adc, uint32_t ckmode)
void adc_set_clk_prescale(uint32_t adc, uint32_t prescale)
{
uint32_t reg32 = ((ADC_CCR(adc) & ~ADC_CCR_CKMODE_MASK) | ckmode);
ADC_CCR(adc) = reg32;
uint32_t reg32 = ADC_CCR(adc);
reg32 &= ~(ADC_CCR_PRESC_MASK << ADC_CCR_PRESC_SHIFT);
ADC_CCR(adc) = (reg32 | (prescale << ADC_CCR_PRESC_SHIFT));
}
/*---------------------------------------------------------------------------*/