Split sam3x/sam3n support.
This commit is contained in:
Gareth McMullin
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
4535a4c9b6
commit
ce3e3dc39b
36
include/libopencm3/sam/3n/irq.yaml
Normal file
36
include/libopencm3/sam/3n/irq.yaml
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@@ -0,0 +1,36 @@
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includeguard: LIBOPENCM3_SAM3N_NVIC_H
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partname_humanreadable: Atmel SAM3N series
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partname_doxygen: SAM3N
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irqs:
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- supc
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- rstc
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- rtc
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- rtt
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- wdg
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- pmc
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- eefc0
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- reserved0
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- uart0
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- uart1
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- reserved1
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- pioa
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- piob
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- pioc
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- usart0
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- usart1
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- reserved2
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- reserved3
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- reserved4
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- twi0
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- twi1
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- spi
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- reserved5
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- tc0
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- tc1
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- tc2
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- tc3
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- tc4
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- tc5
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- adc
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- dacc
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- pwm
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60
include/libopencm3/sam/3n/memorymap.h
Normal file
60
include/libopencm3/sam/3n/memorymap.h
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@@ -0,0 +1,60 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SAM3N_MEMORYMAP_H
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#define SAM3N_MEMORYMAP_H
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#include <libopencm3/cm3/common.h>
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/* --- SAM3N peripheral space -------------------------------------------- */
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#define SPI_BASE (0x40008000)
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#define TC0_BASE (0x40010000)
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#define TC1_BASE (0x40010040)
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#define TC2_BASE (0x40010080)
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#define TC3_BASE (0x40014000)
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#define TC4_BASE (0x40014040)
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#define TC5_BASE (0x40014080)
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#define TWI0_BASE (0x40018000)
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#define TWI1_BASE (0x4001C000)
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#define PWM_BASE (0x40020000)
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#define USART0_BASE (0x40024000)
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#define USART1_BASE (0x40028000)
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#define ADC_BASE (0x40038000)
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#define DACC_BASE (0x4003C000)
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/* --- SAM3N system controller space ------------------------------------- */
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#define SMC_BASE (0x400E0000)
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#define MATRIX_BASE (0x400E0200)
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#define PMC_BASE (0x400E0400)
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#define UART0_BASE (0x400E0600)
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#define CHIPID_BASE (0x400E0740)
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#define UART1_BASE (0x400E0800)
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#define EEFC_BASE (0x400E0A00)
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#define PIOA_BASE (0x400E0E00)
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#define PIOB_BASE (0x400E1000)
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#define PIOC_BASE (0x400E1200)
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#define RSTC_BASE (0x400E1400)
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#define SUPC_BASE (0x400E1410)
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#define RTT_BASE (0x400E1430)
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#define WDT_BASE (0x400E1450)
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#define RTC_BASE (0x400E1460)
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#define GPBR_BASE (0x400E1490)
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#endif
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49
include/libopencm3/sam/3x/irq.yaml
Normal file
49
include/libopencm3/sam/3x/irq.yaml
Normal file
@@ -0,0 +1,49 @@
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includeguard: LIBOPENCM3_SAM3X_NVIC_H
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partname_humanreadable: Atmel SAM3X series
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partname_doxygen: SAM3X
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irqs:
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- supc
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- rstc
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- rtc
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- rtt
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- wdg
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- pmc
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- eefc0
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- eefc1
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- uart
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- smc_sdramc
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- sdramc
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- pioa
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- piob
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- pioc
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- piod
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- pioe
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- piof
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- usart0
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- usart1
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- usart2
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- usart3
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- hsmci
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- twi0
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- twi1
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- spi0
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- spi1
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- ssc
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- tc0
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- tc1
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- tc2
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- tc3
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- tc4
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- tc5
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- tc6
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- tc7
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- tc8
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- pwm
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- adc
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- dacc
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- dmac
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- uotghs
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- trng
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- emac
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- can0
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- can1
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78
include/libopencm3/sam/3x/memorymap.h
Normal file
78
include/libopencm3/sam/3x/memorymap.h
Normal file
@@ -0,0 +1,78 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
|
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SAM3X_MEMORYMAP_H
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#define SAM3X_MEMORYMAP_H
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#include <libopencm3/cm3/common.h>
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/* --- SAM3X peripheral space -------------------------------------------- */
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#define HSMCI_BASE (0x40000000)
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#define SSC_BASE (0x40004000)
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#define SPI0_BASE (0x40008000)
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#define SPI1_BASE (0x4000C000)
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#define TC0_BASE (0x40080000)
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#define TC1_BASE (0x40080040)
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#define TC2_BASE (0x40080080)
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#define TC3_BASE (0x40084000)
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#define TC4_BASE (0x40084040)
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#define TC5_BASE (0x40084080)
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#define TC6_BASE (0x40088000)
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#define TC7_BASE (0x40088040)
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#define TC8_BASE (0x40088080)
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#define TWI0_BASE (0x4008C000)
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#define TWI1_BASE (0x40090000)
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#define PWM_BASE (0x40094000)
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#define USART0_BASE (0x40098000)
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#define USART1_BASE (0x4009C000)
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#define USART2_BASE (0x400A0000)
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#define USART3_BASE (0x400A4000)
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#define UOTGHS_BASE (0x400AC000)
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#define EMAC_BASE (0x400B0000)
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#define CAN0_BASE (0x400B4000)
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#define CAN1_BASE (0x400B8000)
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#define TRNG_BASE (0x400BC000)
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#define ADC_BASE (0x400C0000)
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#define DMAC_BASE (0x400C4000)
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/* --- SAM3X system controller space ------------------------------------- */
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#define SMC_BASE (0x400E0000)
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#define SDRAM_BASE (0x400E0200)
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#define MATRIX_BASE (0x400E0400)
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#define PMC_BASE (0x400E0600)
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#define UART_BASE (0x400E0800)
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#define CHIPID_BASE (0x400E0940)
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#define EEFC0_BASE (0x400E0A00)
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#define EEFC1_BASE (0x400E0C00)
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#define PIOA_BASE (0x400E0E00)
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#define PIOB_BASE (0x400E1000)
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#define PIOC_BASE (0x400E1200)
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#define PIOD_BASE (0x400E1400)
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#define PIOE_BASE (0x400E1600)
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#define PIOF_BASE (0x400E1800)
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#define RSTC_BASE (0x400E1A00)
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#define SUPC_BASE (0x400E1A10)
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#define RTT_BASE (0x400E1A30)
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#define WDT_BASE (0x400E1A50)
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#define RTC_BASE (0x400E1A60)
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#define GPBR_BASE (0x400E1A90)
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#define RTC_BASE (0x400E1A60)
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#endif
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83
include/libopencm3/sam/eefc.h
Normal file
83
include/libopencm3/sam/eefc.h
Normal file
@@ -0,0 +1,83 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
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*
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* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
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* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef SAM3X_EEFC_H
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#define SAM3X_EEFC_H
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#include <libopencm3/cm3/common.h>
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#include <libopencm3/sam/memorymap.h>
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/* --- Convenience macros ------------------------------------------------ */
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#define EEFC EEFC_BASE
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#define EEFC0 EEFC0_BASE
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#define EEFC1 EEFC1_BASE
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/* --- Enhanced Embedded Flash Controller (EEFC) registers --------------- */
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#define EEFC_FMR(port) MMIO32((port) + 0x00)
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#define EEFC_FCR(port) MMIO32((port) + 0x04)
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#define EEFC_FSR(port) MMIO32((port) + 0x08)
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#define EEFC_FRR(port) MMIO32((port) + 0x0C)
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/* 0x0010 - Reserved */
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/* EEFC Flash Mode Register (EEFC_FMR) */
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/* Bit [31:25] - Reserved */
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#define EEFC_FMR_FAM (0x01 << 24)
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/* Bit [23:12] - Reserved */
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#define EEFC_FMR_FWS_MASK (0x0F << 8)
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/* Bit [7:1] - Reserved */
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#define EEFC_FMR_FRDY (0x01 << 0)
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/* EEFC Flash Command Register (EEFC_FCR) */
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#define EEFC_FCR_FKEY (0x5A << 24)
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#define EEFC_FCR_FARG_MASK (0xFFFF << 8)
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#define EEFC_FCR_FCMD_MASK (0xFF << 0)
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#define EEFC_FCR_FCMD_GETD (0x00 << 0)
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#define EEFC_FCR_FCMD_WP (0x01 << 0)
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#define EEFC_FCR_FCMD_WPL (0x02 << 0)
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#define EEFC_FCR_FCMD_EWP (0x03 << 0)
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#define EEFC_FCR_FCMD_EWPL (0x04 << 0)
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#define EEFC_FCR_FCMD_EA (0x05 << 0)
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#define EEFC_FCR_FCMD_SLB (0x08 << 0)
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#define EEFC_FCR_FCMD_CLB (0x09 << 0)
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#define EEFC_FCR_FCMD_GLB (0x0A << 0)
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#define EEFC_FCR_FCMD_SGPB (0x0B << 0)
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#define EEFC_FCR_FCMD_CGPB (0x0C << 0)
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#define EEFC_FCR_FCMD_GGPB (0x0D << 0)
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#define EEFC_FCR_FCMD_STUI (0x0E << 0)
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#define EEFC_FCR_FCMD_SPUI (0x0F << 0)
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/* EEFC Flash Status Register (EEFC_FSR) */
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/* Bit [31:3] - Reserved */
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#define EEFC_FSR_FLOCKE (0x01 << 2)
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#define EEFC_FSR_FCMDE (0x01 << 1)
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#define EEFC_FSR_FRDY (0x01 << 0)
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static inline void eefc_set_latency(u8 wait)
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{
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#if defined(SAM3X)
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EEFC_FMR(EEFC0) = (EEFC_FMR(EEFC0) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
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EEFC_FMR(EEFC1) = (EEFC_FMR(EEFC1) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
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#elif defined(SAM3N)
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EEFC_FMR(EEFC) = (EEFC_FMR(EEFC) & ~EEFC_FMR_FWS_MASK) | (wait << 8);
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#endif
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}
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#endif
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51
include/libopencm3/sam/gpio.h
Normal file
51
include/libopencm3/sam/gpio.h
Normal file
@@ -0,0 +1,51 @@
|
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/*
|
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* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
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#ifndef SAM3X_GPIO_H
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#define SAM3X_GPIO_H
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#include <libopencm3/sam/pio.h>
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/* flags may be or'd together, but only contain one of
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* GPOUTPUT, PERIPHA and PERIPHB */
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enum gpio_flags {
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GPIO_FLAG_GPINPUT = 0,
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GPIO_FLAG_GPOUTPUT = 1,
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GPIO_FLAG_PERIPHA = 2,
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GPIO_FLAG_PERIPHB = 3,
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GPIO_FLAG_OPEN_DRAIN = 4,
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GPIO_FLAG_PULL_UP = 8,
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};
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void gpio_init(u32 gpioport, u32 pins, enum gpio_flags flags);
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|
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static inline void gpio_set(u32 gpioport, u32 gpios)
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{
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PIO_SODR(gpioport) = gpios;
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}
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static inline void gpio_clear(u32 gpioport, u32 gpios)
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{
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PIO_CODR(gpioport) = gpios;
|
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}
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|
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void gpio_toggle(u32 gpioport, u32 gpios);
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|
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#endif
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32
include/libopencm3/sam/memorymap.h
Normal file
32
include/libopencm3/sam/memorymap.h
Normal file
@@ -0,0 +1,32 @@
|
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/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef SAM_MEMORYMAP_H
|
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#define SAM_MEMORYMAP_H
|
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|
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#if defined(SAM3X)
|
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# include <libopencm3/sam/3x/memorymap.h>
|
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#elif defined(SAM3N)
|
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# include <libopencm3/sam/3n/memorymap.h>
|
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#else
|
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# error "Processor family not defined."
|
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#endif
|
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|
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#endif
|
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|
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96
include/libopencm3/sam/pio.h
Normal file
96
include/libopencm3/sam/pio.h
Normal file
@@ -0,0 +1,96 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef SAM_PIO_H
|
||||
#define SAM_PIO_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/sam/memorymap.h>
|
||||
|
||||
/* --- Convenience macros ------------------------------------------------ */
|
||||
|
||||
/* GPIO port base addresses (for convenience) */
|
||||
#define PIOA PIOA_BASE
|
||||
#define PIOB PIOB_BASE
|
||||
#define PIOC PIOC_BASE
|
||||
#define PIOD PIOD_BASE
|
||||
#define PIOE PIOE_BASE
|
||||
#define PIOF PIOF_BASE
|
||||
#define PIOG PIOG_BASE
|
||||
#define PIOH PIOH_BASE
|
||||
|
||||
/* --- PIO registers ----------------------------------------------------- */
|
||||
|
||||
#define PIO_PER(port) MMIO32((port) + 0x0000)
|
||||
#define PIO_PDR(port) MMIO32((port) + 0x0004)
|
||||
#define PIO_PSR(port) MMIO32((port) + 0x0008)
|
||||
/* 0x000C - Reserved */
|
||||
#define PIO_OER(port) MMIO32((port) + 0x0010)
|
||||
#define PIO_ODR(port) MMIO32((port) + 0x0014)
|
||||
#define PIO_OSR(port) MMIO32((port) + 0x0018)
|
||||
/* 0x001C - Reserved */
|
||||
#define PIO_IFER(port) MMIO32((port) + 0x0020)
|
||||
#define PIO_IFDR(port) MMIO32((port) + 0x0024)
|
||||
#define PIO_IFSR(port) MMIO32((port) + 0x0028)
|
||||
/* 0x002C - Reserved */
|
||||
#define PIO_SODR(port) MMIO32((port) + 0x0030)
|
||||
#define PIO_CODR(port) MMIO32((port) + 0x0034)
|
||||
#define PIO_ODSR(port) MMIO32((port) + 0x0038)
|
||||
#define PIO_PDSR(port) MMIO32((port) + 0x003C)
|
||||
#define PIO_IER(port) MMIO32((port) + 0x0040)
|
||||
#define PIO_IDR(port) MMIO32((port) + 0x0044)
|
||||
#define PIO_IMR(port) MMIO32((port) + 0x0048)
|
||||
#define PIO_ISR(port) MMIO32((port) + 0x004C)
|
||||
#define PIO_MDER(port) MMIO32((port) + 0x0050)
|
||||
#define PIO_MDDR(port) MMIO32((port) + 0x0054)
|
||||
#define PIO_MDSR(port) MMIO32((port) + 0x0058)
|
||||
/* 0x005C - Reserved */
|
||||
#define PIO_PUDR(port) MMIO32((port) + 0x0060)
|
||||
#define PIO_PUER(port) MMIO32((port) + 0x0064)
|
||||
#define PIO_PUSR(port) MMIO32((port) + 0x0068)
|
||||
/* 0x006C - Reserved */
|
||||
#define PIO_ABSR(port) MMIO32((port) + 0x0070)
|
||||
/* 0x0074-0x007C - Reserved */
|
||||
#define PIO_SCIFSR(port) MMIO32((port) + 0x0080)
|
||||
#define PIO_DIFSR(port) MMIO32((port) + 0x0084)
|
||||
#define PIO_IFDGSR(port) MMIO32((port) + 0x0088)
|
||||
#define PIO_SCDR(port) MMIO32((port) + 0x008C)
|
||||
/* 0x0090-0x009C - Reserved */
|
||||
#define PIO_OWER(port) MMIO32((port) + 0x00A0)
|
||||
#define PIO_OWDR(port) MMIO32((port) + 0x00A4)
|
||||
#define PIO_OWSR(port) MMIO32((port) + 0x00A8)
|
||||
/* 0x00AC - Reserved */
|
||||
#define PIO_AIMER(port) MMIO32((port) + 0x00B0)
|
||||
#define PIO_AIMDR(port) MMIO32((port) + 0x00B4)
|
||||
#define PIO_AIMMR(port) MMIO32((port) + 0x00B8)
|
||||
/* 0x00BC - Reserved */
|
||||
#define PIO_ESR(port) MMIO32((port) + 0x00C0)
|
||||
#define PIO_LSR(port) MMIO32((port) + 0x00C4)
|
||||
#define PIO_ELSR(port) MMIO32((port) + 0x00C8)
|
||||
/* 0x00CC - Reserved */
|
||||
#define PIO_FELLSR(port) MMIO32((port) + 0x00D0)
|
||||
#define PIO_REHLSR(port) MMIO32((port) + 0x00D4)
|
||||
#define PIO_FRLHSR(port) MMIO32((port) + 0x00D8)
|
||||
/* 0x00DC - Reserved */
|
||||
#define PIO_LOCKSR(port) MMIO32((port) + 0x00E0)
|
||||
#define PIO_WPMR(port) MMIO32((port) + 0x00E4)
|
||||
#define PIO_WPSR(port) MMIO32((port) + 0x00E8)
|
||||
/* 0x00EC-0x0144 - Reserved */
|
||||
|
||||
#endif
|
||||
145
include/libopencm3/sam/pmc.h
Normal file
145
include/libopencm3/sam/pmc.h
Normal file
@@ -0,0 +1,145 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef SAM3X_PMC_H
|
||||
#define SAM3X_PMC_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/sam/memorymap.h>
|
||||
|
||||
/* --- Power Management Controller (PMC) registers ----------------------- */
|
||||
|
||||
#define PMC_SCER MMIO32(PMC_BASE + 0x0000)
|
||||
#define PMC_SCDR MMIO32(PMC_BASE + 0x0004)
|
||||
#define PMC_SCSR MMIO32(PMC_BASE + 0x0008)
|
||||
/* 0x000C - Reserved */
|
||||
#define PMC_PCER0 MMIO32(PMC_BASE + 0x0010)
|
||||
#define PMC_PCDR0 MMIO32(PMC_BASE + 0x0014)
|
||||
#define PMC_PCSR0 MMIO32(PMC_BASE + 0x0018)
|
||||
#define CKGR_UCKR MMIO32(PMC_BASE + 0x001C)
|
||||
#define CKGR_MOR MMIO32(PMC_BASE + 0x0020)
|
||||
#define CKGR_MCFR MMIO32(PMC_BASE + 0x0024)
|
||||
#define CKGR_PLLAR MMIO32(PMC_BASE + 0x0028)
|
||||
/* 0x002C - Reserved */
|
||||
#define PMC_MCKR MMIO32(PMC_BASE + 0x0030)
|
||||
/* 0x0034 - Reserved */
|
||||
#define PMC_USB MMIO32(PMC_BASE + 0x0038)
|
||||
/* 0x003C - Reserved */
|
||||
#define PMC_PCK0 MMIO32(PMC_BASE + 0x0040)
|
||||
#define PMC_PCK1 MMIO32(PMC_BASE + 0x0044)
|
||||
#define PMC_PCK2 MMIO32(PMC_BASE + 0x0048)
|
||||
/* 0x004C-0x005C - Reserved */
|
||||
#define PMC_IER MMIO32(PMC_BASE + 0x0060)
|
||||
#define PMC_IDR MMIO32(PMC_BASE + 0x0064)
|
||||
#define PMC_SR MMIO32(PMC_BASE + 0x0068)
|
||||
#define PMC_IMR MMIO32(PMC_BASE + 0x006C)
|
||||
#define PMC_FSMR MMIO32(PMC_BASE + 0x0070)
|
||||
#define PMC_FSPR MMIO32(PMC_BASE + 0x0074)
|
||||
#define PMC_FOCR MMIO32(PMC_BASE + 0x0078)
|
||||
/* 0x007C-0x00E0 - Reserved */
|
||||
#define PMC_WPMR MMIO32(PMC_BASE + 0x00E4)
|
||||
#define PMC_WPSR MMIO32(PMC_BASE + 0x00E8)
|
||||
/* 0x00EC-0x00FC - Reserved */
|
||||
#define PMC_PCER1 MMIO32(PMC_BASE + 0x0100)
|
||||
#define PMC_PCDR1 MMIO32(PMC_BASE + 0x0104)
|
||||
#define PMC_PCSR1 MMIO32(PMC_BASE + 0x0108)
|
||||
#define PMC_PCR MMIO32(PMC_BASE + 0x010C)
|
||||
|
||||
/* PMC UTMI Clock Configuration Register (CKGR_UCKR) */
|
||||
/* Bit [31:22] - Reserved */
|
||||
#define CKGR_CKGR_UPLLCOUNT_MASK (0x0F << 20)
|
||||
/* Bit [19:17] - Reserved */
|
||||
#define CKGR_CKGR_UPLLEN (0x01 << 16)
|
||||
/* Bit [15:0] - Reserved */
|
||||
|
||||
/* PMC Clock Generator Main Oscillator Register (CKGR_MOR) */
|
||||
/* Bit [31:26] - Reserved */
|
||||
#define CKGR_MOR_CFDEN (0x01 << 25)
|
||||
#define CKGR_MOR_MOSCSEL (0x01 << 24)
|
||||
#define CKGR_MOR_KEY (0x37 << 16)
|
||||
#define CKGR_MOR_MOSCXTST_MASK (0xFF << 8)
|
||||
/* Bit 7 - Reserved */
|
||||
#define CKGR_MOR_MOSCRCF_MASK (0x07 << 4)
|
||||
#define CKGR_MOR_MOSCRCEN (0x01 << 3)
|
||||
/* Bit 2 - Reserved */
|
||||
#define CKGR_MOR_MOSCXTBY (0x01 << 1)
|
||||
#define CKGR_MOR_MOSCXTEN (0x01 << 0)
|
||||
|
||||
/* PMC Clock Generator PLLA Register (CKGR_PLLAR) */
|
||||
#define CKGR_PLLAR_ONE (0x01 << 29)
|
||||
#define CKGR_PLLAR_MULA_MASK (0x7FF << 16)
|
||||
#define CKGR_PLLAR_PLLACOUNT_MASK (0x3F << 8)
|
||||
#define CKGR_PLLAR_DIVA_MASK (0xFF << 0)
|
||||
|
||||
/* PMC Master Clock Register (PMC_MCKR) */
|
||||
/* Bit [31:14] - Reserved */
|
||||
#define PMC_MCKR_UPLLDIV2 (0x01 << 13)
|
||||
#define PMC_MCKR_PLLADIV2 (0x01 << 12)
|
||||
/* Bit [11:7] - Reserved */
|
||||
#define PMC_MCKR_PRES_MASK (0x07 << 4)
|
||||
/* Bit [3:2] - Reserved */
|
||||
#define PMC_MCKR_CSS_MASK (0x03 << 0)
|
||||
#define PMC_MCKR_CSS_SLOW_CLK (0x00 << 0)
|
||||
#define PMC_MCKR_CSS_MAIN_CLK (0x01 << 0)
|
||||
#define PMC_MCKR_CSS_PLLA_CLK (0x02 << 0)
|
||||
#define PMC_MCKR_CSS_UPLL_CLK (0x03 << 0)
|
||||
|
||||
/* PMC USB Clock Register (PMC_USB) */
|
||||
/* Bit [31:12] - Reserved */
|
||||
#define PMC_USB_USBDIV_MASK (0x0F << 8)
|
||||
/* Bit [7:1] - Reserved */
|
||||
#define PMC_USB_USBS (0x01 << 0)
|
||||
|
||||
/* PMC Status Register (PMC_SR) */
|
||||
/* Bits [31:21] - Reserved */
|
||||
#define PMC_SR_FOS (0x01 << 20)
|
||||
#define PMC_SR_CFDS (0x01 << 19)
|
||||
#define PMC_SR_CFDEV (0x01 << 18)
|
||||
#define PMC_SR_MOSCRCS (0x01 << 17)
|
||||
#define PMC_SR_MOSCSELS (0x01 << 16)
|
||||
/* Bits [15:11] - Reserved */
|
||||
#define PMC_SR_PCKRDY2 (0x01 << 10)
|
||||
#define PMC_SR_PCKRDY1 (0x01 << 9)
|
||||
#define PMC_SR_PCKRDY0 (0x01 << 8)
|
||||
#define PMC_SR_OSCSELS (0x01 << 7)
|
||||
#define PMC_SR_LOCKU (0x01 << 6)
|
||||
/* Bits [5:4] - Reserved */
|
||||
#define PMC_SR_MCKRDY (0x01 << 3)
|
||||
/* Bit [2] - Reserved */
|
||||
#define PMC_SR_LOCKA (0x01 << 1)
|
||||
#define PMC_SR_MOSCXTS (0x01 << 0)
|
||||
|
||||
extern u32 pmc_mck_frequency;
|
||||
|
||||
enum mck_src {
|
||||
MCK_SRC_SLOW = 0,
|
||||
MCK_SRC_MAIN = 1,
|
||||
MCK_SRC_PLLA = 2,
|
||||
MCK_SRC_UPLL = 3,
|
||||
};
|
||||
|
||||
void pmc_mck_set_source(enum mck_src src);
|
||||
void pmc_xtal_enable(bool en, u8 startup_time);
|
||||
void pmc_plla_config(u8 mul, u8 div);
|
||||
void pmc_peripheral_clock_enable(u8 pid);
|
||||
void pmc_peripheral_clock_disable(u8 pid);
|
||||
void pmc_clock_setup_in_xtal_12mhz_out_84mhz(void);
|
||||
|
||||
#endif
|
||||
|
||||
109
include/libopencm3/sam/pwm.h
Normal file
109
include/libopencm3/sam/pwm.h
Normal file
@@ -0,0 +1,109 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef SAM3X_PWM_H
|
||||
#define SAM3X_PWM_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/sam/memorymap.h>
|
||||
|
||||
/* --- Pulse Width Modulation (PWM) registers ----------------------- */
|
||||
|
||||
#define PWM_CLK MMIO32(PWM_BASE + 0x0000)
|
||||
#define PWM_ENA MMIO32(PWM_BASE + 0x0004)
|
||||
#define PWM_DIS MMIO32(PWM_BASE + 0x0008)
|
||||
#define PWM_SR MMIO32(PWM_BASE + 0x000C)
|
||||
#define PWM_IER1 MMIO32(PWM_BASE + 0x0010)
|
||||
#define PWM_IDR1 MMIO32(PWM_BASE + 0x0014)
|
||||
#define PWM_IMR1 MMIO32(PWM_BASE + 0x0018)
|
||||
#define PWM_ISR1 MMIO32(PWM_BASE + 0x001C)
|
||||
#define PWM_SCM MMIO32(PWM_BASE + 0x0020)
|
||||
/* 0x0024 - Reserved */
|
||||
#define PWM_SCUC MMIO32(PWM_BASE + 0x0028)
|
||||
#define PWM_SCUP MMIO32(PWM_BASE + 0x002C)
|
||||
#define PWM_SCUPUPD MMIO32(PWM_BASE + 0x0030)
|
||||
#define PWM_IER2 MMIO32(PWM_BASE + 0x0034)
|
||||
#define PWM_IDR2 MMIO32(PWM_BASE + 0x0038)
|
||||
#define PWM_IMR2 MMIO32(PWM_BASE + 0x003C)
|
||||
#define PWM_ISR2 MMIO32(PWM_BASE + 0x0040)
|
||||
#define PWM_OOV MMIO32(PWM_BASE + 0x0044)
|
||||
#define PWM_OS MMIO32(PWM_BASE + 0x0048)
|
||||
#define PWM_OSS MMIO32(PWM_BASE + 0x004C)
|
||||
#define PWM_OSC MMIO32(PWM_BASE + 0x0050)
|
||||
#define PWM_OSSUPD MMIO32(PWM_BASE + 0x0054)
|
||||
#define PWM_OSCUPD MMIO32(PWM_BASE + 0x0058)
|
||||
#define PWM_FMR MMIO32(PWM_BASE + 0x005C)
|
||||
#define PWM_FSR MMIO32(PWM_BASE + 0x0060)
|
||||
#define PWM_FCR MMIO32(PWM_BASE + 0x0064)
|
||||
#define PWM_FPV MMIO32(PWM_BASE + 0x0068)
|
||||
#define PWM_FPE1 MMIO32(PWM_BASE + 0x006C)
|
||||
#define PWM_FPE2 MMIO32(PWM_BASE + 0x0070)
|
||||
/* 0x0074:0x0078 - Reserved */
|
||||
#define PWM_ELMR0 MMIO32(PWM_BASE + 0x007C)
|
||||
#define PWM_ELMR1 MMIO32(PWM_BASE + 0x0080)
|
||||
/* 0x0084:0x00AC - Reserved */
|
||||
#define PWM_SMMR MMIO32(PWM_BASE + 0x00B0)
|
||||
/* 0x00B4:0x00E0 - Reserved */
|
||||
#define PWM_WPCR MMIO32(PWM_BASE + 0x00E4)
|
||||
#define PWM_WPSR MMIO32(PWM_BASE + 0x00E8)
|
||||
/* 0x00EC:0x00FC - Reserved */
|
||||
/* 0x0100:0x012C - Reserved */
|
||||
#define PWM_CMPV(x) MMIO32(PWM_BASE + 0x0130 + 0x10*(x))
|
||||
#define PWM_CMPVUPD(x) MMIO32(PWM_BASE + 0x0134 + 0x10*(x))
|
||||
#define PWM_CMMV(x) MMIO32(PWM_BASE + 0x0138 + 0x10*(x))
|
||||
#define PWM_CMMVUPD(x) MMIO32(PWM_BASE + 0x013C + 0x10*(x))
|
||||
/* 0x01B0:0x01FC - Reserved */
|
||||
#define PWM_CMR(x) MMIO32(PWM_BASE + 0x0200 + 0x20*(x))
|
||||
#define PWM_CDTY(x) MMIO32(PWM_BASE + 0x0204 + 0x20*(x))
|
||||
#if defined(SAM3X)
|
||||
# define PWM_CDTYUPD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x))
|
||||
# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x))
|
||||
# define PWM_CPRDUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x))
|
||||
# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x0214 + 0x20*(x))
|
||||
# define PWM_DT(x) MMIO32(PWM_BASE + 0x0218 + 0x20*(x))
|
||||
# define PWM_DTUPD(x) MMIO32(PWM_BASE + 0x021C + 0x20*(x))
|
||||
#elif defined(SAM3N)
|
||||
# define PWM_CPRD(x) MMIO32(PWM_BASE + 0x0208 + 0x20*(x))
|
||||
# define PWM_CCNT(x) MMIO32(PWM_BASE + 0x020C + 0x20*(x))
|
||||
# define PWM_CUPD(x) MMIO32(PWM_BASE + 0x0210 + 0x20*(x))
|
||||
#else
|
||||
# error "Processor family not defined."
|
||||
#endif
|
||||
|
||||
static inline void pwm_set_period(int ch, u32 period)
|
||||
{
|
||||
PWM_CPRD(ch) = period;
|
||||
}
|
||||
|
||||
static inline void pwm_set_duty(int ch, u32 duty)
|
||||
{
|
||||
PWM_CDTY(ch) = duty;
|
||||
}
|
||||
|
||||
static inline void pwm_enable(int ch)
|
||||
{
|
||||
PWM_ENA = 1 << ch;
|
||||
}
|
||||
|
||||
static inline void pwm_disable(int ch)
|
||||
{
|
||||
PWM_DIS = 1 << ch;
|
||||
}
|
||||
|
||||
#endif
|
||||
52
include/libopencm3/sam/tc.h
Normal file
52
include/libopencm3/sam/tc.h
Normal file
@@ -0,0 +1,52 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef SAM3X_TC_H
|
||||
#define SAM3X_TC_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/sam/memorymap.h>
|
||||
|
||||
/* --- Timer Counter (TC) registers -------------------------------------- */
|
||||
|
||||
#define TC_CCR(x) MMIO32(TC_BASE + 0x00 + 0x40*(x))
|
||||
#define TC_CMR(x) MMIO32(TC_BASE + 0x04 + 0x40*(x))
|
||||
#define TC_SMMR(x) MMIO32(TC_BASE + 0x08 + 0x40*(x))
|
||||
/* 0x0C + 0x40*channel - Reserved */
|
||||
#define TC_CV(x) MMIO32(TC_BASE + 0x10 + 0x40*(x))
|
||||
#define TC_RA(x) MMIO32(TC_BASE + 0x14 + 0x40*(x))
|
||||
#define TC_RB(x) MMIO32(TC_BASE + 0x18 + 0x40*(x))
|
||||
#define TC_RC(x) MMIO32(TC_BASE + 0x1C + 0x40*(x))
|
||||
#define TC_SR(x) MMIO32(TC_BASE + 0x20 + 0x40*(x))
|
||||
#define TC_IER(x) MMIO32(TC_BASE + 0x24 + 0x40*(x))
|
||||
#define TC_IDR(x) MMIO32(TC_BASE + 0x28 + 0x40*(x))
|
||||
#define TC_IMR(x) MMIO32(TC_BASE + 0x2C + 0x40*(x))
|
||||
#define TC_BCR MMIO32(TC_BASE + 0xC0)
|
||||
#define TC_BMR MMIO32(TC_BASE + 0xC4)
|
||||
#define TC_QIER MMIO32(TC_BASE + 0xC8)
|
||||
#define TC_QIDR MMIO32(TC_BASE + 0xCC)
|
||||
#define TC_QIMR MMIO32(TC_BASE + 0xD0)
|
||||
#define TC_QISR MMIO32(TC_BASE + 0xD4)
|
||||
#define TC_FMR MMIO32(TC_BASE + 0xD8)
|
||||
/* 0x00DC:0x00E0 - Undocumented */
|
||||
#define TC_WPMR MMIO32(TC_BASE + 0xE4)
|
||||
/* 0x00E8:0x00F8 - Undocumented */
|
||||
/* 0x00FC - Reserved */
|
||||
|
||||
#endif
|
||||
85
include/libopencm3/sam/uart.h
Normal file
85
include/libopencm3/sam/uart.h
Normal file
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef SAM3X_UART_H
|
||||
#define SAM3X_UART_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/sam/memorymap.h>
|
||||
|
||||
/* --- Universal Asynchronous Receiver Transmitter (UART) registers ------- */
|
||||
#define UART_CR MMIO32(UART_BASE + 0x0000)
|
||||
#define UART_MR MMIO32(UART_BASE + 0x0004)
|
||||
#define UART_IER MMIO32(UART_BASE + 0x0008)
|
||||
#define UART_IDR MMIO32(UART_BASE + 0x000C)
|
||||
#define UART_IMR MMIO32(UART_BASE + 0x0010)
|
||||
#define UART_SR MMIO32(UART_BASE + 0x0014)
|
||||
#define UART_RHR MMIO32(UART_BASE + 0x0018)
|
||||
#define UART_THR MMIO32(UART_BASE + 0x001C)
|
||||
#define UART_BRGR MMIO32(UART_BASE + 0x0020)
|
||||
/* 0x0024:0x003C - Reserved */
|
||||
/* 0x004C:0x00FC - Reserved */
|
||||
/* 0x0100:0x0124 - PDC Area */
|
||||
|
||||
|
||||
/* UART Control Register (UART_CR) */
|
||||
/* Bits [31:9] - Reserved */
|
||||
#define UART_CR_RSTSTA (0x01 << 8)
|
||||
#define UART_CR_TXDIS (0x01 << 7)
|
||||
#define UART_CR_TXEN (0x01 << 6)
|
||||
#define UART_CR_RXDIS (0x01 << 5)
|
||||
#define UART_CR_RXEN (0x01 << 4)
|
||||
#define UART_CR_RSTTX (0x01 << 3)
|
||||
#define UART_CR_RSTRX (0x01 << 2)
|
||||
/* Bit [1:0] - Reserved */
|
||||
|
||||
/* UART Mode Register (UART_MR) */
|
||||
/* Bits [31:16] - Reserved */
|
||||
#define UART_MR_CHMODE_MASK (0x03 << 14)
|
||||
#define UART_MR_CHMODE_NORMAL (0x00 << 14)
|
||||
#define UART_MR_CHMODE_AUTOMATIC (0x01 << 14)
|
||||
#define UART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14)
|
||||
#define UART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14)
|
||||
/* Bits [13:12] - Reserved */
|
||||
#define UART_MR_PAR_MASK (0x07 << 9)
|
||||
#define UART_MR_PAR_EVEN (0x00 << 9)
|
||||
#define UART_MR_PAR_ODD (0x01 << 9)
|
||||
#define UART_MR_PAR_SPACE (0x02 << 9)
|
||||
#define UART_MR_PAR_MARK (0x03 << 9)
|
||||
#define UART_MR_PAR_NO (0x04 << 9)
|
||||
/* Bits [8:0] - Reserved */
|
||||
|
||||
/* UART Status Register (UART_SR) */
|
||||
/* Bits [31:13] - Reserved */
|
||||
#define UART_SR_RXBUFF (0x01 << 12)
|
||||
#define UART_SR_TXBUFF (0x01 << 11)
|
||||
/* Bit [10] - Reserved */
|
||||
#define UART_SR_TXEMPTY (0x01 << 9)
|
||||
/* Bit [8] - Reserved */
|
||||
#define UART_SR_PARE (0x01 << 7)
|
||||
#define UART_SR_FRAME (0x01 << 6)
|
||||
#define UART_SR_OVRE (0x01 << 5)
|
||||
#define UART_SR_ENDTX (0x01 << 4)
|
||||
#define UART_SR_ENDRX (0x01 << 3)
|
||||
/* Bit [2] - Reserved */
|
||||
#define UART_SR_TXRDY (0x01 << 1)
|
||||
#define UART_SR_RXRDY (0x01 << 0)
|
||||
|
||||
#endif
|
||||
|
||||
217
include/libopencm3/sam/usart.h
Normal file
217
include/libopencm3/sam/usart.h
Normal file
@@ -0,0 +1,217 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef SAM3X_USART_H
|
||||
#define SAM3X_USART_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/sam/memorymap.h>
|
||||
|
||||
#define USART0 USART0_BASE
|
||||
#define USART1 USART1_BASE
|
||||
#define USART2 USART2_BASE
|
||||
#define USART3 USART3_BASE
|
||||
|
||||
/* --- Universal Synchronous Asynchronous Receiver Transmitter (USART) */
|
||||
#define USART_CR(x) MMIO32((x) + 0x0000)
|
||||
#define USART_MR(x) MMIO32((x) + 0x0004)
|
||||
#define USART_IER(x) MMIO32((x) + 0x0008)
|
||||
#define USART_IDR(x) MMIO32((x) + 0x000C)
|
||||
#define USART_IMR(x) MMIO32((x) + 0x0010)
|
||||
#define USART_CSR(x) MMIO32((x) + 0x0014)
|
||||
#define USART_RHR(x) MMIO32((x) + 0x0018)
|
||||
#define USART_THR(x) MMIO32((x) + 0x001C)
|
||||
#define USART_BRGR(x) MMIO32((x) + 0x0020)
|
||||
#define USART_RTOR(x) MMIO32((x) + 0x0024)
|
||||
#define USART_TTGR(x) MMIO32((x) + 0x0028)
|
||||
/* 0x002C:0x003C - Reserved */
|
||||
#define USART_FIDI(x) MMIO32((x) + 0x0040)
|
||||
#define USART_NER(x) MMIO32((x) + 0x0044)
|
||||
#define USART_NER(x) MMIO32((x) + 0x0044)
|
||||
/* 0x0048 - Reserved */
|
||||
#define USART_IF(x) MMIO32((x) + 0x004C)
|
||||
#define USART_MAN(x) MMIO32((x) + 0x0050)
|
||||
#define USART_LINMR(x) MMIO32((x) + 0x0054)
|
||||
#define USART_LINIR(x) MMIO32((x) + 0x0058)
|
||||
/* 0x005C:0x00E0 - Reserved */
|
||||
#define USART_WPMR(x) MMIO32((x) + 0x00E4)
|
||||
#define USART_WPSR(x) MMIO32((x) + 0x00E8)
|
||||
/* 0x00EC:0x00F8 - Reserved */
|
||||
#define USART_VERSION(x) MMIO32((x) + 0x00FC)
|
||||
/* 0x0100:0x0124 - PDC Area */
|
||||
|
||||
|
||||
/* USART Control Register (USART_CR) */
|
||||
/* Bits [31:22] - Reserved */
|
||||
#define USART_CR_LINWKUP (0x01 << 21)
|
||||
#define USART_CR_LINABT (0x01 << 20)
|
||||
#define USART_CR_RTSDIS (0x01 << 19)
|
||||
#define USART_CR_RCS (0x01 << 19)
|
||||
#define USART_CR_RTSEN (0x01 << 18)
|
||||
#define USART_CR_FCS (0x01 << 18)
|
||||
/* Bits [17:16] - Reserved */
|
||||
#define USART_CR_RETTO (0x01 << 15)
|
||||
#define USART_CR_RSTNACK (0x01 << 14)
|
||||
#define USART_CR_RSTIT (0x01 << 13)
|
||||
#define USART_CR_SENDA (0x01 << 12)
|
||||
#define USART_CR_STTTO (0x01 << 11)
|
||||
#define USART_CR_STPBRK (0x01 << 10)
|
||||
#define USART_CR_STTBRK (0x01 << 9)
|
||||
#define USART_CR_RSTSTA (0x01 << 8)
|
||||
#define USART_CR_TXDIS (0x01 << 7)
|
||||
#define USART_CR_TXEN (0x01 << 6)
|
||||
#define USART_CR_RXDIS (0x01 << 5)
|
||||
#define USART_CR_RXEN (0x01 << 4)
|
||||
#define USART_CR_RSTTX (0x01 << 3)
|
||||
#define USART_CR_RSTRX (0x01 << 2)
|
||||
/* Bits [1:0] - Reserved */
|
||||
|
||||
/* USART Mode Register (USART_MR) */
|
||||
#define USART_MR_ONEBIT (0x01 << 31)
|
||||
#define USART_MR_MODSYNC (0x01 << 30)
|
||||
#define USART_MR_MAN (0x01 << 29)
|
||||
#define USART_MR_FILTER (0x01 << 28)
|
||||
/* Bit [27] - Reserved */
|
||||
#define USART_MR_MAX_ITERATION_MASK (0x07 << 24)
|
||||
#define USART_MR_INVDATA (0x01 << 23)
|
||||
#define USART_MR_VAR_SYNC (0x01 << 22)
|
||||
#define USART_MR_DSNACK (0x01 << 21)
|
||||
#define USART_MR_INACK (0x01 << 20)
|
||||
#define USART_MR_OVER (0x01 << 19)
|
||||
#define USART_MR_CLKO (0x01 << 18)
|
||||
#define USART_MR_MODE9 (0x01 << 17)
|
||||
#define USART_MR_MSBF (0x01 << 16)
|
||||
#define USART_MR_CPOL (0x01 << 16)
|
||||
#define USART_MR_CHMODE_MASK (0x03 << 14)
|
||||
#define USART_MR_CHMODE_NORMAL (0x00 << 14)
|
||||
#define USART_MR_CHMODE_AUTOMATIC (0x01 << 14)
|
||||
#define USART_MR_CHMODE_LOCAL_LOOPBACK (0x02 << 14)
|
||||
#define USART_MR_CHMODE_REMOTE_LOOPBACK (0x03 << 14)
|
||||
#define USART_MR_NBSTOP_MASK (0x03 << 12)
|
||||
#define USART_MR_NBSTOP_1_BIT (0x00 << 12)
|
||||
#define USART_MR_NBSTOP_1_5_BIT (0x01 << 12)
|
||||
#define USART_MR_NBSTOP_2_BIT (0x02 << 12)
|
||||
/* Bits [13:12] - Reserved */
|
||||
#define USART_MR_PAR_MASK (0x07 << 9)
|
||||
#define USART_MR_PAR_EVEN (0x00 << 9)
|
||||
#define USART_MR_PAR_ODD (0x01 << 9)
|
||||
#define USART_MR_PAR_SPACE (0x02 << 9)
|
||||
#define USART_MR_PAR_MARK (0x03 << 9)
|
||||
#define USART_MR_PAR_NO (0x04 << 9)
|
||||
/* Bits [8:0] - Reserved */
|
||||
#define USART_MR_SYNC (0x01 << 8)
|
||||
#define USART_MR_CPHA (0x01 << 8)
|
||||
#define USART_MR_CHRL_MASK (0x03 << 6)
|
||||
#define USART_MR_CHRL_5BIT (0x00 << 6)
|
||||
#define USART_MR_CHRL_6BIT (0x01 << 6)
|
||||
#define USART_MR_CHRL_7BIT (0x02 << 6)
|
||||
#define USART_MR_CHRL_8BIT (0x03 << 6)
|
||||
#define USART_MR_USCLKS_MASK (0x03 << 4)
|
||||
#define USART_MR_USCLKS_MCK (0x00 << 4)
|
||||
#define USART_MR_USCLKS_DIV (0x01 << 4)
|
||||
#define USART_MR_USCLKS_SCK (0x03 << 4)
|
||||
#define USART_MR_MODE_MASK (0x0F << 0)
|
||||
#define USART_MR_MODE_NORMAL (0x00 << 0)
|
||||
#define USART_MR_MODE_RS485 (0x01 << 0)
|
||||
#define USART_MR_MODE_HW_HANDSHAKING (0x02 << 0)
|
||||
#define USART_MR_MODE_ISO7816_T_0 (0x03 << 0)
|
||||
#define USART_MR_MODE_ISO7816_T_1 (0x04 << 0)
|
||||
#define USART_MR_MODE_IRDA (0x06 << 0)
|
||||
#define USART_MR_MODE_LIN_MASTER (0x0A << 0)
|
||||
#define USART_MR_MODE_LIN_SLAVE (0x0B << 0)
|
||||
#define USART_MR_MODE_SPI_MASTER (0x0E << 0)
|
||||
#define USART_MR_MODE_SPI_SLAVE (0x0F << 0)
|
||||
|
||||
/* USART Status Register (USART_CSR) */
|
||||
/* Bits [31:30] - Reserved */
|
||||
#define USART_CSR_LINSNRE (0x01 << 29)
|
||||
#define USART_CSR_LINCE (0x01 << 28)
|
||||
#define USART_CSR_LINIPE (0x01 << 27)
|
||||
#define USART_CSR_LINSFE (0x01 << 26)
|
||||
#define USART_CSR_LINBE (0x01 << 25)
|
||||
#define USART_CSR_MANERR (0x01 << 24)
|
||||
#define USART_CSR_CTS (0x01 << 23)
|
||||
#define USART_CSR_LINBLS (0x01 << 23)
|
||||
/* Bits [22:20] - Reserved */
|
||||
#define USART_CSR_CTSIC (0x01 << 19)
|
||||
/* Bits [18:16] - Reserved */
|
||||
#define USART_CSR_LINTC (0x01 << 15)
|
||||
#define USART_CSR_LINID (0x01 << 14)
|
||||
#define USART_CSR_NACK (0x01 << 13)
|
||||
#define USART_CSR_LINBK (0x01 << 13)
|
||||
#define USART_CSR_RXBUFF (0x01 << 12)
|
||||
#define USART_CSR_TXBUFE (0x01 << 11)
|
||||
/* Bit [10] - Reserved */
|
||||
#define USART_CSR_TXEMPTY (0x01 << 9)
|
||||
/* Bit [8] - Reserved */
|
||||
#define USART_CSR_PARE (0x01 << 7)
|
||||
#define USART_CSR_FRAME (0x01 << 6)
|
||||
#define USART_CSR_OVRE (0x01 << 5)
|
||||
#define USART_CSR_ENDTX (0x01 << 4)
|
||||
#define USART_CSR_ENDRX (0x01 << 3)
|
||||
/* Bit [2] - Reserved */
|
||||
#define USART_CSR_TXRDY (0x01 << 1)
|
||||
#define USART_CSR_RXRDY (0x01 << 0)
|
||||
|
||||
enum usart_stopbits {
|
||||
USART_STOPBITS_1,
|
||||
USART_STOPBITS_1_5,
|
||||
USART_STOPBITS_2,
|
||||
};
|
||||
|
||||
enum usart_parity {
|
||||
USART_PARITY_EVEN,
|
||||
USART_PARITY_ODD,
|
||||
USART_PARITY_SPACE,
|
||||
USART_PARITY_MARK,
|
||||
USART_PARITY_NONE,
|
||||
USART_PARITY_MULTIDROP,
|
||||
};
|
||||
|
||||
enum usart_mode {
|
||||
USART_MODE_DISABLED,
|
||||
USART_MODE_RX,
|
||||
USART_MODE_TX,
|
||||
USART_MODE_TX_RX,
|
||||
};
|
||||
|
||||
enum usart_flowcontrol {
|
||||
USART_FLOWCONTROL_NONE,
|
||||
USART_FLOWCONTROL_RTS_CTS,
|
||||
};
|
||||
|
||||
void usart_set_baudrate(u32 usart, u32 baud);
|
||||
void usart_set_databits(u32 usart, int bits);
|
||||
void usart_set_stopbits(u32 usart, enum usart_stopbits);
|
||||
void usart_set_parity(u32 usart, enum usart_parity);
|
||||
void usart_set_mode(u32 usart, enum usart_mode);
|
||||
void usart_set_flow_control(u32 usart, enum usart_flowcontrol);
|
||||
void usart_enable(u32 usart);
|
||||
void usart_disable(u32 usart);
|
||||
void usart_send(u32 usart, u16 data);
|
||||
u16 usart_recv(u32 usart);
|
||||
void usart_wait_send_ready(u32 usart);
|
||||
void usart_wait_recv_ready(u32 usart);
|
||||
void usart_send_blocking(u32 usart, u16 data);
|
||||
u16 usart_recv_blocking(u32 usart);
|
||||
void usart_enable_rx_interrupt(u32 usart);
|
||||
void usart_disable_rx_interrupt(u32 usart);
|
||||
|
||||
#endif
|
||||
|
||||
57
include/libopencm3/sam/wdt.h
Normal file
57
include/libopencm3/sam/wdt.h
Normal file
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2013 Gareth McMullin <gareth@blacksphere.co.nz>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef SAM3X_WDT_H
|
||||
#define SAM3X_WDT_H
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/sam/memorymap.h>
|
||||
|
||||
|
||||
/* --- WDT registers ----------------------------------------------------- */
|
||||
|
||||
#define WDT_CR MMIO32(WDT_BASE + 0x00)
|
||||
#define WDT_MR MMIO32(WDT_BASE + 0x04)
|
||||
#define WDT_SR MMIO32(WDT_BASE + 0x08)
|
||||
|
||||
/* --- WDT_CR values ------------------------------------------------------ */
|
||||
|
||||
#define WDT_CR_KEY (0xA5 << 24)
|
||||
/* Bits [23:1]: Reserved. */
|
||||
#define WDT_CR_WDRSTT (1 << 0)
|
||||
|
||||
/* --- WDT_MR values ------------------------------------------------------ */
|
||||
|
||||
/* Bits [31:32]: Reserved. */
|
||||
#define WDT_MR_WDIDLEHLT (1 << 29)
|
||||
#define WDT_MR_WDDBGHLT (1 << 28)
|
||||
#define WDT_MR_WDD_MASK (0xFFF << 16)
|
||||
#define WDT_MR_WDDIS (1 << 15)
|
||||
#define WDT_MR_WDRPROC (1 << 14)
|
||||
#define WDT_MR_WDRSTEN (1 << 13)
|
||||
#define WDT_MR_WDFIEN (1 << 12)
|
||||
#define WDT_MR_WDV_MASK (0xFFF << 0)
|
||||
|
||||
/* --- WDT_SR values ------------------------------------------------------ */
|
||||
|
||||
/* Bits [31:2]: Reserved. */
|
||||
#define WDT_SR_WDERR (1 << 1)
|
||||
#define WDT_SR_WDUNF (1 << 0)
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user