stm32/h7: Implemented support for the Flash controller having untangled the previous pretending it was the F2/F4 controller mess
This commit is contained in:
dragonmux
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
ee418f1780
commit
cdd8f2adac
@@ -5,6 +5,8 @@
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*
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* @author @htmlonly © @endhtmlonly 2019
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* Brian Viele <vielster@allocor.tech>
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* @author @htmlonly © @endhtmlonly 2024
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* Rachel Mant <git@dragonmux.network>
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*/
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/*
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* This file is part of the libopencm3 project.
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@@ -26,11 +28,51 @@
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#ifndef LIBOPENCM3_FLASH_H
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#define LIBOPENCM3_FLASH_H
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#include <libopencm3/stm32/common/flash_common_all.h>
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#include <libopencm3/stm32/common/flash_common_f.h>
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#include <libopencm3/stm32/common/flash_common_f24.h>
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#include <stdbool.h>
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#include <stddef.h>
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#include <libopencm3/stm32/common/flash_common_idcache.h>
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/**@{*/
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#define FLASH_FPEC1_BASE (FLASH_MEM_INTERFACE_BASE + 0x000U)
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#define FLASH_FPEC2_BASE (FLASH_MEM_INTERFACE_BASE + 0x100U)
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/** @defgroup flash_registers Flash Registers
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* @ingroup flash_defines
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@{*/
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/** Flash Access Control register */
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#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00U)
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/** Flash Key register */
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#define FLASH_KEYR 0x04U
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/** Flash Option bytes key register */
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#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08U)
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/** Flash Control register */
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#define FLASH_CR 0x0CU
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/** Flash Status register - NB: Read-only on H7!! */
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#define FLASH_SR 0x10U
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/** Flash Clear Control register */
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#define FLASH_CCR 0x14U
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/** Flash Option Control register */
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#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18U)
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/** Flash Option Status read side register */
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#define FLASH_OPTSR_CUR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1CU)
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/** Flash Option Status write side register */
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#define FLASH_OPTSR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18U)
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/**@}*/
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/** @defgroup flash_latency FLASH Wait States
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@ingroup flash_defines
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@{*/
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#define FLASH_ACR_LATENCY(w) ((w) & FLASH_ACR_LATENCY_MASK)
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#define FLASH_ACR_LATENCY_0WS FLASH_ACR_LATENCY(0U)
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#define FLASH_ACR_LATENCY_1WS FLASH_ACR_LATENCY(1U)
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#define FLASH_ACR_LATENCY_2WS FLASH_ACR_LATENCY(2U)
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#define FLASH_ACR_LATENCY_3WS FLASH_ACR_LATENCY(3U)
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#define FLASH_ACR_LATENCY_4WS FLASH_ACR_LATENCY(4U)
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#define FLASH_ACR_LATENCY_5WS FLASH_ACR_LATENCY(5U)
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#define FLASH_ACR_LATENCY_6WS FLASH_ACR_LATENCY(6U)
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#define FLASH_ACR_LATENCY_7WS FLASH_ACR_LATENCY(7U)
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/**@}*/
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#define FLASH_ACR_LATENCY_SHIFT 0U
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#define FLASH_ACR_LATENCY_MASK 0x0fU
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/** @addtogroup flash_acr_values FLASH_ACR values
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* @ingroup flash_registers
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@@ -49,7 +91,205 @@
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#define FLASH_ACR_WRHIGHFREQ_MASK (0x3)
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#define FLASH_ACR_WRHIGHFREQ_SHIFT (0x4)
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/* --- FLASH_SR values ----------------------------------------------------- */
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#define FLASH_SR_BSY (1U << 0U)
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#define FLASH_SR_WBNE (1U << 1U)
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#define FLASH_SR_QW (1U << 2U)
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#define FLASH_SR_CRC_BUSY (1U << 3U)
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#define FLASH_SR_EOP (1U << 16U)
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#define FLASH_SR_WRPERR (1U << 17U)
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#define FLASH_SR_PGSERR (1U << 18U)
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#define FLASH_SR_STRBERR (1U << 19U)
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#define FLASH_SR_INCERR (1U << 21U)
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#define FLASH_SR_OPERR (1U << 22U)
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#define FLASH_SR_RDPERR (1U << 23U)
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#define FLASH_SR_RDSERR (1U << 24U)
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#define FLASH_SR_SNECCERR (1U << 25U)
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#define FLASH_SR_DBECCERR (1U << 26U)
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#define FLASH_SR_CRCEND (1U << 27U)
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#define FLASH_SR_CRCRDERR (1U << 28U)
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#define FLASH_SR_READ_ERROR_MASK \
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(FLASH_SR_RDPERR | FLASH_SR_RDSERR | FLASH_SR_SNECCERR | FLASH_SR_DBECCERR)
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#define FLASH_SR_ERROR_MASK ( \
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FLASH_SR_WRPERR | FLASH_SR_PGSERR | FLASH_SR_STRBERR | \
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FLASH_SR_INCERR | FLASH_SR_OPERR | FLASH_SR_READ_ERROR_MASK \
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)
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/* --- FLASH_CR values ----------------------------------------------------- */
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#define FLASH_CR_LOCK (1U << 0U)
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#define FLASH_CR_PG (1U << 1U)
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#define FLASH_CR_SER (1U << 2U)
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#define FLASH_CR_BER (1U << 3U)
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#define FLASH_CR_PROGRAM_MASK 0x3U
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#define FLASH_CR_PROGRAM_SHIFT (4U)
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#define FLASH_CR_FW (1U << 6U)
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#define FLASH_CR_STRT (1U << 7U)
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#define FLASH_CR_H7Bx_FW (1U << 4U)
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#define FLASH_CR_H7Bx_STRT (1U << 5U)
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#define FLASH_CR_SNB_SHIFT (8U)
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#define FLASH_CR_SNB_MASK (0x3U << FLASH_CR_SNB_SHIFT)
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#define FLASH_CR_H7Bx_SNB_SHIFT (6U)
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#define FLASH_CR_H7Bx_SNB_MASK (0x3U << FLASH_CR_H7Bx_SNB_SHIFT)
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#define FLASH_CR_CRC_EN (1U << 15U)
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#define FLASH_CR_EOPIE (1U << 16U)
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#define FLASH_CR_WRPERRIE (1U << 17U)
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#define FLASH_CR_PGSERRIE (1U << 18U)
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#define FLASH_CR_STRBERRIE (1U << 19U)
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#define FLASH_CR_INCERRIE (1U << 21U)
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#define FLASH_CR_OPERRIE (1U << 22U)
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#define FLASH_CR_RDPERRIE (1U << 23U)
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#define FLASH_CR_RDSERRIE (1U << 24U)
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#define FLASH_CR_SNECCERRIE (1U << 25U)
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#define FLASH_CR_DBECCERRIE (1U << 26U)
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#define FLASH_CR_CRCENDIE (1U << 27U)
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#define FLASH_CR_CRCRDERRIE (1U << 28U)
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/* The operation control bits are all in the lower half the register */
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#define FLASH_CR_OP_MASK (0x0000ffffU)
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/** @defgroup flash_cr_program_width Flash programming width
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@ingroup flash_group
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@{*/
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#define FLASH_CR_PROGRAM_X8 0U
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#define FLASH_CR_PROGRAM_X16 1U
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#define FLASH_CR_PROGRAM_X32 2U
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#define FLASH_CR_PROGRAM_X64 3U
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/**@}*/
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/* --- FLASH_OPTCR values -------------------------------------------------- */
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#define FLASH_OPTCR_OPTLOCK (1U << 0U)
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#define FLASH_OPTCR_OPTSTRT (1U << 1U)
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/* --- Flash Keys -----------------------------------------------------------*/
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#define FLASH_KEYR_KEY1 (0x45670123U)
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#define FLASH_KEYR_KEY2 (0xcdef89abU)
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#define FLASH_OPTKEYR_KEY1 (0x08192a3bU)
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#define FLASH_OPTKEYR_KEY2 (0x4c5d6e7fU)
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/* --- Flash Bank access constants ----------------------------------------- */
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#define FLASH_BANK_MAX_SIZE (0x00100000U)
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#define FLASH_WRITE_BLOCK_SIZE (32U)
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#define FLASH_WRITE_BLOCK_MASK (0x0000001FU)
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enum flash_bank {
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FLASH_BANK_1 = 1,
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FLASH_BANK_2,
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};
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/* --- Function prototypes ------------------------------------------------- */
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BEGIN_DECLS
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/** Set the Number of Wait States.
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*
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* Used to match the system clock to the FLASH memory access time. See the
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* programming manual for more information on clock speed ranges. The latency must
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* be changed to the appropriate value <b>before</b> any increase in clock
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* speed, or <b>after</b> any decrease in clock speed.
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*
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* @param[in] wait_states values from @ref flash_latency.
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*/
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void flash_set_ws(uint32_t wait_states);
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/** Check if the FPEC is currently busy with an operation */
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bool flash_is_busy(enum flash_bank bank);
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/** Clear the End of OPeration flag. */
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void flash_clear_eop_flag(enum flash_bank bank);
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/** Clear all status flags. */
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void flash_clear_status_flags(enum flash_bank bank);
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/** Wait until Last Operation has Ended.
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* This loops indefinitely until an operation (write or erase) has completed by
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* testing for EOP and nothing being left in the queue.
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*
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* Returns whether the operation was a success or not
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*/
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bool flash_wait_for_last_operation(enum flash_bank bank);
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/** Check if the FPEC is currently locked for writes. */
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bool flash_is_locked(enum flash_bank bank);
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/** Unlock the Flash Program and Erase Controller.
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* This enables write access to the Flash memory. It is locked by default on
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* reset.
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*/
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void flash_unlock(enum flash_bank bank);
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/** Lock the Flash Program and Erase Controller.
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* Used to prevent spurious writes to FLASH.
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*/
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void flash_lock(enum flash_bank bank);
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/** Erases a sector of a bank of Flash.
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*
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* NB: The second bank is not always valid on all STM32H7 parts. Check your part datasheet
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* to determine if it exists and is valid before using this function with FLASH_BANK_2.
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*
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* @param[in] bank one of the FLASH_BANK_* constants indicating which bank to erase
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* @param[in] sector the sector number in the bank to erase
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* @param[in] operation_parallelism the write parallelism to use for the erase -
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* one of the PROGRAM_SIZE_* constants
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*/
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void flash_erase_sector(enum flash_bank bank, uint8_t sector, uint8_t operation_parallelism);
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/** Erases a whole bank of Flash.
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*
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* Which banks are valid depends on your part as follows:
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* - H72x/H73x: Flash Bank 1 **only**
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* - H74x/H75x:
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* - H75xB: Flash Bank 1 **only** with 128kiB of Flash total
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* - H74xG: Both banks, split at 512kiB for 1MiB total
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* - H7xxI: Both banks, split at 1MiB for 2MiB total
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* - H7Bx:
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* - H7B0xB: Flash Bank 1 **only** with 128kiB of Flash total
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* - H7A3xG: Flash Bank 1 **only** for 1MiB total
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* - H7x3xI: Both banks, split at 1MiB for 2MiB total
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*
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* @param[in] bank one of the FLASH_BANK_* constants indicating which bank to erase
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* @param[in] operation_parallelism the write parallelism to use for the erase -
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* one of the PROGRAM_SIZE_* constants
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*/
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void flash_erase_bank(enum flash_bank bank, uint8_t operation_parallelism);
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/** Enable writing the Flash in a bank and set the operation parallelism */
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void flash_program_enable(enum flash_bank bank, uint8_t operation_parallelism);
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/** Disable writing the Flash in a bank*/
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void flash_program_disable(enum flash_bank bank);
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/** Program one u8 to Flash (forced) */
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bool flash_program_byte(uintptr_t address, uint8_t data);
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/** Program one u16 to Flash (forced) */
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bool flash_program_half_word(uintptr_t address, uint16_t data);
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/** Program one u32 to Flash (forced) */
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bool flash_program_word(uintptr_t address, uint32_t data);
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/** Program one u64 to Flash (forced) */
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bool flash_program_double_word(uintptr_t address, uint64_t data);
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/** Program a block of data to Flash (forced) */
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bool flash_program(uintptr_t address, const uint8_t *data, size_t len);
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/** Force the write operation - required to flush out a non-full block of data to the Flash
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*
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* NB: This must be called only *after* setting up the operation with the above functions.
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*/
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void flash_program_force(enum flash_bank bank);
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/** Unlock the Option Byte Access.
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* This enables write access to the option bytes. It is locked by default on
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* reset.
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*/
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void flash_unlock_option_bytes(void);
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/** Lock the Option Byte Access.
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* This disables write access to the option bytes.
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*/
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void flash_lock_option_bytes(void);
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/** Program the Option Bytes.
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* Write
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*/
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void flash_program_option_bytes(uint32_t data);
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END_DECLS
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/**@}*/
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#endif
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@@ -23,6 +23,7 @@
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#include <libopencm3/stm32/flash.h>
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#if !defined(STM32H7)
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void flash_prefetch_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_PRFTEN;
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@@ -32,6 +33,7 @@ void flash_prefetch_disable(void)
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{
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FLASH_ACR &= ~FLASH_ACR_PRFTEN;
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}
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#endif
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void flash_set_ws(uint32_t ws)
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{
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@@ -40,7 +40,7 @@ ARFLAGS = rcs
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OBJS += dac_common_all.o dac_common_v2.o
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OBJS += exti_common_all.o
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OBJS += fdcan.o fdcan_common.o
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OBJS += flash_common_all.o flash_common_f.o flash_common_f24.o
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OBJS += flash.o
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OBJS += fmc_common_f47.o
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OBJS += gpio_common_all.o gpio_common_f0234.o
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OBJS += pwr.o rcc.o
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334
lib/stm32/h7/flash.c
Normal file
334
lib/stm32/h7/flash.c
Normal file
@@ -0,0 +1,334 @@
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/** @addtogroup flash_file FLASH peripheral API
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* @ingroup peripheral_apis
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2024 Rachel Mant <git@dragonmux.network>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <string.h>
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#include <libopencm3/stm32/flash.h>
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#define REBASE(x) MMIO32((x) + (bank_base_address))
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#define MIN(x, y) ((x) < (y) ? (x) : (y))
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#define DBGMCU_IDCODE (DBGMCU_BASE + 0x000U)
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/** @brief Set the Program Parallelism Size
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*
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* Set the programming parallelism width. Note carefully the power supply voltage
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* restrictions under which the different word sizes may be used. See the
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* programming manual for more information.
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* @param[in] psize The programming word width one of: @ref flash_cr_program_width
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*/
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static inline void flash_set_program_size(const uintptr_t bank_base_address, const uint32_t psize)
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{
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REBASE(FLASH_CR) &= ~(FLASH_CR_PROGRAM_MASK << FLASH_CR_PROGRAM_SHIFT);
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REBASE(FLASH_CR) |= psize << FLASH_CR_PROGRAM_SHIFT;
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}
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/** @brief Translate a bank number to its FPEC base address */
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static inline uintptr_t flash_bank_address(const enum flash_bank bank)
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{
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switch (bank) {
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case FLASH_BANK_1:
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return FLASH_FPEC1_BASE;
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case FLASH_BANK_2:
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return FLASH_FPEC2_BASE;
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}
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/* We should never be able to reach this point */
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__builtin_unreachable();
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}
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static inline enum flash_bank flash_bank_from_address(const uintptr_t address)
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{
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/* Make it undefined behaviour to call this function with an address below the Flash range start */
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if (address < FLASH_BASE)
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__builtin_unreachable();
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/* Check if the addres falls in the first bank */
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if (address < FLASH_BASE + FLASH_BANK_MAX_SIZE)
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return FLASH_BANK_1;
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/* Check if the address falls in the second */
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if (address < FLASH_BASE + (FLASH_BANK_MAX_SIZE << 1U))
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return FLASH_BANK_2;
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/* Turn any other addresses passed in into UB too */
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__builtin_unreachable();
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}
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static inline enum device_variant mcu_variant(void)
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{
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/* Read the device DBGMCU ID code out */
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const uint32_t idcode = DBGMCU_IDCODE;
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/* Mask out and return the device ID component */
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return idcode & 0xfffU;
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}
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void flash_set_ws(const uint32_t wait_states)
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{
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/* Read the current ACR value and mask out the wait states component */
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const uint32_t reg32 = FLASH_ACR & ~(FLASH_ACR_LATENCY_MASK << FLASH_ACR_LATENCY_SHIFT);
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/* Write back the new value, with the new wait states shifted in to place */
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FLASH_ACR = reg32 | (wait_states << FLASH_ACR_LATENCY_SHIFT);
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}
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bool flash_is_busy(const enum flash_bank bank)
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{
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const uintptr_t bank_base_address = flash_bank_address(bank);
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/*
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* Read back the current status register value and check for there still
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* being items in the queue, and the EOP flag not yet being set.
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*/
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const uint32_t status = REBASE(FLASH_SR);
|
||||
return !(status & FLASH_SR_EOP) && (status & FLASH_SR_QW);
|
||||
}
|
||||
|
||||
void flash_clear_eop_flag(const enum flash_bank bank)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
/*
|
||||
* The H7 uses a special clear register for the control bits related
|
||||
* to errors and operation completion, which clears the *status* bits.
|
||||
* The status register is strictly read-only on this part.
|
||||
*/
|
||||
REBASE(FLASH_CCR) = FLASH_SR_EOP;
|
||||
}
|
||||
|
||||
void flash_clear_status_flags(const enum flash_bank bank)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
REBASE(FLASH_CCR) = FLASH_SR_ERROR_MASK | FLASH_SR_EOP;
|
||||
}
|
||||
|
||||
bool flash_wait_for_last_operation(const enum flash_bank bank)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
/* Wait in a busy loop while the controller says we're busy */
|
||||
while (flash_is_busy(bank))
|
||||
continue;
|
||||
/* Pull back if any errors occured and return accordingly */
|
||||
return !(REBASE(FLASH_SR) & FLASH_SR_ERROR_MASK);
|
||||
}
|
||||
|
||||
bool flash_is_locked(const enum flash_bank bank)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
return REBASE(FLASH_CR) & FLASH_CR_LOCK;
|
||||
}
|
||||
|
||||
void flash_unlock(const enum flash_bank bank)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
/* Authorize the FPEC access. */
|
||||
REBASE(FLASH_KEYR) = FLASH_KEYR_KEY1;
|
||||
REBASE(FLASH_KEYR) = FLASH_KEYR_KEY2;
|
||||
}
|
||||
|
||||
void flash_lock(const enum flash_bank bank)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
REBASE(FLASH_CR) |= FLASH_CR_LOCK;
|
||||
}
|
||||
|
||||
void flash_erase_sector(const enum flash_bank bank, const uint8_t sector, const uint8_t operation_parallelism)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
const enum device_variant variant = mcu_variant();
|
||||
/* Reset the bottom control register bits ready for the new operation */
|
||||
REBASE(FLASH_CR) &= ~FLASH_CR_OP_MASK;
|
||||
/* H7Bx does not have write parallelism bits */
|
||||
if (variant != STM32H7Bx)
|
||||
flash_set_program_size(bank_base_address, operation_parallelism);
|
||||
/*
|
||||
* The control register layout is dependant on the variant.
|
||||
* Set up the sector erase operation and then kick it off.
|
||||
*/
|
||||
switch (variant) {
|
||||
case STM32H7Bx:
|
||||
REBASE(FLASH_CR) |= FLASH_CR_SER | (sector << FLASH_CR_H7Bx_SNB_SHIFT);
|
||||
REBASE(FLASH_CR) |= FLASH_CR_H7Bx_STRT;
|
||||
break;
|
||||
default:
|
||||
REBASE(FLASH_CR) |= FLASH_CR_SER | (sector << FLASH_CR_SNB_SHIFT);
|
||||
REBASE(FLASH_CR) |= FLASH_CR_STRT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void flash_erase_bank(const enum flash_bank bank, const uint8_t operation_parallelism)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
const enum device_variant variant = mcu_variant();
|
||||
/* Reset the bottom control register bits ready for the new operation */
|
||||
REBASE(FLASH_CR) &= ~FLASH_CR_OP_MASK;
|
||||
/* H7Bx does not have write parallelism bits */
|
||||
if (variant != STM32H7Bx)
|
||||
flash_set_program_size(bank_base_address, operation_parallelism);
|
||||
/*
|
||||
* The control register layout is dependant on the variant.
|
||||
* Set up the bank erase operation and then kick it off.
|
||||
* NB: per §4.3.10 "Standard flash bank erase sequence" of RM0433 rev8, pg166
|
||||
* setting BER and start can be merged.
|
||||
*/
|
||||
switch (variant) {
|
||||
case STM32H7Bx:
|
||||
REBASE(FLASH_CR) |= FLASH_CR_BER | FLASH_CR_H7Bx_STRT;
|
||||
break;
|
||||
default:
|
||||
REBASE(FLASH_CR) |= FLASH_CR_BER | FLASH_CR_STRT;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void flash_program_enable(const enum flash_bank bank, const uint8_t operation_parallelism)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
const enum device_variant variant = mcu_variant();
|
||||
/* Reset the bottom control register bits ready for the new operation */
|
||||
REBASE(FLASH_CR) &= ~FLASH_CR_OP_MASK;
|
||||
/* H7Bx does not have write parallelism bits */
|
||||
if (variant != STM32H7Bx)
|
||||
flash_set_program_size(bank_base_address, operation_parallelism);
|
||||
REBASE(FLASH_CR) |= FLASH_CR_PG;
|
||||
}
|
||||
|
||||
void flash_program_disable(const enum flash_bank bank)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
REBASE(FLASH_CR) &= ~FLASH_CR_PG;
|
||||
}
|
||||
|
||||
bool flash_program_byte(const uintptr_t address, const uint8_t data)
|
||||
{
|
||||
const enum flash_bank bank = flash_bank_from_address(address);
|
||||
flash_program_enable(bank, FLASH_CR_PROGRAM_X8);
|
||||
MMIO8(address) = data;
|
||||
flash_program_force(bank);
|
||||
return flash_wait_for_last_operation(bank);
|
||||
}
|
||||
|
||||
bool flash_program_half_word(const uintptr_t address, const uint16_t data)
|
||||
{
|
||||
const enum flash_bank bank = flash_bank_from_address(address);
|
||||
flash_program_enable(bank, FLASH_CR_PROGRAM_X16);
|
||||
MMIO16(address) = data;
|
||||
flash_program_force(bank);
|
||||
return flash_wait_for_last_operation(bank);
|
||||
}
|
||||
|
||||
bool flash_program_word(const uintptr_t address, const uint32_t data)
|
||||
{
|
||||
const enum flash_bank bank = flash_bank_from_address(address);
|
||||
flash_program_enable(bank, FLASH_CR_PROGRAM_X32);
|
||||
MMIO32(address) = data;
|
||||
flash_program_force(bank);
|
||||
return flash_wait_for_last_operation(bank);
|
||||
}
|
||||
|
||||
bool flash_program_double_word(const uintptr_t address, const uint64_t data)
|
||||
{
|
||||
const enum flash_bank bank = flash_bank_from_address(address);
|
||||
flash_program_enable(bank, FLASH_CR_PROGRAM_X64);
|
||||
MMIO64(address) = data;
|
||||
flash_program_force(bank);
|
||||
return flash_wait_for_last_operation(bank);
|
||||
}
|
||||
|
||||
bool flash_program(const uintptr_t address, const uint8_t *const data, const size_t len)
|
||||
{
|
||||
/* Begin operations */
|
||||
const enum flash_bank bank = flash_bank_from_address(address);
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
const enum device_variant variant = mcu_variant();
|
||||
flash_program_enable(bank, FLASH_CR_PROGRAM_X64);
|
||||
/* If the address to write does not start on a write block boundary, write out what we have and force write it */
|
||||
size_t offset = address & FLASH_WRITE_BLOCK_MASK;
|
||||
if (offset != 0U) {
|
||||
/* Figure out the amount of data that needs written to complete the block */
|
||||
const size_t amount = MIN(len, FLASH_WRITE_BLOCK_SIZE - offset);
|
||||
memcpy((void *)address, data, amount);
|
||||
flash_program_force(bank);
|
||||
if (!flash_wait_for_last_operation(bank))
|
||||
return false;
|
||||
offset = amount;
|
||||
/* Having completed the forced write, reset the FW bit */
|
||||
switch (variant) {
|
||||
case STM32H7Bx:
|
||||
REBASE(FLASH_CR) &= FLASH_CR_H7Bx_FW;
|
||||
break;
|
||||
default:
|
||||
REBASE(FLASH_CR) &= FLASH_CR_FW;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* Now write out as many complete blocks as we have */
|
||||
for (; len - offset >= FLASH_WRITE_BLOCK_SIZE; offset += FLASH_WRITE_BLOCK_SIZE) {
|
||||
memcpy((void *)(address + offset), data + offset, FLASH_WRITE_BLOCK_SIZE);
|
||||
if (!flash_wait_for_last_operation(bank))
|
||||
return false;
|
||||
}
|
||||
/* Finally, figure out if we've got anything left to write, and flush that out too */
|
||||
const size_t amount = len - offset;
|
||||
if (amount != 0U) {
|
||||
memcpy((void *)(address + offset), data + offset, amount);
|
||||
flash_program_force(bank);
|
||||
if (!flash_wait_for_last_operation(bank))
|
||||
return false;
|
||||
/* Having completed the forced write, reset the FW bit */
|
||||
switch (variant) {
|
||||
case STM32H7Bx:
|
||||
REBASE(FLASH_CR) &= FLASH_CR_H7Bx_FW;
|
||||
break;
|
||||
default:
|
||||
REBASE(FLASH_CR) &= FLASH_CR_FW;
|
||||
break;
|
||||
}
|
||||
}
|
||||
/* We're done, clean up the enable bit and return success */
|
||||
flash_program_disable(bank);
|
||||
return true;
|
||||
}
|
||||
|
||||
void flash_program_force(const enum flash_bank bank)
|
||||
{
|
||||
const uintptr_t bank_base_address = flash_bank_address(bank);
|
||||
const enum device_variant variant = mcu_variant();
|
||||
/*
|
||||
* The control register layout is dependant on the variant.
|
||||
* Set the FW bit appropriately to force the write operation that's already been set up.
|
||||
*/
|
||||
switch (variant) {
|
||||
case STM32H7Bx:
|
||||
REBASE(FLASH_CR) |= FLASH_CR_H7Bx_FW;
|
||||
break;
|
||||
default:
|
||||
REBASE(FLASH_CR) |= FLASH_CR_FW;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void flash_unlock_option_bytes(void)
|
||||
{
|
||||
FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
|
||||
FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
|
||||
}
|
||||
|
||||
void flash_lock_option_bytes(void)
|
||||
{
|
||||
FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
|
||||
}
|
||||
@@ -189,13 +189,8 @@ void rcc_clock_setup_pll(const struct rcc_pll_config *config) {
|
||||
pwr_set_mode(config->power_mode, config->smps_level);
|
||||
pwr_set_vos_scale(config->voltage_scale);
|
||||
|
||||
/* Set flash waitstates. Enable flash prefetch if we have at least 1WS */
|
||||
/* Set flash waitstates. H7 doesn't support prefetch, so nothing to do WRT this. */
|
||||
flash_set_ws(config->flash_waitstates);
|
||||
if (config->flash_waitstates > FLASH_ACR_LATENCY_0WS) {
|
||||
flash_prefetch_enable();
|
||||
} else {
|
||||
flash_prefetch_disable();
|
||||
}
|
||||
|
||||
/* User has specified an external oscillator, make sure we turn it on. */
|
||||
if (config->hse_frequency > 0) {
|
||||
|
||||
Reference in New Issue
Block a user