NVIC_Set_Interrupt_Priority: change to use 4-bit fields.
(viz STM32F10xxx Cortex-M3 programming manual PM0056 and Cortex-M3-Generic-User-Guide.pdf) Doxygen commentary added
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@@ -27,6 +27,10 @@
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*/
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/* User Interrupts */
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/** @defgroup nvic_stn32f1_userint STM32F1xx User Interrupts
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@ingroup STM32F_nvic_defines
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@{*/
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#define NVIC_WWDG_IRQ 0
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#define NVIC_PVD_IRQ 1
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#define NVIC_TAMPER_IRQ 2
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@@ -95,5 +99,6 @@
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#define NVIC_CAN2_RX1_IRQ 65
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#define NVIC_CAN2_SCE_IRQ 66
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#define NVIC_OTG_FS_IRQ 67
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/*@}*/
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#endif
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@@ -1,3 +1,26 @@
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/** @file
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@ingroup STM32F
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@brief <b>libopencm3 STM32F Nested Vectored Interrupt Controller</b>
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@version 1.0.0
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@author @htmlonly © @endhtmlonly 2010 Piotr Esden-Tempski <piotr@esden.net>
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@date 8 July 2012
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LGPL License Terms @ref lgpl_license
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*/
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/** @defgroup STM32F_nvic_defines
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@brief Defined Constants and Types for the STM32F Nested Vectored Interrupt Controller
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@ingroup STM32F_defines
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LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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@@ -65,6 +88,11 @@
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/* --- IRQ channel numbers-------------------------------------------------- */
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/* Cortex M3 System Interrupts */
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/** @defgroup nvic_sysint Cortex M3 System Interrupts
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@ingroup STM32F_nvic_defines
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IRQ numbers -3 and -6 to -9 are reserved
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@{*/
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#define NVIC_NMI_IRQ -14
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#define NVIC_HARD_FAULT_IRQ -13
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#define NVIC_MEM_MANAGE_IRQ -12
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@@ -76,9 +104,10 @@
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/* irq number -3 reserved */
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#define NVIC_PENDSV_IRQ -2
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#define NVIC_SYSTICK_IRQ -1
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/*@}*/
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/* Note: User interrupts are family specific and are defined in a familiy
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/* Note: User interrupts are family specific and are defined in a family
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* specific header file in the corresponding subfolder.
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*/
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@@ -103,6 +132,6 @@ void nvic_clear_pending_irq(u8 irqn);
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u8 nvic_get_active_irq(u8 irqn);
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u8 nvic_get_irq_enabled(u8 irqn);
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void nvic_set_priority(u8 irqn, u8 priority);
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void nvic_generate_software_interrupt(u8 irqn);
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void nvic_generate_software_interrupt(u16 irqn);
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#endif
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