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stm32: rcc: Standardize prescaler define names

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We did have
* _HPRE_SYSCLK_DIVN (3 parts)
* _HPRE_DIVN (5 parts)
* _HPRE_DIV_N (4 parts)

Unify all on _HPRE_DIVN.  Provide deprecated definitions to not break
everything at once.

Also, standardize on "NODIV" instead of DIVNONE.
This commit is contained in:
Karl Palsson
2020-10-18 14:48:45 +00:00
parent 43b3fa5ddc
commit c7d7a18dd7
8 changed files with 386 additions and 186 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/libopencm3/gd32/f1x0/rcc.h
+57 -29
View File
@@ -174,44 +174,39 @@
/** @defgroup rcc_cfgr_adcpre ADCPRE: ADC prescaler
* @{
*/
#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
#define RCC_CFGR_ADCPRE_DIV2 0x0
#define RCC_CFGR_ADCPRE_DIV4 0x1
#define RCC_CFGR_ADCPRE_DIV6 0x2
#define RCC_CFGR_ADCPRE_DIV8 0x3
/**@}*/
/** @defgroup rcc_cfgr_apb2pre PPRE2: APB high-speed prescaler (APB2)
#define RCC_CFGR_PPRE2_SHIFT 11
#define RCC_CFGR_PPRE2_MASK 0x7
#define RCC_CFGR_PPRE1_SHIFT 8
#define RCC_CFGR_PPRE1_MASK 0x7
/** @defgroup rcc_cfgr_apbxpre RCC_CFGR APBx prescale factors
* These can be used for both APB1 and APB2 prescaling
* @{
*/
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
/**@}*/
/** @defgroup rcc_cfgr_apb1pre PPRE1: APB low-speed prescaler (APB1)
* @{
*/
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
#define RCC_CFGR_PPRE_NODIV 0x0
#define RCC_CFGR_PPRE_DIV2 0x4
#define RCC_CFGR_PPRE_DIV4 0x5
#define RCC_CFGR_PPRE_DIV8 0x6
#define RCC_CFGR_PPRE_DIV16 0x7
/**@}*/
/** @defgroup rcc_cfgr_ahbpre HPRE: AHB prescaler
* @{
*/
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
#define RCC_CFGR_HPRE_NODIV 0x0
#define RCC_CFGR_HPRE_DIV2 0x8
#define RCC_CFGR_HPRE_DIV4 0x9
#define RCC_CFGR_HPRE_DIV8 0xa
#define RCC_CFGR_HPRE_DIV16 0xb
#define RCC_CFGR_HPRE_DIV64 0xc
#define RCC_CFGR_HPRE_DIV128 0xd
#define RCC_CFGR_HPRE_DIV256 0xe
#define RCC_CFGR_HPRE_DIV512 0xf
/**@}*/
/* SWS: System clock switch status */
@@ -227,6 +222,39 @@
#define RCC_CFGR_SW_SYSCLKSEL_PLLCLK 0x2
/**@}*/
/** Older compatible definitions to ease migration
* @defgroup rcc_cfgr_deprecated RCC_CFGR Deprecated dividers
* @deprecated Use _CFGR_xPRE_DIVn form instead, across all families
* @{
*/
#define RCC_CFGR_ADCPRE_PCLK2_DIV2 0x0
#define RCC_CFGR_ADCPRE_PCLK2_DIV4 0x1
#define RCC_CFGR_ADCPRE_PCLK2_DIV6 0x2
#define RCC_CFGR_ADCPRE_PCLK2_DIV8 0x3
#define RCC_CFGR_PPRE2_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE2_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE2_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE2_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE2_HCLK_DIV16 0x7
#define RCC_CFGR_PPRE1_HCLK_NODIV 0x0
#define RCC_CFGR_PPRE1_HCLK_DIV2 0x4
#define RCC_CFGR_PPRE1_HCLK_DIV4 0x5
#define RCC_CFGR_PPRE1_HCLK_DIV8 0x6
#define RCC_CFGR_PPRE1_HCLK_DIV16 0x7
#define RCC_CFGR_HPRE_SYSCLK_NODIV 0x0
#define RCC_CFGR_HPRE_SYSCLK_DIV2 0x8
#define RCC_CFGR_HPRE_SYSCLK_DIV4 0x9
#define RCC_CFGR_HPRE_SYSCLK_DIV8 0xa
#define RCC_CFGR_HPRE_SYSCLK_DIV16 0xb
#define RCC_CFGR_HPRE_SYSCLK_DIV64 0xc
#define RCC_CFGR_HPRE_SYSCLK_DIV128 0xd
#define RCC_CFGR_HPRE_SYSCLK_DIV256 0xe
#define RCC_CFGR_HPRE_SYSCLK_DIV512 0xf
/**@}*/
/* --- RCC_CIR values ------------------------------------------------------ */
/* Clock security system interrupt clear bit */