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Surround all macro parameters with ()

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All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.

Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.

Fixes github issue #321
This commit is contained in:
Karl Palsson
2015-10-14 21:52:54 +00:00
parent c899273c62
commit c72f3d588a
50 changed files with 559 additions and 559 deletions
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38
include/libopencm3/stm32/l1/adc.h
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@@ -40,52 +40,52 @@ LGPL License Terms @ref lgpl_license
#define ADC_MAX_CHANNELS 32
/* ADC sample time register 3 (ADC_SMPR3) */
#define ADC_SMPR3(block) MMIO32(block + 0x14)
#define ADC_SMPR3(block) MMIO32((block) + 0x14)
#define ADC1_SMPR3 ADC_SMPR3(ADC1)
/* ADC injected channel data offset register x (ADC_JOFRx) (x=1..4) */
#define ADC_JOFR1(block) MMIO32(block + 0x18)
#define ADC_JOFR2(block) MMIO32(block + 0x1c)
#define ADC_JOFR3(block) MMIO32(block + 0x20)
#define ADC_JOFR4(block) MMIO32(block + 0x24)
#define ADC_JOFR1(block) MMIO32((block) + 0x18)
#define ADC_JOFR2(block) MMIO32((block) + 0x1c)
#define ADC_JOFR3(block) MMIO32((block) + 0x20)
#define ADC_JOFR4(block) MMIO32((block) + 0x24)
/* ADC watchdog high threshold register (ADC_HTR) */
#define ADC_HTR(block) MMIO32(block + 0x28)
#define ADC_HTR(block) MMIO32((block) + 0x28)
/* ADC watchdog low threshold register (ADC_LTR) */
#define ADC_LTR(block) MMIO32(block + 0x2c)
#define ADC_LTR(block) MMIO32((block) + 0x2c)
/* ADC regular sequence register 1 (ADC_SQR1) */
#define ADC_SQR1(block) MMIO32(block + 0x30)
#define ADC_SQR1(block) MMIO32((block) + 0x30)
/* ADC regular sequence register 2 (ADC_SQR2) */
#define ADC_SQR2(block) MMIO32(block + 0x34)
#define ADC_SQR2(block) MMIO32((block) + 0x34)
/* ADC regular sequence register 3 (ADC_SQR3) */
#define ADC_SQR3(block) MMIO32(block + 0x38)
#define ADC_SQR3(block) MMIO32((block) + 0x38)
/* ADC regular sequence register 4 (ADC_SQR4) */
#define ADC_SQR4(block) MMIO32(block + 0x3c)
#define ADC_SQR4(block) MMIO32((block) + 0x3c)
#define ADC1_SQR4 ADC_SQR4(ADC1)
/* ADC regular sequence register 5 (ADC_SQR5) */
#define ADC_SQR5(block) MMIO32(block + 0x40)
#define ADC_SQR5(block) MMIO32((block) + 0x40)
#define ADC1_SQR5 ADC_SQR5(ADC1)
/* ADC injected sequence register (ADC_JSQR) */
#define ADC_JSQR(block) MMIO32(block + 0x44)
#define ADC_JSQR(block) MMIO32((block) + 0x44)
/* ADC injected data register x (ADC_JDRx) (x=1..4) */
#define ADC_JDR1(block) MMIO32(block + 0x48)
#define ADC_JDR2(block) MMIO32(block + 0x4c)
#define ADC_JDR3(block) MMIO32(block + 0x50)
#define ADC_JDR4(block) MMIO32(block + 0x54)
#define ADC_JDR1(block) MMIO32((block) + 0x48)
#define ADC_JDR2(block) MMIO32((block) + 0x4c)
#define ADC_JDR3(block) MMIO32((block) + 0x50)
#define ADC_JDR4(block) MMIO32((block) + 0x54)
/* ADC regular data register (ADC_DR) */
#define ADC_DR(block) MMIO32(block + 0x58)
#define ADC_DR(block) MMIO32((block) + 0x58)
/* ADC sample time register 0 (ADC_SMPR0) (high/med+ only) */
#define ADC_SMPR0(block) MMIO32(block + 0x5c)
#define ADC_SMPR0(block) MMIO32((block) + 0x5c)
#define ADC1_SMPR0 ADC_SMPR0(ADC1)
#define ADC_CSR MMIO32(ADC1 + 0x300)