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Surround all macro parameters with ()

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All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.

Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.

Fixes github issue #321
This commit is contained in:
Karl Palsson
2015-10-14 21:52:54 +00:00
parent c899273c62
commit c72f3d588a
50 changed files with 559 additions and 559 deletions
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84
include/libopencm3/stm32/can.h
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@@ -54,23 +54,23 @@ LGPL License Terms @ref lgpl_license
/* --- CAN registers ------------------------------------------------------- */
/* CAN master control register (CAN_MCR) */
#define CAN_MCR(can_base) MMIO32(can_base + 0x000)
#define CAN_MCR(can_base) MMIO32((can_base) + 0x000)
/* CAN master status register (CAN_MSR) */
#define CAN_MSR(can_base) MMIO32(can_base + 0x004)
#define CAN_MSR(can_base) MMIO32((can_base) + 0x004)
/* CAN transmit status register (CAN_TSR) */
#define CAN_TSR(can_base) MMIO32(can_base + 0x008)
#define CAN_TSR(can_base) MMIO32((can_base) + 0x008)
/* CAN receive FIFO 0 register (CAN_RF0R) */
#define CAN_RF0R(can_base) MMIO32(can_base + 0x00C)
#define CAN_RF0R(can_base) MMIO32((can_base) + 0x00C)
/* CAN receive FIFO 1 register (CAN_RF1R) */
#define CAN_RF1R(can_base) MMIO32(can_base + 0x010)
#define CAN_RF1R(can_base) MMIO32((can_base) + 0x010)
/* CAN interrupt enable register (CAN_IER) */
#define CAN_IER(can_base) MMIO32(can_base + 0x014)
#define CAN_IER(can_base) MMIO32((can_base) + 0x014)
/* CAN error status register (CAN_ESR) */
#define CAN_ESR(can_base) MMIO32(can_base + 0x018)
#define CAN_ESR(can_base) MMIO32((can_base) + 0x018)
/* CAN bit timing register (CAN_BTR) */
#define CAN_BTR(can_base) MMIO32(can_base + 0x01C)
#define CAN_BTR(can_base) MMIO32((can_base) + 0x01C)
/* Registers in the offset range 0x020 to 0x17F are reserved. */
@@ -84,71 +84,71 @@ LGPL License Terms @ref lgpl_license
#define CAN_FIFO1 0x1C0
/* CAN TX mailbox identifier register (CAN_TIxR) */
#define CAN_TIxR(can_base, mbox) MMIO32(can_base + mbox + 0x0)
#define CAN_TIxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x0)
#define CAN_TI0R(can_base) CAN_TIxR(can_base, CAN_MBOX0)
#define CAN_TI1R(can_base) CAN_TIxR(can_base, CAN_MBOX1)
#define CAN_TI2R(can_base) CAN_TIxR(can_base, CAN_MBOX2)
/* CAN mailbox data length control and time stamp register (CAN_TDTxR) */
#define CAN_TDTxR(can_base, mbox) MMIO32(can_base + mbox + 0x4)
#define CAN_TDT0R(can_base) CAN_TDTxR(can_base, CAN_MBOX0)
#define CAN_TDT1R(can_base) CAN_TDTxR(can_base, CAN_MBOX1)
#define CAN_TDT2R(can_base) CAN_TDTxR(can_base, CAN_MBOX2)
#define CAN_TDTxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x4)
#define CAN_TDT0R(can_base) CAN_TDTxR((can_base), CAN_MBOX0)
#define CAN_TDT1R(can_base) CAN_TDTxR((can_base), CAN_MBOX1)
#define CAN_TDT2R(can_base) CAN_TDTxR((can_base), CAN_MBOX2)
/* CAN mailbox data low register (CAN_TDLxR) */
#define CAN_TDLxR(can_base, mbox) MMIO32(can_base + mbox + 0x8)
#define CAN_TDL0R(can_base) CAN_TDLxR(can_base, CAN_MBOX0)
#define CAN_TDL1R(can_base) CAN_TDLxR(can_base, CAN_MBOX1)
#define CAN_TDL2R(can_base) CAN_TDLxR(can_base, CAN_MBOX2)
#define CAN_TDLxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0x8)
#define CAN_TDL0R(can_base) CAN_TDLxR((can_base), CAN_MBOX0)
#define CAN_TDL1R(can_base) CAN_TDLxR((can_base), CAN_MBOX1)
#define CAN_TDL2R(can_base) CAN_TDLxR((can_base), CAN_MBOX2)
/* CAN mailbox data high register (CAN_TDHxR) */
#define CAN_TDHxR(can_base, mbox) MMIO32(can_base + mbox + 0xC)
#define CAN_TDH0R(can_base) CAN_TDHxR(can_base, CAN_MBOX0)
#define CAN_TDH1R(can_base) CAN_TDHxR(can_base, CAN_MBOX1)
#define CAN_TDH2R(can_base) CAN_TDHxR(can_base, CAN_MBOX2)
#define CAN_TDHxR(can_base, mbox) MMIO32((can_base) + (mbox) + 0xC)
#define CAN_TDH0R(can_base) CAN_TDHxR((can_base), CAN_MBOX0)
#define CAN_TDH1R(can_base) CAN_TDHxR((can_base), CAN_MBOX1)
#define CAN_TDH2R(can_base) CAN_TDHxR((can_base), CAN_MBOX2)
/* CAN RX FIFO identifier register (CAN_RIxR) */
#define CAN_RIxR(can_base, fifo) MMIO32(can_base + fifo + 0x0)
#define CAN_RI0R(can_base) CAN_RIxR(can_base, CAN_FIFO0)
#define CAN_RI1R(can_base) CAN_RIxR(can_base, CAN_FIFO1)
#define CAN_RIxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x0)
#define CAN_RI0R(can_base) CAN_RIxR((can_base), CAN_FIFO0)
#define CAN_RI1R(can_base) CAN_RIxR((can_base), CAN_FIFO1)
/* CAN RX FIFO mailbox data length control & time stamp register (CAN_RDTxR) */
#define CAN_RDTxR(can_base, fifo) MMIO32(can_base + fifo + 0x4)
#define CAN_RDT0R(can_base) CAN_RDTxR(can_base, CAN_FIFO0)
#define CAN_RDT1R(can_base) CAN_RDTxR(can_base, CAN_FIFO1)
#define CAN_RDTxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x4)
#define CAN_RDT0R(can_base) CAN_RDTxR((can_base), CAN_FIFO0)
#define CAN_RDT1R(can_base) CAN_RDTxR((can_base), CAN_FIFO1)
/* CAN RX FIFO mailbox data low register (CAN_RDLxR) */
#define CAN_RDLxR(can_base, fifo) MMIO32(can_base + fifo + 0x8)
#define CAN_RDL0R(can_base) CAN_RDLxR(can_base, CAN_FIFO0)
#define CAN_RDL1R(can_base) CAN_RDLxR(can_base, CAN_FIFO1)
#define CAN_RDLxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0x8)
#define CAN_RDL0R(can_base) CAN_RDLxR((can_base), CAN_FIFO0)
#define CAN_RDL1R(can_base) CAN_RDLxR((can_base), CAN_FIFO1)
/* CAN RX FIFO mailbox data high register (CAN_RDHxR) */
#define CAN_RDHxR(can_base, fifo) MMIO32(can_base + fifo + 0xC)
#define CAN_RDH0R(can_base) CAN_RDHxR(can_base, CAN_FIFO0)
#define CAN_RDH1R(can_base) CAN_RDHxR(can_base, CAN_FIFO1)
#define CAN_RDHxR(can_base, fifo) MMIO32((can_base) + (fifo) + 0xC)
#define CAN_RDH0R(can_base) CAN_RDHxR((can_base), CAN_FIFO0)
#define CAN_RDH1R(can_base) CAN_RDHxR((can_base), CAN_FIFO1)
/* --- CAN filter registers ------------------------------------------------ */
/* CAN filter master register (CAN_FMR) */
#define CAN_FMR(can_base) MMIO32(can_base + 0x200)
#define CAN_FMR(can_base) MMIO32((can_base) + 0x200)
/* CAN filter mode register (CAN_FM1R) */
#define CAN_FM1R(can_base) MMIO32(can_base + 0x204)
#define CAN_FM1R(can_base) MMIO32((can_base) + 0x204)
/* Register offset 0x208 is reserved. */
/* CAN filter scale register (CAN_FS1R) */
#define CAN_FS1R(can_base) MMIO32(can_base + 0x20C)
#define CAN_FS1R(can_base) MMIO32((can_base) + 0x20C)
/* Register offset 0x210 is reserved. */
/* CAN filter FIFO assignement register (CAN_FFA1R) */
#define CAN_FFA1R(can_base) MMIO32(can_base + 0x214)
#define CAN_FFA1R(can_base) MMIO32((can_base) + 0x214)
/* Register offset 0x218 is reserved. */
/* CAN filter activation register (CAN_FA1R) */
#define CAN_FA1R(can_base) MMIO32(can_base + 0x21C)
#define CAN_FA1R(can_base) MMIO32((can_base) + 0x21C)
/* Register offset 0x220 is reserved. */
@@ -159,10 +159,10 @@ LGPL License Terms @ref lgpl_license
* Connectivity line devices have 28 banks so the bank ID spans 0..27
* all other devices have 14 banks so the bank ID spans 0..13.
*/
#define CAN_FiR1(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32(can_base + 0x240 + \
(bank * 0x8) + 0x4)
#define CAN_FiR1(can_base, bank) MMIO32((can_base) + 0x240 + \
((bank) * 0x8) + 0x0)
#define CAN_FiR2(can_base, bank) MMIO32((can_base) + 0x240 + \
((bank) * 0x8) + 0x4)
/* --- CAN_MCR values ------------------------------------------------------ */