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Surround all macro parameters with ()

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All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.

Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.

Fixes github issue #321
This commit is contained in:
Karl Palsson
2015-10-14 21:52:54 +00:00
parent c899273c62
commit c72f3d588a
50 changed files with 559 additions and 559 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
include/libopencm3/lpc43xx/adc.h
View File

@@ -49,62 +49,62 @@ LGPL License Terms @ref lgpl_license
/* --- ADC registers ------------------------------------------------------- */
/* A/D Control Register */
#define ADC_CR(port) MMIO32(port + 0x000)
#define ADC_CR(port) MMIO32((port) + 0x000)
#define ADC0_CR ADC_CR(ADC0)
#define ADC1_CR ADC_CR(ADC1)
/* A/D Global Data Register */
#define ADC_GDR(port) MMIO32(port + 0x004)
#define ADC_GDR(port) MMIO32((port) + 0x004)
#define ADC0_GDR ADC_GDR(ADC0)
#define ADC1_GDR ADC_GDR(ADC1)
/* A/D Interrupt Enable Register */
#define ADC_INTEN(port) MMIO32(port + 0x00C)
#define ADC_INTEN(port) MMIO32((port) + 0x00C)
#define ADC0_INTEN ADC_INTEN(ADC0)
#define ADC1_INTEN ADC_INTEN(ADC1)
/* A/D Channel 0 Data Register */
#define ADC_DR0(port) MMIO32(port + 0x010)
#define ADC_DR0(port) MMIO32((port) + 0x010)
#define ADC0_DR0 ADC_DR0(ADC0)
#define ADC1_DR0 ADC_DR0(ADC1)
/* A/D Channel 1 Data Register */
#define ADC_DR1(port) MMIO32(port + 0x014)
#define ADC_DR1(port) MMIO32((port) + 0x014)
#define ADC0_DR1 ADC_DR1(ADC0)
#define ADC1_DR1 ADC_DR1(ADC1)
/* A/D Channel 2 Data Register */
#define ADC_DR2(port) MMIO32(port + 0x018)
#define ADC_DR2(port) MMIO32((port) + 0x018)
#define ADC0_DR2 ADC_DR2(ADC0)
#define ADC1_DR2 ADC_DR2(ADC1)
/* A/D Channel 3 Data Register */
#define ADC_DR3(port) MMIO32(port + 0x01C)
#define ADC_DR3(port) MMIO32((port) + 0x01C)
#define ADC0_DR3 ADC_DR3(ADC0)
#define ADC1_DR3 ADC_DR3(ADC1)
/* A/D Channel 4 Data Register */
#define ADC_DR4(port) MMIO32(port + 0x020)
#define ADC_DR4(port) MMIO32((port) + 0x020)
#define ADC0_DR4 ADC_DR4(ADC0)
#define ADC1_DR4 ADC_DR4(ADC1)
/* A/D Channel 5 Data Register */
#define ADC_DR5(port) MMIO32(port + 0x024)
#define ADC_DR5(port) MMIO32((port) + 0x024)
#define ADC0_DR5 ADC_DR5(ADC0)
#define ADC1_DR5 ADC_DR5(ADC1)
/* A/D Channel 6 Data Register */
#define ADC_DR6(port) MMIO32(port + 0x028)
#define ADC_DR6(port) MMIO32((port) + 0x028)
#define ADC0_DR6 ADC_DR6(ADC0)
#define ADC1_DR6 ADC_DR6(ADC1)
/* A/D Channel 7 Data Register */
#define ADC_DR7(port) MMIO32(port + 0x02C)
#define ADC_DR7(port) MMIO32((port) + 0x02C)
#define ADC0_DR7 ADC_DR7(ADC0)
#define ADC1_DR7 ADC_DR7(ADC1)
/* A/D Status Register */
#define ADC_STAT(port) MMIO32(port + 0x030)
#define ADC_STAT(port) MMIO32((port) + 0x030)
#define ADC0_STAT ADC_STAT(ADC0)
#define ADC1_STAT ADC_STAT(ADC1)

14
include/libopencm3/lpc43xx/gpio.h
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@@ -693,7 +693,7 @@ LGPL License Terms @ref lgpl_license
#define GPIO_W255 (GPIO_PORT_BASE + 0x13FC)
/* GPIO data direction register (GPIOn_DIR) */
#define GPIO_DIR(port) MMIO32(port + 0x00)
#define GPIO_DIR(port) MMIO32((port) + 0x00)
#define GPIO0_DIR GPIO_DIR(GPIO0)
#define GPIO1_DIR GPIO_DIR(GPIO1)
#define GPIO2_DIR GPIO_DIR(GPIO2)
@@ -704,7 +704,7 @@ LGPL License Terms @ref lgpl_license
#define GPIO7_DIR GPIO_DIR(GPIO7)
/* GPIO fast mask register (GPIOn_MASK) */
#define GPIO_MASK(port) MMIO32(port + 0x80)
#define GPIO_MASK(port) MMIO32((port) + 0x80)
#define GPIO0_MASK GPIO_MASK(GPIO0)
#define GPIO1_MASK GPIO_MASK(GPIO1)
#define GPIO2_MASK GPIO_MASK(GPIO2)
@@ -715,7 +715,7 @@ LGPL License Terms @ref lgpl_license
#define GPIO7_MASK GPIO_MASK(GPIO7)
/* GPIO port pin value register (GPIOn_PIN) */
#define GPIO_PIN(port) MMIO32(port + 0x100)
#define GPIO_PIN(port) MMIO32((port) + 0x100)
#define GPIO0_PIN GPIO_PIN(GPIO0)
#define GPIO1_PIN GPIO_PIN(GPIO1)
#define GPIO2_PIN GPIO_PIN(GPIO2)
@@ -726,7 +726,7 @@ LGPL License Terms @ref lgpl_license
#define GPIO7_PIN GPIO_PIN(GPIO7)
/* GPIO port masked pin value register (GPIOn_MPIN) */
#define GPIO_MPIN(port) MMIO32(port + 0x180)
#define GPIO_MPIN(port) MMIO32((port) + 0x180)
#define GPIO0_MPIN GPIO_MPIN(GPIO0)
#define GPIO1_MPIN GPIO_MPIN(GPIO1)
#define GPIO2_MPIN GPIO_MPIN(GPIO2)
@@ -737,7 +737,7 @@ LGPL License Terms @ref lgpl_license
#define GPIO7_MPIN GPIO_MPIN(GPIO7)
/* GPIO port output set register (GPIOn_SET) */
#define GPIO_SET(port) MMIO32(port + 0x200)
#define GPIO_SET(port) MMIO32((port) + 0x200)
#define GPIO0_SET GPIO_SET(GPIO0)
#define GPIO1_SET GPIO_SET(GPIO1)
#define GPIO2_SET GPIO_SET(GPIO2)
@@ -748,7 +748,7 @@ LGPL License Terms @ref lgpl_license
#define GPIO7_SET GPIO_SET(GPIO7)
/* GPIO port output clear register (GPIOn_CLR) */
#define GPIO_CLR(port) MMIO32(port + 0x280)
#define GPIO_CLR(port) MMIO32((port) + 0x280)
#define GPIO0_CLR GPIO_CLR(GPIO0)
#define GPIO1_CLR GPIO_CLR(GPIO1)
#define GPIO2_CLR GPIO_CLR(GPIO2)
@@ -759,7 +759,7 @@ LGPL License Terms @ref lgpl_license
#define GPIO7_CLR GPIO_CLR(GPIO7)
/* GPIO port toggle register (GPIOn_NOT) */
#define GPIO_NOT(port) MMIO32(port + 0x300)
#define GPIO_NOT(port) MMIO32((port) + 0x300)
#define GPIO0_NOT GPIO_NOT(GPIO0)
#define GPIO1_NOT GPIO_NOT(GPIO1)
#define GPIO2_NOT GPIO_NOT(GPIO2)

32
include/libopencm3/lpc43xx/i2c.h
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@@ -48,82 +48,82 @@ LGPL License Terms @ref lgpl_license
/* --- I2C registers ------------------------------------------------------- */
/* I2C Control Set Register */
#define I2C_CONSET(port) MMIO32(port + 0x000)
#define I2C_CONSET(port) MMIO32((port) + 0x000)
#define I2C0_CONSET I2C_CONSET(I2C0)
#define I2C1_CONSET I2C_CONSET(I2C1)
/* I2C Status Register */
#define I2C_STAT(port) MMIO32(port + 0x004)
#define I2C_STAT(port) MMIO32((port) + 0x004)
#define I2C0_STAT I2C_STAT(I2C0)
#define I2C1_STAT I2C_STAT(I2C1)
/* I2C Data Register */
#define I2C_DAT(port) MMIO32(port + 0x008)
#define I2C_DAT(port) MMIO32((port) + 0x008)
#define I2C0_DAT I2C_DAT(I2C0)
#define I2C1_DAT I2C_DAT(I2C1)
/* I2C Slave Address Register 0 */
#define I2C_ADR0(port) MMIO32(port + 0x00C)
#define I2C_ADR0(port) MMIO32((port) + 0x00C)
#define I2C0_ADR0 I2C_ADR0(I2C0)
#define I2C1_ADR0 I2C_ADR0(I2C1)
/* SCH Duty Cycle Register High Half Word */
#define I2C_SCLH(port) MMIO32(port + 0x010)
#define I2C_SCLH(port) MMIO32((port) + 0x010)
#define I2C0_SCLH I2C_SCLH(I2C0)
#define I2C1_SCLH I2C_SCLH(I2C1)
/* SCL Duty Cycle Register Low Half Word */
#define I2C_SCLL(port) MMIO32(port + 0x014)
#define I2C_SCLL(port) MMIO32((port) + 0x014)
#define I2C0_SCLL I2C_SCLL(I2C0)
#define I2C1_SCLL I2C_SCLL(I2C1)
/* I2C Control Clear Register */
#define I2C_CONCLR(port) MMIO32(port + 0x018)
#define I2C_CONCLR(port) MMIO32((port) + 0x018)
#define I2C0_CONCLR I2C_CONCLR(I2C0)
#define I2C1_CONCLR I2C_CONCLR(I2C1)
/* Monitor mode control register */
#define I2C_MMCTRL(port) MMIO32(port + 0x01C)
#define I2C_MMCTRL(port) MMIO32((port) + 0x01C)
#define I2C0_MMCTRL I2C_MMCTRL(I2C0)
#define I2C1_MMCTRL I2C_MMCTRL(I2C1)
/* I2C Slave Address Register 1 */
#define I2C_ADR1(port) MMIO32(port + 0x020)
#define I2C_ADR1(port) MMIO32((port) + 0x020)
#define I2C0_ADR1 I2C_ADR1(I2C0)
#define I2C1_ADR1 I2C_ADR1(I2C1)
/* I2C Slave Address Register 2 */
#define I2C_ADR2(port) MMIO32(port + 0x024)
#define I2C_ADR2(port) MMIO32((port) + 0x024)
#define I2C0_ADR2 I2C_ADR2(I2C0)
#define I2C1_ADR2 I2C_ADR2(I2C1)
/* I2C Slave Address Register 3 */
#define I2C_ADR3(port) MMIO32(port + 0x028)
#define I2C_ADR3(port) MMIO32((port) + 0x028)
#define I2C0_ADR3 I2C_ADR3(I2C0)
#define I2C1_ADR3 I2C_ADR3(I2C1)
/* Data buffer register */
#define I2C_DATA_BUFFER(port) MMIO32(port + 0x02C)
#define I2C_DATA_BUFFER(port) MMIO32((port) + 0x02C)
#define I2C0_DATA_BUFFER I2C_DATA_BUFFER(I2C0)
#define I2C1_DATA_BUFFER I2C_DATA_BUFFER(I2C1)
/* I2C Slave address mask register 0 */
#define I2C_MASK0(port) MMIO32(port + 0x030)
#define I2C_MASK0(port) MMIO32((port) + 0x030)
#define I2C0_MASK0 I2C_MASK0(I2C0)
#define I2C1_MASK0 I2C_MASK0(I2C1)
/* I2C Slave address mask register 1 */
#define I2C_MASK1(port) MMIO32(port + 0x034)
#define I2C_MASK1(port) MMIO32((port) + 0x034)
#define I2C0_MASK1 I2C_MASK1(I2C0)
#define I2C1_MASK1 I2C_MASK1(I2C1)
/* I2C Slave address mask register 2 */
#define I2C_MASK2(port) MMIO32(port + 0x038)
#define I2C_MASK2(port) MMIO32((port) + 0x038)
#define I2C0_MASK2 I2C_MASK2(I2C0)
#define I2C1_MASK2 I2C_MASK2(I2C1)
/* I2C Slave address mask register 3 */
#define I2C_MASK3(port) MMIO32(port + 0x03C)
#define I2C_MASK3(port) MMIO32((port) + 0x03C)
#define I2C0_MASK3 I2C_MASK3(I2C0)
#define I2C1_MASK3 I2C_MASK3(I2C1)

28
include/libopencm3/lpc43xx/i2s.h
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@@ -48,72 +48,72 @@ LGPL License Terms @ref lgpl_license
/* --- I2S registers ------------------------------------------------------- */
/* I2S Digital Audio Output Register */
#define I2S_DAO(port) MMIO32(port + 0x000)
#define I2S_DAO(port) MMIO32((port) + 0x000)
#define I2S0_DAO I2S_DAO(I2S0)
#define I2S1_DAO I2S_DAO(I2S1)
/* I2S Digital Audio Input Register */
#define I2S_DAI(port) MMIO32(port + 0x004)
#define I2S_DAI(port) MMIO32((port) + 0x004)
#define I2S0_DAI I2S_DAI(I2S0)
#define I2S1_DAI I2S_DAI(I2S1)
/* I2S Transmit FIFO */
#define I2S_TXFIFO(port) MMIO32(port + 0x008)
#define I2S_TXFIFO(port) MMIO32((port) + 0x008)
#define I2S0_TXFIFO I2S_TXFIFO(I2S0)
#define I2S1_TXFIFO I2S_TXFIFO(I2S1)
/* I2S Receive FIFO */
#define I2S_RXFIFO(port) MMIO32(port + 0x00C)
#define I2S_RXFIFO(port) MMIO32((port) + 0x00C)
#define I2S0_RXFIFO I2S_RXFIFO(I2S0)
#define I2S1_RXFIFO I2S_RXFIFO(I2S1)
/* I2S Status Feedback Register */
#define I2S_STATE(port) MMIO32(port + 0x010)
#define I2S_STATE(port) MMIO32((port) + 0x010)
#define I2S0_STATE I2S_STATE(I2S0)
#define I2S1_STATE I2S_STATE(I2S1)
/* I2S DMA Configuration Register 1 */
#define I2S_DMA1(port) MMIO32(port + 0x014)
#define I2S_DMA1(port) MMIO32((port) + 0x014)
#define I2S0_DMA1 I2S_DMA1(I2S0)
#define I2S1_DMA1 I2S_DMA1(I2S1)
/* I2S DMA Configuration Register 2 */
#define I2S_DMA2(port) MMIO32(port + 0x018)
#define I2S_DMA2(port) MMIO32((port) + 0x018)
#define I2S0_DMA2 I2S_DMA2(I2S0)
#define I2S1_DMA2 I2S_DMA2(I2S1)
/* I2S Interrupt Request Control Register */
#define I2S_IRQ(port) MMIO32(port + 0x01C)
#define I2S_IRQ(port) MMIO32((port) + 0x01C)
#define I2S0_IRQ I2S_IRQ(I2S0)
#define I2S1_IRQ I2S_IRQ(I2S1)
/* I2S Transmit MCLK divider */
#define I2S_TXRATE(port) MMIO32(port + 0x020)
#define I2S_TXRATE(port) MMIO32((port) + 0x020)
#define I2S0_TXRATE I2S_TXRATE(I2S0)
#define I2S1_TXRATE I2S_TXRATE(I2S1)
/* I2S Receive MCLK divider */
#define I2S_RXRATE(port) MMIO32(port + 0x024)
#define I2S_RXRATE(port) MMIO32((port) + 0x024)
#define I2S0_RXRATE I2S_RXRATE(I2S0)
#define I2S1_RXRATE I2S_RXRATE(I2S1)
/* I2S Transmit bit rate divider */
#define I2S_TXBITRATE(port) MMIO32(port + 0x028)
#define I2S_TXBITRATE(port) MMIO32((port) + 0x028)
#define I2S0_TXBITRATE I2S_TXBITRATE(I2S0)
#define I2S1_TXBITRATE I2S_TXBITRATE(I2S1)
/* I2S Receive bit rate divider */
#define I2S_RXBITRATE(port) MMIO32(port + 0x02C)
#define I2S_RXBITRATE(port) MMIO32((port) + 0x02C)
#define I2S0_RXBITRATE I2S_RXBITRATE(I2S0)
#define I2S1_RXBITRATE I2S_RXBITRATE(I2S1)
/* I2S Transmit mode control */
#define I2S_TXMODE(port) MMIO32(port + 0x030)
#define I2S_TXMODE(port) MMIO32((port) + 0x030)
#define I2S0_TXMODE I2S_TXMODE(I2S0)
#define I2S1_TXMODE I2S_TXMODE(I2S1)
/* I2S Receive mode control */
#define I2S_RXMODE(port) MMIO32(port + 0x034)
#define I2S_RXMODE(port) MMIO32((port) + 0x034)
#define I2S0_RXMODE I2S_RXMODE(I2S0)
#define I2S1_RXMODE I2S_RXMODE(I2S1)

2
include/libopencm3/lpc43xx/scu.h
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@@ -87,7 +87,7 @@ LGPL License Terms @ref lgpl_license
/* Pin configuration registers */
#define SCU_SFS(group, pin) MMIO32(group + pin)
#define SCU_SFS(group, pin) MMIO32((group) + (pin))
/* Pins P0_n */
#define SCU_SFSP0_0 SCU_SFS(PIN_GROUP0, PIN0)

20
include/libopencm3/lpc43xx/ssp.h
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@@ -50,22 +50,22 @@ LGPL License Terms @ref lgpl_license
/* --- SSP registers ------------------------------------------------------- */
/* Control Register 0 */
#define SSP_CR0(port) MMIO32(port + 0x000)
#define SSP_CR0(port) MMIO32((port) + 0x000)
#define SSP0_CR0 SSP_CR0(SSP0)
#define SSP1_CR0 SSP_CR0(SSP1)
/* Control Register 1 */
#define SSP_CR1(port) MMIO32(port + 0x004)
#define SSP_CR1(port) MMIO32((port) + 0x004)
#define SSP0_CR1 SSP_CR1(SSP0)
#define SSP1_CR1 SSP_CR1(SSP1)
/* Data Register */
#define SSP_DR(port) MMIO32(port + 0x008)
#define SSP_DR(port) MMIO32((port) + 0x008)
#define SSP0_DR SSP_DR(SSP0)
#define SSP1_DR SSP_DR(SSP1)
/* Status Register */
#define SSP_SR(port) MMIO32(port + 0x00C)
#define SSP_SR(port) MMIO32((port) + 0x00C)
#define SSP0_SR SSP_SR(SSP0)
#define SSP1_SR SSP_SR(SSP1)
@@ -76,32 +76,32 @@ LGPL License Terms @ref lgpl_license
#define SSP_SR_BSY BIT4
/* Clock Prescale Register */
#define SSP_CPSR(port) MMIO32(port + 0x010)
#define SSP_CPSR(port) MMIO32((port) + 0x010)
#define SSP0_CPSR SSP_CPSR(SSP0)
#define SSP1_CPSR SSP_CPSR(SSP1)
/* Interrupt Mask Set and Clear Register */
#define SSP_IMSC(port) MMIO32(port + 0x014)
#define SSP_IMSC(port) MMIO32((port) + 0x014)
#define SSP0_IMSC SSP_IMSC(SSP0)
#define SSP1_IMSC SSP_IMSC(SSP1)
/* Raw Interrupt Status Register */
#define SSP_RIS(port) MMIO32(port + 0x018)
#define SSP_RIS(port) MMIO32((port) + 0x018)
#define SSP0_RIS SSP_RIS(SSP0)
#define SSP1_RIS SSP_RIS(SSP1)
/* Masked Interrupt Status Register */
#define SSP_MIS(port) MMIO32(port + 0x01C)
#define SSP_MIS(port) MMIO32((port) + 0x01C)
#define SSP0_MIS SSP_MIS(SSP0)
#define SSP1_MIS SSP_MIS(SSP1)
/* SSPICR Interrupt Clear Register */
#define SSP_ICR(port) MMIO32(port + 0x020)
#define SSP_ICR(port) MMIO32((port) + 0x020)
#define SSP0_ICR SSP_ICR(SSP0)
#define SSP1_ICR SSP_ICR(SSP1)
/* SSP1 DMA control register */
#define SSP_DMACR(port) MMIO32(port + 0x024)
#define SSP_DMACR(port) MMIO32((port) + 0x024)
#define SSP0_DMACR SSP_DMACR(SSP0)
#define SSP1_DMACR SSP_DMACR(SSP1)

34
include/libopencm3/lpc43xx/timer.h
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@@ -51,119 +51,119 @@ LGPL License Terms @ref lgpl_license
/* --- Timer registers ----------------------------------------------------- */
/* Interrupt Register */
#define TIMER_IR(timer) MMIO32(timer + 0x000)
#define TIMER_IR(timer) MMIO32((timer) + 0x000)
#define TIMER0_IR TIMER_IR(TIMER0)
#define TIMER1_IR TIMER_IR(TIMER1)
#define TIMER2_IR TIMER_IR(TIMER2)
#define TIMER3_IR TIMER_IR(TIMER3)
/* Timer Control Register */
#define TIMER_TCR(timer) MMIO32(timer + 0x004)
#define TIMER_TCR(timer) MMIO32((timer) + 0x004)
#define TIMER0_TCR TIMER_TCR(TIMER0)
#define TIMER1_TCR TIMER_TCR(TIMER1)
#define TIMER2_TCR TIMER_TCR(TIMER2)
#define TIMER3_TCR TIMER_TCR(TIMER3)
/* Timer Counter */
#define TIMER_TC(timer) MMIO32(timer + 0x008)
#define TIMER_TC(timer) MMIO32((timer) + 0x008)
#define TIMER0_TC TIMER_TC(TIMER0)
#define TIMER1_TC TIMER_TC(TIMER1)
#define TIMER2_TC TIMER_TC(TIMER2)
#define TIMER3_TC TIMER_TC(TIMER3)
/* Prescale Register */
#define TIMER_PR(timer) MMIO32(timer + 0x00C)
#define TIMER_PR(timer) MMIO32((timer) + 0x00C)
#define TIMER0_PR TIMER_PR(TIMER0)
#define TIMER1_PR TIMER_PR(TIMER1)
#define TIMER2_PR TIMER_PR(TIMER2)
#define TIMER3_PR TIMER_PR(TIMER3)
/* Prescale Counter */
#define TIMER_PC(timer) MMIO32(timer + 0x010)
#define TIMER_PC(timer) MMIO32((timer) + 0x010)
#define TIMER0_PC TIMER_PC(TIMER0)
#define TIMER1_PC TIMER_PC(TIMER1)
#define TIMER2_PC TIMER_PC(TIMER2)
#define TIMER3_PC TIMER_PC(TIMER3)
/* Match Control Register */
#define TIMER_MCR(timer) MMIO32(timer + 0x014)
#define TIMER_MCR(timer) MMIO32((timer) + 0x014)
#define TIMER0_MCR TIMER_MCR(TIMER0)
#define TIMER1_MCR TIMER_MCR(TIMER1)
#define TIMER2_MCR TIMER_MCR(TIMER2)
#define TIMER3_MCR TIMER_MCR(TIMER3)
/* Match Register 0 */
#define TIMER_MR0(timer) MMIO32(timer + 0x018)
#define TIMER_MR0(timer) MMIO32((timer) + 0x018)
#define TIMER0_MR0 TIMER_MR0(TIMER0)
#define TIMER1_MR0 TIMER_MR0(TIMER1)
#define TIMER2_MR0 TIMER_MR0(TIMER2)
#define TIMER3_MR0 TIMER_MR0(TIMER3)
/* Match Register 1 */
#define TIMER_MR1(timer) MMIO32(timer + 0x01C)
#define TIMER_MR1(timer) MMIO32((timer) + 0x01C)
#define TIMER0_MR1 TIMER_MR1(TIMER0)
#define TIMER1_MR1 TIMER_MR1(TIMER1)
#define TIMER2_MR1 TIMER_MR1(TIMER2)
#define TIMER3_MR1 TIMER_MR1(TIMER3)
/* Match Register 2 */
#define TIMER_MR2(timer) MMIO32(timer + 0x020)
#define TIMER_MR2(timer) MMIO32((timer) + 0x020)
#define TIMER0_MR2 TIMER_MR2(TIMER0)
#define TIMER1_MR2 TIMER_MR2(TIMER1)
#define TIMER2_MR2 TIMER_MR2(TIMER2)
#define TIMER3_MR2 TIMER_MR2(TIMER3)
/* Match Register 3 */
#define TIMER_MR3(timer) MMIO32(timer + 0x024)
#define TIMER_MR3(timer) MMIO32((timer) + 0x024)
#define TIMER0_MR3 TIMER_MR3(TIMER0)
#define TIMER1_MR3 TIMER_MR3(TIMER1)
#define TIMER2_MR3 TIMER_MR3(TIMER2)
#define TIMER3_MR3 TIMER_MR3(TIMER3)
/* Capture Control Register */
#define TIMER_CCR(timer) MMIO32(timer + 0x028)
#define TIMER_CCR(timer) MMIO32((timer) + 0x028)
#define TIMER0_CCR TIMER_CCR(TIMER0)
#define TIMER1_CCR TIMER_CCR(TIMER1)
#define TIMER2_CCR TIMER_CCR(TIMER2)
#define TIMER3_CCR TIMER_CCR(TIMER3)
/* Capture Register 0 */
#define TIMER_CR0(timer) MMIO32(timer + 0x02C)
#define TIMER_CR0(timer) MMIO32((timer) + 0x02C)
#define TIMER0_CR0 TIMER_CR0(TIMER0)
#define TIMER1_CR0 TIMER_CR0(TIMER1)
#define TIMER2_CR0 TIMER_CR0(TIMER2)
#define TIMER3_CR0 TIMER_CR0(TIMER3)
/* Capture Register 1 */
#define TIMER_CR1(timer) MMIO32(timer + 0x030)
#define TIMER_CR1(timer) MMIO32((timer) + 0x030)
#define TIMER0_CR1 TIMER_CR1(TIMER0)
#define TIMER1_CR1 TIMER_CR1(TIMER1)
#define TIMER2_CR1 TIMER_CR1(TIMER2)
#define TIMER3_CR1 TIMER_CR1(TIMER3)
/* Capture Register 2 */
#define TIMER_CR2(timer) MMIO32(timer + 0x034)
#define TIMER_CR2(timer) MMIO32((timer) + 0x034)
#define TIMER0_CR2 TIMER_CR2(TIMER0)
#define TIMER1_CR2 TIMER_CR2(TIMER1)
#define TIMER2_CR2 TIMER_CR2(TIMER2)
#define TIMER3_CR2 TIMER_CR2(TIMER3)
/* Capture Register 3 */
#define TIMER_CR3(timer) MMIO32(timer + 0x038)
#define TIMER_CR3(timer) MMIO32((timer) + 0x038)
#define TIMER0_CR3 TIMER_CR3(TIMER0)
#define TIMER1_CR3 TIMER_CR3(TIMER1)
#define TIMER2_CR3 TIMER_CR3(TIMER2)
#define TIMER3_CR3 TIMER_CR3(TIMER3)
/* External Match Register */
#define TIMER_EMR(timer) MMIO32(timer + 0x03C)
#define TIMER_EMR(timer) MMIO32((timer) + 0x03C)
#define TIMER0_EMR TIMER_EMR(TIMER0)
#define TIMER1_EMR TIMER_EMR(TIMER1)
#define TIMER2_EMR TIMER_EMR(TIMER2)
#define TIMER3_EMR TIMER_EMR(TIMER3)
/* Count Control Register */
#define TIMER_CTCR(timer) MMIO32(timer + 0x070)
#define TIMER_CTCR(timer) MMIO32((timer) + 0x070)
#define TIMER0_CTCR TIMER_CTCR(TIMER0)
#define TIMER1_CTCR TIMER_CTCR(TIMER1)
#define TIMER2_CTCR TIMER_CTCR(TIMER2)

54
include/libopencm3/lpc43xx/uart.h
View File

@@ -34,66 +34,66 @@
/* --- UART registers ------------------------------------------------------- */
/* Receiver Buffer Register (DLAB=0) Read Only */
#define UART_RBR(port) MMIO32(port + 0x000) /* 8bits */
#define UART_RBR(port) MMIO32((port) + 0x000) /* 8bits */
/* Transmitter Holding Register (DLAB=0) Write Only */
#define UART_THR(port) MMIO32(port + 0x000) /* 8bits */
#define UART_THR(port) MMIO32((port) + 0x000) /* 8bits */
/* Divisor Latch LSB Register (DLAB=1) */
#define UART_DLL(port) MMIO32(port + 0x000) /* 8bits */
#define UART_DLL(port) MMIO32((port) + 0x000) /* 8bits */
/* Divisor Latch MSB Register (DLAB=1) */
#define UART_DLM(port) MMIO32(port + 0x004) /* 8bits */
#define UART_DLM(port) MMIO32((port) + 0x004) /* 8bits */
/* Interrupt Enable Register (DLAB=0) */
#define UART_IER(port) MMIO32(port + 0x004)
#define UART_IER(port) MMIO32((port) + 0x004)
/* Interrupt ID Register Read Only */
#define UART_IIR(port) MMIO32(port + 0x008)
#define UART_IIR(port) MMIO32((port) + 0x008)
/* FIFO Control Register Write Only */
#define UART_FCR(port) MMIO32(port + 0x008)
#define UART_FCR(port) MMIO32((port) + 0x008)
/* Line Control Register */
#define UART_LCR(port) MMIO32(port + 0x00C)
#define UART_LCR(port) MMIO32((port) + 0x00C)
/* MCR only for UART1 */
/* Line Status Register */
#define UART_LSR(port) MMIO32(port + 0x014)
#define UART_LSR(port) MMIO32((port) + 0x014)
/* Auto Baud Control Register */
#define UART_ACR(port) MMIO32(port + 0x020)
#define UART_ACR(port) MMIO32((port) + 0x020)
/* IrDA Control Register only for UART0/2/3 */
#define UART_ICR(port) MMIO32(port + 0x024)
#define UART_ICR(port) MMIO32((port) + 0x024)
/* Fractional Divider Register */
#define UART_FDR(port) MMIO32(port + 0x028)
#define UART_FDR(port) MMIO32((port) + 0x028)
/* Oversampling Register only for UART0/2/3 */
#define UART_OSR(port) MMIO32(port + 0x02C)
#define UART_OSR(port) MMIO32((port) + 0x02C)
/* Half-Duplex enable Register only for UART0/2/3 */
#define UART_HDEN(port) MMIO32(port + 0x040)
#define UART_HDEN(port) MMIO32((port) + 0x040)
/* Smart card Interface Register Only for UART0/2/3 */
#define UART_SCICTRL(port) MMIO32(port + 0x048)
#define UART_SCICTRL(port) MMIO32((port) + 0x048)
/* RS-485/EIA-485 Control Register */
#define UART_RS485CTRL(port) MMIO32(port + 0x04C)
#define UART_RS485CTRL(port) MMIO32((port) + 0x04C)
/* RS-485/EIA-485 Address Match Register */
#define UART_RS485ADRMATCH(port) MMIO32(port + 0x050)
#define UART_RS485ADRMATCH(port) MMIO32((port) + 0x050)
/* RS-485/EIA-485 Direction Control Delay Register */
#define UART_RS485DLY(port) MMIO32(port + 0x054)
#define UART_RS485DLY(port) MMIO32((port) + 0x054)
/* Synchronous Mode Control Register only for UART0/2/3 */
#define UART_SYNCCTRL(port) MMIO32(port + 0x058)
#define UART_SYNCCTRL(port) MMIO32((port) + 0x058)
/* Transmit Enable Register */
#define UART_TER(port) MMIO32(port + 0x05C)
#define UART_TER(port) MMIO32((port) + 0x05C)
/* --------------------- BIT DEFINITIONS ----------------------------------- */
/***********************************************************************
@@ -291,7 +291,7 @@
/* IrDA fixed pulse width mode */
#define UART_ICR_FIXPULSE_EN (1 << 2)
/* PulseDiv - Configures the pulse when FixPulseEn = 1 */
#define UART_ICR_PULSEDIV(n) ((uint32_t)((n&0x07)<<3))
#define UART_ICR_PULSEDIV(n) ((uint32_t)(((n)&0x07)<<3))
/* UART IRDA bit mask */
#define UART_ICR_BITMASK ((uint32_t)(0x3F))
@@ -311,9 +311,9 @@
/* ISO7816-3 protocol T1 is selected*/
#define UART_SCICTRL_PROTSEL_T1 (1 << 2)
/* number of retransmission*/
#define UART_SCICTRL_TXRETRY(n) ((uint32_t)((n&0x07)<<5))
#define UART_SCICTRL_TXRETRY(n) ((uint32_t)(((n)&0x07)<<5))
/* Extra guard time*/
#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)((n&0xFF)<<8))
#define UART_SCICTRL_GUARDTIME(n) ((uint32_t)(((n)&0xFF)<<8))
/*********************************************************************
* Macro defines for Macro defines for UART synchronous control register
@@ -338,9 +338,9 @@
**********************************************************************/
/* Baud-rate generation pre-scaler divisor */
#define UART_FDR_DIVADDVAL(n) ((uint32_t)(n&0x0F))
#define UART_FDR_DIVADDVAL(n) ((uint32_t)((n)&0x0F))
/* Baud-rate pre-scaler multiplier value */
#define UART_FDR_MULVAL(n) ((uint32_t)((n<<4)&0xF0))
#define UART_FDR_MULVAL(n) ((uint32_t)(((n)<<4)&0xF0))
/* UART Fractional Divider register bit mask */
#define UART_FDR_BITMASK ((uint32_t)(0xFF))
@@ -354,9 +354,9 @@
* Macro defines for Macro defines for UART FIFO Level register
**********************************************************************/
/* Reflects the current level of the UART receiver FIFO */
#define UART_FIFOLVL_RX(n) ((uint32_t)(n&0x0F))
#define UART_FIFOLVL_RX(n) ((uint32_t)((n)&0x0F))
/* Reflects the current level of the UART transmitter FIFO */
#define UART_FIFOLVL_TX(n) ((uint32_t)((n>>8)&0x0F))
#define UART_FIFOLVL_TX(n) ((uint32_t)(((n)>>8)&0x0F))
/* UART FIFO Level Register bit mask */
#define UART_FIFOLVL_BITMASK ((uint32_t)(0x0F0F))

10
include/libopencm3/lpc43xx/usb.h
View File

@@ -51,7 +51,7 @@ struct usb_transfer_descriptor_t {
#define USB_TD_DTD_TOKEN_TOTAL_BYTES_SHIFT (16)
#define USB_TD_DTD_TOKEN_TOTAL_BYTES_WIDTH (15)
#define USB_TD_DTD_TOKEN_TOTAL_BYTES_MASK BIT_MASK(USB_TD_DTD_TOKEN_TOTAL_BYTES)
#define USB_TD_DTD_TOKEN_TOTAL_BYTES(x) BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, x)
#define USB_TD_DTD_TOKEN_TOTAL_BYTES(x) BIT_ARG(USB_TD_DTD_TOKEN_TOTAL_BYTES, (x))
#define USB_TD_DTD_TOKEN_IOC_SHIFT (15)
#define USB_TD_DTD_TOKEN_IOC (1 << USB_TD_DTD_TOKEN_IOC_SHIFT)
@@ -59,7 +59,7 @@ struct usb_transfer_descriptor_t {
#define USB_TD_DTD_TOKEN_MULTO_SHIFT (10)
#define USB_TD_DTD_TOKEN_MULTO_WIDTH (2)
#define USB_TD_DTD_TOKEN_MULTO_MASK BIT_MASK(USB_TD_DTD_TOKEN_MULTO)
#define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, x)
#define USB_TD_DTD_TOKEN_MULTO(x) BIT_ARG(USB_TD_DTD_TOKEN_MULTO, (x))
#define USB_TD_DTD_TOKEN_STATUS_ACTIVE_SHIFT (7)
#define USB_TD_DTD_TOKEN_STATUS_ACTIVE \
@@ -97,7 +97,7 @@ typedef struct {
#define USB_QH_CAPABILITIES_MPL_SHIFT (16)
#define USB_QH_CAPABILITIES_MPL_WIDTH (11)
#define USB_QH_CAPABILITIES_MPL_MASK BIT_MASK(USB_QH_CAPABILITIES_MPL)
#define USB_QH_CAPABILITIES_MPL(x) BIT_ARG(USB_QH_CAPABILITIES_MPL, x)
#define USB_QH_CAPABILITIES_MPL(x) BIT_ARG(USB_QH_CAPABILITIES_MPL, (x))
#define USB_QH_CAPABILITIES_ZLT_SHIFT (29)
#define USB_QH_CAPABILITIES_ZLT (1 << USB_QH_CAPABILITIES_ZLT_SHIFT)
@@ -105,7 +105,7 @@ typedef struct {
#define USB_QH_CAPABILITIES_MULT_SHIFT (30)
#define USB_QH_CAPABILITIES_MULT_WIDTH (2)
#define USB_QH_CAPABILITIES_MULT_MASK BIT_MASK(USB_QH_CAPABILITIES_MULT)
#define USB_QH_CAPABILITIES_MULT(x) BIT_ARG(USB_QH_CAPABILITIES_MULT, x)
#define USB_QH_CAPABILITIES_MULT(x) BIT_ARG(USB_QH_CAPABILITIES_MULT, (x))
/* --- USB0 registers ------------------------------------------------------ */
@@ -218,7 +218,7 @@ typedef struct {
/* Endpoint control */
#define USB0_ENDPTCTRL(logical_ep) MMIO32(USB0_BASE + 0x1C0 + \
(logical_ep * 4))
((logical_ep) * 4))
/* Endpoint control 0 */
#define USB0_ENDPTCTRL0 USB0_ENDPTCTRL(0)