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Surround all macro parameters with ()

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All the macro arguments that are user supplied, or potentially, wrap properly
in () as good practice.

Probably missed one or two, and a lot of them are possibly unnecessary, but
it's straightforward to just do it always.

Fixes github issue #321
This commit is contained in:
Karl Palsson
2015-10-14 21:52:54 +00:00
parent c899273c62
commit c72f3d588a
50 changed files with 559 additions and 559 deletions
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include/libopencm3/cm3/itm.h
+3 -3
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@@ -30,9 +30,9 @@
/* --- ITM registers ------------------------------------------------------- */
/* Stimulus Port x (ITM_STIM<sz>(x)) */
#define ITM_STIM8(n) (MMIO8(ITM_BASE + (n*4)))
#define ITM_STIM16(n) (MMIO16(ITM_BASE + (n*4)))
#define ITM_STIM32(n) (MMIO32(ITM_BASE + (n*4)))
#define ITM_STIM8(n) (MMIO8(ITM_BASE + ((n)*4)))
#define ITM_STIM16(n) (MMIO16(ITM_BASE + ((n)*4)))
#define ITM_STIM32(n) (MMIO32(ITM_BASE + ((n)*4)))
/* Trace Enable ports (ITM_TER[x]) */
#define ITM_TER (&MMIO32(ITM_BASE + 0xE00))
include/libopencm3/cm3/nvic.h
+6 -6
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@@ -46,7 +46,7 @@
/* Note: 8 32bit Registers */
/* Note: Single register on CM0 */
#define NVIC_ISER(iser_id) MMIO32(NVIC_BASE + 0x00 + \
(iser_id * 4))
((iser_id) * 4))
/* NVIC_BASE + 0x020 (0xE000 E120 - 0xE000 E17F): Reserved */
@@ -54,7 +54,7 @@
/* Note: 8 32bit Registers */
/* Note: Single register on CM0 */
#define NVIC_ICER(icer_id) MMIO32(NVIC_BASE + 0x80 + \
(icer_id * 4))
((icer_id) * 4))
/* NVIC_BASE + 0x0A0 (0xE000 E1A0 - 0xE000 E1FF): Reserved */
@@ -62,7 +62,7 @@
/* Note: 8 32bit Registers */
/* Note: Single register on CM0 */
#define NVIC_ISPR(ispr_id) MMIO32(NVIC_BASE + 0x100 + \
(ispr_id * 4))
((ispr_id) * 4))
/* NVIC_BASE + 0x120 (0xE000 E220 - 0xE000 E27F): Reserved */
@@ -70,7 +70,7 @@
/* Note: 8 32bit Registers */
/* Note: Single register on CM0 */
#define NVIC_ICPR(icpr_id) MMIO32(NVIC_BASE + 0x180 + \
(icpr_id * 4))
((icpr_id) * 4))
/* NVIC_BASE + 0x1A0 (0xE000 E2A0 - 0xE00 E2FF): Reserved */
@@ -79,7 +79,7 @@
/* IABR: Interrupt Active Bit Register */
/* Note: 8 32bit Registers */
#define NVIC_IABR(iabr_id) MMIO32(NVIC_BASE + 0x200 + \
(iabr_id * 4))
((iabr_id) * 4))
#endif
/* NVIC_BASE + 0x220 (0xE000 E320 - 0xE000 E3FF): Reserved */
@@ -88,7 +88,7 @@
/* Note: 240 8bit Registers */
/* Note: 32 8bit Registers on CM0 */
#define NVIC_IPR(ipr_id) MMIO8(NVIC_BASE + 0x300 + \
ipr_id)
(ipr_id))
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
/* STIR: Software Trigger Interrupt Register */
include/libopencm3/cm3/scb.h
+1 -1
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@@ -46,7 +46,7 @@
/* SHP: System Handler Priority Registers */
/* Note: 12 8bit registers */
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + shpr_id)
#define SCB_SHPR(shpr_id) MMIO8(SCB_BASE + 0x18 + (shpr_id))
#define SCB_SHPR1 MMIO32(SCB_BASE + 0x18)
#define SCB_SHPR2 MMIO32(SCB_BASE + 0x1C)
#define SCB_SHPR3 MMIO32(SCB_BASE + 0x20)
include/libopencm3/cm3/scs.h
+1 -1
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@@ -44,7 +44,7 @@
/* System Handler Priority 8 bits Registers, SHPR1/2/3 */
/* Note: 12 8bit Registers */
#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + ipr_id)
#define SCS_SHPR(ipr_id) MMIO8(SCS_BASE + 0xD18 + (ipr_id))
/*
* Debug Halting Control and Status Register (DHCSR).