From c6f861139dbf0d1a7119f56afb568885aa9f846d Mon Sep 17 00:00:00 2001 From: BuFran Date: Mon, 8 Jul 2013 17:21:39 +0200 Subject: [PATCH] Removed mostly copied code REG1 REG2 REG3 -> REGx --- include/libopencm3/lpc43xx/gpdma.h | 1254 ++------------------ include/libopencm3/lpc43xx/gpio.h | 136 +-- include/libopencm3/lpc43xx/sgpio.h | 1695 ++-------------------------- 3 files changed, 183 insertions(+), 2902 deletions(-) diff --git a/include/libopencm3/lpc43xx/gpdma.h b/include/libopencm3/lpc43xx/gpdma.h index 32d42947..371f1b9b 100644 --- a/include/libopencm3/lpc43xx/gpdma.h +++ b/include/libopencm3/lpc43xx/gpdma.h @@ -394,1230 +394,158 @@ #define GPDMA_SYNC_DMACSYNC_MASK (0xffff << GPDMA_SYNC_DMACSYNC_SHIFT) #define GPDMA_SYNC_DMACSYNC(x) ((x) << GPDMA_SYNC_DMACSYNC_SHIFT) -/* --- GPDMA_C0SRCADDR values ----------------------------------- */ +/* --- GPDMA_C[0..7]SRCADDR values ----------------------------------- */ /* SRCADDR: DMA source address */ -#define GPDMA_C0SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C0SRCADDR_SRCADDR_MASK \ - (0xffffffff << GPDMA_C0SRCADDR_SRCADDR_SHIFT) -#define GPDMA_C0SRCADDR_SRCADDR(x) ((x) << GPDMA_C0SRCADDR_SRCADDR_SHIFT) +#define GPDMA_CxSRCADDR_SRCADDR_SHIFT (0) +#define GPDMA_CxSRCADDR_SRCADDR_MASK \ + (0xffffffff << GPDMA_CxSRCADDR_SRCADDR_SHIFT) +#define GPDMA_CxSRCADDR_SRCADDR(x) ((x) << GPDMA_CxSRCADDR_SRCADDR_SHIFT) -/* --- GPDMA_C1SRCADDR values ----------------------------------- */ - -/* SRCADDR: DMA source address */ -#define GPDMA_C1SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C1SRCADDR_SRCADDR_MASK \ - (0xffffffff << GPDMA_C1SRCADDR_SRCADDR_SHIFT) -#define GPDMA_C1SRCADDR_SRCADDR(x) ((x) << GPDMA_C1SRCADDR_SRCADDR_SHIFT) - -/* --- GPDMA_C2SRCADDR values ----------------------------------- */ - -/* SRCADDR: DMA source address */ -#define GPDMA_C2SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C2SRCADDR_SRCADDR_MASK \ - (0xffffffff << GPDMA_C2SRCADDR_SRCADDR_SHIFT) -#define GPDMA_C2SRCADDR_SRCADDR(x) ((x) << GPDMA_C2SRCADDR_SRCADDR_SHIFT) - -/* --- GPDMA_C3SRCADDR values ----------------------------------- */ - -/* SRCADDR: DMA source address */ -#define GPDMA_C3SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C3SRCADDR_SRCADDR_MASK \ - (0xffffffff << GPDMA_C3SRCADDR_SRCADDR_SHIFT) -#define GPDMA_C3SRCADDR_SRCADDR(x) ((x) << GPDMA_C3SRCADDR_SRCADDR_SHIFT) - -/* --- GPDMA_C4SRCADDR values ----------------------------------- */ - -/* SRCADDR: DMA source address */ -#define GPDMA_C4SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C4SRCADDR_SRCADDR_MASK \ - (0xffffffff << GPDMA_C4SRCADDR_SRCADDR_SHIFT) -#define GPDMA_C4SRCADDR_SRCADDR(x) ((x) << GPDMA_C4SRCADDR_SRCADDR_SHIFT) - -/* --- GPDMA_C5SRCADDR values ----------------------------------- */ - -/* SRCADDR: DMA source address */ -#define GPDMA_C5SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C5SRCADDR_SRCADDR_MASK \ - (0xffffffff << GPDMA_C5SRCADDR_SRCADDR_SHIFT) -#define GPDMA_C5SRCADDR_SRCADDR(x) ((x) << GPDMA_C5SRCADDR_SRCADDR_SHIFT) - -/* --- GPDMA_C6SRCADDR values ----------------------------------- */ - -/* SRCADDR: DMA source address */ -#define GPDMA_C6SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C6SRCADDR_SRCADDR_MASK \ - (0xffffffff << GPDMA_C6SRCADDR_SRCADDR_SHIFT) -#define GPDMA_C6SRCADDR_SRCADDR(x) ((x) << GPDMA_C6SRCADDR_SRCADDR_SHIFT) - -/* --- GPDMA_C7SRCADDR values ----------------------------------- */ - -/* SRCADDR: DMA source address */ -#define GPDMA_C7SRCADDR_SRCADDR_SHIFT (0) -#define GPDMA_C7SRCADDR_SRCADDR_MASK \ - (0xffffffff << GPDMA_C7SRCADDR_SRCADDR_SHIFT) -#define GPDMA_C7SRCADDR_SRCADDR(x) ((x) << GPDMA_C7SRCADDR_SRCADDR_SHIFT) - -/* --- GPDMA_C0DESTADDR values ---------------------------------- */ +/* --- GPDMA_C[0..7]DESTADDR values ---------------------------------- */ /* DESTADDR: DMA source address */ -#define GPDMA_C0DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C0DESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_C0DESTADDR_DESTADDR_SHIFT) -#define GPDMA_C0DESTADDR_DESTADDR(x) ((x) << GPDMA_C0DESTADDR_DESTADDR_SHIFT) +#define GPDMA_CxDESTADDR_DESTADDR_SHIFT (0) +#define GPDMA_CxDESTADDR_DESTADDR_MASK \ + (0xffffffff << GPDMA_CxDESTADDR_DESTADDR_SHIFT) +#define GPDMA_CxDESTADDR_DESTADDR(x) ((x) << GPDMA_CxDESTADDR_DESTADDR_SHIFT) -/* --- GPDMA_C1DESTADDR values ---------------------------------- */ - -/* DESTADDR: DMA source address */ -#define GPDMA_C1DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C1DESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_C1DESTADDR_DESTADDR_SHIFT) -#define GPDMA_C1DESTADDR_DESTADDR(x) ((x) << GPDMA_C1DESTADDR_DESTADDR_SHIFT) - -/* --- GPDMA_C2DESTADDR values ---------------------------------- */ - -/* DESTADDR: DMA source address */ -#define GPDMA_C2DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C2DESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_C2DESTADDR_DESTADDR_SHIFT) -#define GPDMA_C2DESTADDR_DESTADDR(x) ((x) << GPDMA_C2DESTADDR_DESTADDR_SHIFT) - -/* --- GPDMA_C3DESTADDR values ---------------------------------- */ - -/* DESTADDR: DMA source address */ -#define GPDMA_C3DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C3DESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_C3DESTADDR_DESTADDR_SHIFT) -#define GPDMA_C3DESTADDR_DESTADDR(x) ((x) << GPDMA_C3DESTADDR_DESTADDR_SHIFT) - -/* --- GPDMA_C4DESTADDR values ---------------------------------- */ - -/* DESTADDR: DMA source address */ -#define GPDMA_C4DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C4DESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_C4DESTADDR_DESTADDR_SHIFT) -#define GPDMA_C4DESTADDR_DESTADDR(x) ((x) << GPDMA_C4DESTADDR_DESTADDR_SHIFT) - -/* --- GPDMA_C5DESTADDR values ---------------------------------- */ - -/* DESTADDR: DMA source address */ -#define GPDMA_C5DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C5DESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_C5DESTADDR_DESTADDR_SHIFT) -#define GPDMA_C5DESTADDR_DESTADDR(x) ((x) << GPDMA_C5DESTADDR_DESTADDR_SHIFT) - -/* --- GPDMA_C6DESTADDR values ---------------------------------- */ - -/* DESTADDR: DMA source address */ -#define GPDMA_C6DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C6DESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_C6DESTADDR_DESTADDR_SHIFT) -#define GPDMA_C6DESTADDR_DESTADDR(x) ((x) << GPDMA_C6DESTADDR_DESTADDR_SHIFT) - -/* --- GPDMA_C7DESTADDR values ---------------------------------- */ - -/* DESTADDR: DMA source address */ -#define GPDMA_C7DESTADDR_DESTADDR_SHIFT (0) -#define GPDMA_C7DESTADDR_DESTADDR_MASK \ - (0xffffffff << GPDMA_C7DESTADDR_DESTADDR_SHIFT) -#define GPDMA_C7DESTADDR_DESTADDR(x) ((x) << GPDMA_C7DESTADDR_DESTADDR_SHIFT) - -/* --- GPDMA_C0LLI values --------------------------------------- */ +/* --- GPDMA_C[0..7]LLI values --------------------------------------- */ /* LM: AHB master select for loading the next LLI */ -#define GPDMA_C0LLI_LM_SHIFT (0) -#define GPDMA_C0LLI_LM_MASK (0x1 << GPDMA_C0LLI_LM_SHIFT) -#define GPDMA_C0LLI_LM(x) ((x) << GPDMA_C0LLI_LM_SHIFT) +#define GPDMA_CxLLI_LM_SHIFT (0) +#define GPDMA_CxLLI_LM_MASK (0x1 << GPDMA_CxLLI_LM_SHIFT) +#define GPDMA_CxLLI_LM(x) ((x) << GPDMA_CxLLI_LM_SHIFT) /* LLI: Linked list item */ -#define GPDMA_C0LLI_LLI_SHIFT (2) -#define GPDMA_C0LLI_LLI_MASK (0x3fffffff << GPDMA_C0LLI_LLI_SHIFT) -#define GPDMA_C0LLI_LLI(x) ((x) << GPDMA_C0LLI_LLI_SHIFT) +#define GPDMA_CxLLI_LLI_SHIFT (2) +#define GPDMA_CxLLI_LLI_MASK (0x3fffffff << GPDMA_CxLLI_LLI_SHIFT) +#define GPDMA_CxLLI_LLI(x) ((x) << GPDMA_CxLLI_LLI_SHIFT) -/* --- GPDMA_C1LLI values --------------------------------------- */ - -/* LM: AHB master select for loading the next LLI */ -#define GPDMA_C1LLI_LM_SHIFT (0) -#define GPDMA_C1LLI_LM_MASK (0x1 << GPDMA_C1LLI_LM_SHIFT) -#define GPDMA_C1LLI_LM(x) ((x) << GPDMA_C1LLI_LM_SHIFT) - -/* LLI: Linked list item */ -#define GPDMA_C1LLI_LLI_SHIFT (2) -#define GPDMA_C1LLI_LLI_MASK (0x3fffffff << GPDMA_C1LLI_LLI_SHIFT) -#define GPDMA_C1LLI_LLI(x) ((x) << GPDMA_C1LLI_LLI_SHIFT) - -/* --- GPDMA_C2LLI values --------------------------------------- */ - -/* LM: AHB master select for loading the next LLI */ -#define GPDMA_C2LLI_LM_SHIFT (0) -#define GPDMA_C2LLI_LM_MASK (0x1 << GPDMA_C2LLI_LM_SHIFT) -#define GPDMA_C2LLI_LM(x) ((x) << GPDMA_C2LLI_LM_SHIFT) - -/* LLI: Linked list item */ -#define GPDMA_C2LLI_LLI_SHIFT (2) -#define GPDMA_C2LLI_LLI_MASK (0x3fffffff << GPDMA_C2LLI_LLI_SHIFT) -#define GPDMA_C2LLI_LLI(x) ((x) << GPDMA_C2LLI_LLI_SHIFT) - -/* --- GPDMA_C3LLI values --------------------------------------- */ - -/* LM: AHB master select for loading the next LLI */ -#define GPDMA_C3LLI_LM_SHIFT (0) -#define GPDMA_C3LLI_LM_MASK (0x1 << GPDMA_C3LLI_LM_SHIFT) -#define GPDMA_C3LLI_LM(x) ((x) << GPDMA_C3LLI_LM_SHIFT) - -/* LLI: Linked list item */ -#define GPDMA_C3LLI_LLI_SHIFT (2) -#define GPDMA_C3LLI_LLI_MASK (0x3fffffff << GPDMA_C3LLI_LLI_SHIFT) -#define GPDMA_C3LLI_LLI(x) ((x) << GPDMA_C3LLI_LLI_SHIFT) - -/* --- GPDMA_C4LLI values --------------------------------------- */ - -/* LM: AHB master select for loading the next LLI */ -#define GPDMA_C4LLI_LM_SHIFT (0) -#define GPDMA_C4LLI_LM_MASK (0x1 << GPDMA_C4LLI_LM_SHIFT) -#define GPDMA_C4LLI_LM(x) ((x) << GPDMA_C4LLI_LM_SHIFT) - -/* LLI: Linked list item */ -#define GPDMA_C4LLI_LLI_SHIFT (2) -#define GPDMA_C4LLI_LLI_MASK (0x3fffffff << GPDMA_C4LLI_LLI_SHIFT) -#define GPDMA_C4LLI_LLI(x) ((x) << GPDMA_C4LLI_LLI_SHIFT) - -/* --- GPDMA_C5LLI values --------------------------------------- */ - -/* LM: AHB master select for loading the next LLI */ -#define GPDMA_C5LLI_LM_SHIFT (0) -#define GPDMA_C5LLI_LM_MASK (0x1 << GPDMA_C5LLI_LM_SHIFT) -#define GPDMA_C5LLI_LM(x) ((x) << GPDMA_C5LLI_LM_SHIFT) - -/* LLI: Linked list item */ -#define GPDMA_C5LLI_LLI_SHIFT (2) -#define GPDMA_C5LLI_LLI_MASK (0x3fffffff << GPDMA_C5LLI_LLI_SHIFT) -#define GPDMA_C5LLI_LLI(x) ((x) << GPDMA_C5LLI_LLI_SHIFT) - -/* --- GPDMA_C6LLI values --------------------------------------- */ - -/* LM: AHB master select for loading the next LLI */ -#define GPDMA_C6LLI_LM_SHIFT (0) -#define GPDMA_C6LLI_LM_MASK (0x1 << GPDMA_C6LLI_LM_SHIFT) -#define GPDMA_C6LLI_LM(x) ((x) << GPDMA_C6LLI_LM_SHIFT) - -/* LLI: Linked list item */ -#define GPDMA_C6LLI_LLI_SHIFT (2) -#define GPDMA_C6LLI_LLI_MASK (0x3fffffff << GPDMA_C6LLI_LLI_SHIFT) -#define GPDMA_C6LLI_LLI(x) ((x) << GPDMA_C6LLI_LLI_SHIFT) - -/* --- GPDMA_C7LLI values --------------------------------------- */ - -/* LM: AHB master select for loading the next LLI */ -#define GPDMA_C7LLI_LM_SHIFT (0) -#define GPDMA_C7LLI_LM_MASK (0x1 << GPDMA_C7LLI_LM_SHIFT) -#define GPDMA_C7LLI_LM(x) ((x) << GPDMA_C7LLI_LM_SHIFT) - -/* LLI: Linked list item */ -#define GPDMA_C7LLI_LLI_SHIFT (2) -#define GPDMA_C7LLI_LLI_MASK (0x3fffffff << GPDMA_C7LLI_LLI_SHIFT) -#define GPDMA_C7LLI_LLI(x) ((x) << GPDMA_C7LLI_LLI_SHIFT) - -/* --- GPDMA_C0CONTROL values ----------------------------------- */ +/* --- GPDMA_C[0..7]CONTROL values ----------------------------------- */ /* TRANSFERSIZE: Transfer size in number of transfers */ -#define GPDMA_C0CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C0CONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_C0CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C0CONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_C0CONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT (0) +#define GPDMA_CxCONTROL_TRANSFERSIZE_MASK \ + (0xfff << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) +#define GPDMA_CxCONTROL_TRANSFERSIZE(x) \ + ((x) << GPDMA_CxCONTROL_TRANSFERSIZE_SHIFT) /* SBSIZE: Source burst size */ -#define GPDMA_C0CONTROL_SBSIZE_SHIFT (12) -#define GPDMA_C0CONTROL_SBSIZE_MASK (0x7 << GPDMA_C0CONTROL_SBSIZE_SHIFT) -#define GPDMA_C0CONTROL_SBSIZE(x) ((x) << GPDMA_C0CONTROL_SBSIZE_SHIFT) +#define GPDMA_CxCONTROL_SBSIZE_SHIFT (12) +#define GPDMA_CxCONTROL_SBSIZE_MASK (0x7 << GPDMA_CxCONTROL_SBSIZE_SHIFT) +#define GPDMA_CxCONTROL_SBSIZE(x) ((x) << GPDMA_CxCONTROL_SBSIZE_SHIFT) /* DBSIZE: Destination burst size */ -#define GPDMA_C0CONTROL_DBSIZE_SHIFT (15) -#define GPDMA_C0CONTROL_DBSIZE_MASK (0x7 << GPDMA_C0CONTROL_DBSIZE_SHIFT) -#define GPDMA_C0CONTROL_DBSIZE(x) ((x) << GPDMA_C0CONTROL_DBSIZE_SHIFT) +#define GPDMA_CxCONTROL_DBSIZE_SHIFT (15) +#define GPDMA_CxCONTROL_DBSIZE_MASK (0x7 << GPDMA_CxCONTROL_DBSIZE_SHIFT) +#define GPDMA_CxCONTROL_DBSIZE(x) ((x) << GPDMA_CxCONTROL_DBSIZE_SHIFT) /* SWIDTH: Source transfer width */ -#define GPDMA_C0CONTROL_SWIDTH_SHIFT (18) -#define GPDMA_C0CONTROL_SWIDTH_MASK (0x7 << GPDMA_C0CONTROL_SWIDTH_SHIFT) -#define GPDMA_C0CONTROL_SWIDTH(x) ((x) << GPDMA_C0CONTROL_SWIDTH_SHIFT) +#define GPDMA_CxCONTROL_SWIDTH_SHIFT (18) +#define GPDMA_CxCONTROL_SWIDTH_MASK (0x7 << GPDMA_CxCONTROL_SWIDTH_SHIFT) +#define GPDMA_CxCONTROL_SWIDTH(x) ((x) << GPDMA_CxCONTROL_SWIDTH_SHIFT) /* DWIDTH: Destination transfer width */ -#define GPDMA_C0CONTROL_DWIDTH_SHIFT (21) -#define GPDMA_C0CONTROL_DWIDTH_MASK (0x7 << GPDMA_C0CONTROL_DWIDTH_SHIFT) -#define GPDMA_C0CONTROL_DWIDTH(x) ((x) << GPDMA_C0CONTROL_DWIDTH_SHIFT) +#define GPDMA_CxCONTROL_DWIDTH_SHIFT (21) +#define GPDMA_CxCONTROL_DWIDTH_MASK (0x7 << GPDMA_CxCONTROL_DWIDTH_SHIFT) +#define GPDMA_CxCONTROL_DWIDTH(x) ((x) << GPDMA_CxCONTROL_DWIDTH_SHIFT) /* S: Source AHB master select */ -#define GPDMA_C0CONTROL_S_SHIFT (24) -#define GPDMA_C0CONTROL_S_MASK (0x1 << GPDMA_C0CONTROL_S_SHIFT) -#define GPDMA_C0CONTROL_S(x) ((x) << GPDMA_C0CONTROL_S_SHIFT) +#define GPDMA_CxCONTROL_S_SHIFT (24) +#define GPDMA_CxCONTROL_S_MASK (0x1 << GPDMA_CxCONTROL_S_SHIFT) +#define GPDMA_CxCONTROL_S(x) ((x) << GPDMA_CxCONTROL_S_SHIFT) /* D: Destination AHB master select */ -#define GPDMA_C0CONTROL_D_SHIFT (25) -#define GPDMA_C0CONTROL_D_MASK (0x1 << GPDMA_C0CONTROL_D_SHIFT) -#define GPDMA_C0CONTROL_D(x) ((x) << GPDMA_C0CONTROL_D_SHIFT) +#define GPDMA_CxCONTROL_D_SHIFT (25) +#define GPDMA_CxCONTROL_D_MASK (0x1 << GPDMA_CxCONTROL_D_SHIFT) +#define GPDMA_CxCONTROL_D(x) ((x) << GPDMA_CxCONTROL_D_SHIFT) /* SI: Source increment */ -#define GPDMA_C0CONTROL_SI_SHIFT (26) -#define GPDMA_C0CONTROL_SI_MASK (0x1 << GPDMA_C0CONTROL_SI_SHIFT) -#define GPDMA_C0CONTROL_SI(x) ((x) << GPDMA_C0CONTROL_SI_SHIFT) +#define GPDMA_CxCONTROL_SI_SHIFT (26) +#define GPDMA_CxCONTROL_SI_MASK (0x1 << GPDMA_CxCONTROL_SI_SHIFT) +#define GPDMA_Cx0CONTROL_SI(x) ((x) << GPDMA_CxCONTROL_SI_SHIFT) /* DI: Destination increment */ -#define GPDMA_C0CONTROL_DI_SHIFT (27) -#define GPDMA_C0CONTROL_DI_MASK (0x1 << GPDMA_C0CONTROL_DI_SHIFT) -#define GPDMA_C0CONTROL_DI(x) ((x) << GPDMA_C0CONTROL_DI_SHIFT) +#define GPDMA_CxCONTROL_DI_SHIFT (27) +#define GPDMA_CxCONTROL_DI_MASK (0x1 << GPDMA_CxCONTROL_DI_SHIFT) +#define GPDMA_CxCONTROL_DI(x) ((x) << GPDMA_CxCONTROL_DI_SHIFT) /* PROT1: This information is provided to the peripheral during a DMA bus access and indicates that the access is in user mode or privileged mode */ -#define GPDMA_C0CONTROL_PROT1_SHIFT (28) -#define GPDMA_C0CONTROL_PROT1_MASK (0x1 << GPDMA_C0CONTROL_PROT1_SHIFT) -#define GPDMA_C0CONTROL_PROT1(x) ((x) << GPDMA_C0CONTROL_PROT1_SHIFT) +#define GPDMA_CxCONTROL_PROT1_SHIFT (28) +#define GPDMA_CxCONTROL_PROT1_MASK (0x1 << GPDMA_CxCONTROL_PROT1_SHIFT) +#define GPDMA_CxCONTROL_PROT1(x) ((x) << GPDMA_CxCONTROL_PROT1_SHIFT) /* PROT2: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is bufferable or not bufferable */ -#define GPDMA_C0CONTROL_PROT2_SHIFT (29) -#define GPDMA_C0CONTROL_PROT2_MASK (0x1 << GPDMA_C0CONTROL_PROT2_SHIFT) -#define GPDMA_C0CONTROL_PROT2(x) ((x) << GPDMA_C0CONTROL_PROT2_SHIFT) +#define GPDMA_CxCONTROL_PROT2_SHIFT (29) +#define GPDMA_CxCONTROL_PROT2_MASK (0x1 << GPDMA_CxCONTROL_PROT2_SHIFT) +#define GPDMA_CxCONTROL_PROT2(x) ((x) << GPDMA_CxCONTROL_PROT2_SHIFT) /* PROT3: This information is provided to the peripheral during a DMA bus access and indicates to the peripheral that the access is cacheable or not cacheable */ -#define GPDMA_C0CONTROL_PROT3_SHIFT (30) -#define GPDMA_C0CONTROL_PROT3_MASK (0x1 << GPDMA_C0CONTROL_PROT3_SHIFT) -#define GPDMA_C0CONTROL_PROT3(x) ((x) << GPDMA_C0CONTROL_PROT3_SHIFT) +#define GPDMA_CxCONTROL_PROT3_SHIFT (30) +#define GPDMA_CxCONTROL_PROT3_MASK (0x1 << GPDMA_CxCONTROL_PROT3_SHIFT) +#define GPDMA_CxCONTROL_PROT3(x) ((x) << GPDMA_CxCONTROL_PROT3_SHIFT) /* I: Terminal count interrupt enable bit */ -#define GPDMA_C0CONTROL_I_SHIFT (31) -#define GPDMA_C0CONTROL_I_MASK (0x1 << GPDMA_C0CONTROL_I_SHIFT) -#define GPDMA_C0CONTROL_I(x) ((x) << GPDMA_C0CONTROL_I_SHIFT) +#define GPDMA_CxCONTROL_I_SHIFT (31) +#define GPDMA_CxCONTROL_I_MASK (0x1 << GPDMA_CxCONTROL_I_SHIFT) +#define GPDMA_CxCONTROL_I(x) ((x) << GPDMA_CxCONTROL_I_SHIFT) -/* --- GPDMA_C1CONTROL values ----------------------------------- */ - -/* TRANSFERSIZE: Transfer size in number of transfers */ -#define GPDMA_C1CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C1CONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_C1CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C1CONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_C1CONTROL_TRANSFERSIZE_SHIFT) - -/* SBSIZE: Source burst size */ -#define GPDMA_C1CONTROL_SBSIZE_SHIFT (12) -#define GPDMA_C1CONTROL_SBSIZE_MASK (0x7 << GPDMA_C1CONTROL_SBSIZE_SHIFT) -#define GPDMA_C1CONTROL_SBSIZE(x) ((x) << GPDMA_C1CONTROL_SBSIZE_SHIFT) - -/* DBSIZE: Destination burst size */ -#define GPDMA_C1CONTROL_DBSIZE_SHIFT (15) -#define GPDMA_C1CONTROL_DBSIZE_MASK (0x7 << GPDMA_C1CONTROL_DBSIZE_SHIFT) -#define GPDMA_C1CONTROL_DBSIZE(x) ((x) << GPDMA_C1CONTROL_DBSIZE_SHIFT) - -/* SWIDTH: Source transfer width */ -#define GPDMA_C1CONTROL_SWIDTH_SHIFT (18) -#define GPDMA_C1CONTROL_SWIDTH_MASK (0x7 << GPDMA_C1CONTROL_SWIDTH_SHIFT) -#define GPDMA_C1CONTROL_SWIDTH(x) ((x) << GPDMA_C1CONTROL_SWIDTH_SHIFT) - -/* DWIDTH: Destination transfer width */ -#define GPDMA_C1CONTROL_DWIDTH_SHIFT (21) -#define GPDMA_C1CONTROL_DWIDTH_MASK (0x7 << GPDMA_C1CONTROL_DWIDTH_SHIFT) -#define GPDMA_C1CONTROL_DWIDTH(x) ((x) << GPDMA_C1CONTROL_DWIDTH_SHIFT) - -/* S: Source AHB master select */ -#define GPDMA_C1CONTROL_S_SHIFT (24) -#define GPDMA_C1CONTROL_S_MASK (0x1 << GPDMA_C1CONTROL_S_SHIFT) -#define GPDMA_C1CONTROL_S(x) ((x) << GPDMA_C1CONTROL_S_SHIFT) - -/* D: Destination AHB master select */ -#define GPDMA_C1CONTROL_D_SHIFT (25) -#define GPDMA_C1CONTROL_D_MASK (0x1 << GPDMA_C1CONTROL_D_SHIFT) -#define GPDMA_C1CONTROL_D(x) ((x) << GPDMA_C1CONTROL_D_SHIFT) - -/* SI: Source increment */ -#define GPDMA_C1CONTROL_SI_SHIFT (26) -#define GPDMA_C1CONTROL_SI_MASK (0x1 << GPDMA_C1CONTROL_SI_SHIFT) -#define GPDMA_C1CONTROL_SI(x) ((x) << GPDMA_C1CONTROL_SI_SHIFT) - -/* DI: Destination increment */ -#define GPDMA_C1CONTROL_DI_SHIFT (27) -#define GPDMA_C1CONTROL_DI_MASK (0x1 << GPDMA_C1CONTROL_DI_SHIFT) -#define GPDMA_C1CONTROL_DI(x) ((x) << GPDMA_C1CONTROL_DI_SHIFT) - -/* PROT1: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode */ -#define GPDMA_C1CONTROL_PROT1_SHIFT (28) -#define GPDMA_C1CONTROL_PROT1_MASK (0x1 << GPDMA_C1CONTROL_PROT1_SHIFT) -#define GPDMA_C1CONTROL_PROT1(x) ((x) << GPDMA_C1CONTROL_PROT1_SHIFT) - -/* PROT2: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or not - bufferable */ -#define GPDMA_C1CONTROL_PROT2_SHIFT (29) -#define GPDMA_C1CONTROL_PROT2_MASK (0x1 << GPDMA_C1CONTROL_PROT2_SHIFT) -#define GPDMA_C1CONTROL_PROT2(x) ((x) << GPDMA_C1CONTROL_PROT2_SHIFT) - -/* PROT3: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable */ -#define GPDMA_C1CONTROL_PROT3_SHIFT (30) -#define GPDMA_C1CONTROL_PROT3_MASK (0x1 << GPDMA_C1CONTROL_PROT3_SHIFT) -#define GPDMA_C1CONTROL_PROT3(x) ((x) << GPDMA_C1CONTROL_PROT3_SHIFT) - -/* I: Terminal count interrupt enable bit */ -#define GPDMA_C1CONTROL_I_SHIFT (31) -#define GPDMA_C1CONTROL_I_MASK (0x1 << GPDMA_C1CONTROL_I_SHIFT) -#define GPDMA_C1CONTROL_I(x) ((x) << GPDMA_C1CONTROL_I_SHIFT) - -/* --- GPDMA_C2CONTROL values ----------------------------------- */ - -/* TRANSFERSIZE: Transfer size in number of transfers */ -#define GPDMA_C2CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C2CONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_C2CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C2CONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_C2CONTROL_TRANSFERSIZE_SHIFT) - -/* SBSIZE: Source burst size */ -#define GPDMA_C2CONTROL_SBSIZE_SHIFT (12) -#define GPDMA_C2CONTROL_SBSIZE_MASK (0x7 << GPDMA_C2CONTROL_SBSIZE_SHIFT) -#define GPDMA_C2CONTROL_SBSIZE(x) ((x) << GPDMA_C2CONTROL_SBSIZE_SHIFT) - -/* DBSIZE: Destination burst size */ -#define GPDMA_C2CONTROL_DBSIZE_SHIFT (15) -#define GPDMA_C2CONTROL_DBSIZE_MASK (0x7 << GPDMA_C2CONTROL_DBSIZE_SHIFT) -#define GPDMA_C2CONTROL_DBSIZE(x) ((x) << GPDMA_C2CONTROL_DBSIZE_SHIFT) - -/* SWIDTH: Source transfer width */ -#define GPDMA_C2CONTROL_SWIDTH_SHIFT (18) -#define GPDMA_C2CONTROL_SWIDTH_MASK (0x7 << GPDMA_C2CONTROL_SWIDTH_SHIFT) -#define GPDMA_C2CONTROL_SWIDTH(x) ((x) << GPDMA_C2CONTROL_SWIDTH_SHIFT) - -/* DWIDTH: Destination transfer width */ -#define GPDMA_C2CONTROL_DWIDTH_SHIFT (21) -#define GPDMA_C2CONTROL_DWIDTH_MASK (0x7 << GPDMA_C2CONTROL_DWIDTH_SHIFT) -#define GPDMA_C2CONTROL_DWIDTH(x) ((x) << GPDMA_C2CONTROL_DWIDTH_SHIFT) - -/* S: Source AHB master select */ -#define GPDMA_C2CONTROL_S_SHIFT (24) -#define GPDMA_C2CONTROL_S_MASK (0x1 << GPDMA_C2CONTROL_S_SHIFT) -#define GPDMA_C2CONTROL_S(x) ((x) << GPDMA_C2CONTROL_S_SHIFT) - -/* D: Destination AHB master select */ -#define GPDMA_C2CONTROL_D_SHIFT (25) -#define GPDMA_C2CONTROL_D_MASK (0x1 << GPDMA_C2CONTROL_D_SHIFT) -#define GPDMA_C2CONTROL_D(x) ((x) << GPDMA_C2CONTROL_D_SHIFT) - -/* SI: Source increment */ -#define GPDMA_C2CONTROL_SI_SHIFT (26) -#define GPDMA_C2CONTROL_SI_MASK (0x1 << GPDMA_C2CONTROL_SI_SHIFT) -#define GPDMA_C2CONTROL_SI(x) ((x) << GPDMA_C2CONTROL_SI_SHIFT) - -/* DI: Destination increment */ -#define GPDMA_C2CONTROL_DI_SHIFT (27) -#define GPDMA_C2CONTROL_DI_MASK (0x1 << GPDMA_C2CONTROL_DI_SHIFT) -#define GPDMA_C2CONTROL_DI(x) ((x) << GPDMA_C2CONTROL_DI_SHIFT) - -/* PROT1: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode */ -#define GPDMA_C2CONTROL_PROT1_SHIFT (28) -#define GPDMA_C2CONTROL_PROT1_MASK (0x1 << GPDMA_C2CONTROL_PROT1_SHIFT) -#define GPDMA_C2CONTROL_PROT1(x) ((x) << GPDMA_C2CONTROL_PROT1_SHIFT) - -/* PROT2: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or not - bufferable */ -#define GPDMA_C2CONTROL_PROT2_SHIFT (29) -#define GPDMA_C2CONTROL_PROT2_MASK (0x1 << GPDMA_C2CONTROL_PROT2_SHIFT) -#define GPDMA_C2CONTROL_PROT2(x) ((x) << GPDMA_C2CONTROL_PROT2_SHIFT) - -/* PROT3: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable */ -#define GPDMA_C2CONTROL_PROT3_SHIFT (30) -#define GPDMA_C2CONTROL_PROT3_MASK (0x1 << GPDMA_C2CONTROL_PROT3_SHIFT) -#define GPDMA_C2CONTROL_PROT3(x) ((x) << GPDMA_C2CONTROL_PROT3_SHIFT) - -/* I: Terminal count interrupt enable bit */ -#define GPDMA_C2CONTROL_I_SHIFT (31) -#define GPDMA_C2CONTROL_I_MASK (0x1 << GPDMA_C2CONTROL_I_SHIFT) -#define GPDMA_C2CONTROL_I(x) ((x) << GPDMA_C2CONTROL_I_SHIFT) - -/* --- GPDMA_C3CONTROL values ----------------------------------- */ - -/* TRANSFERSIZE: Transfer size in number of transfers */ -#define GPDMA_C3CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C3CONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_C3CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C3CONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_C3CONTROL_TRANSFERSIZE_SHIFT) - -/* SBSIZE: Source burst size */ -#define GPDMA_C3CONTROL_SBSIZE_SHIFT (12) -#define GPDMA_C3CONTROL_SBSIZE_MASK (0x7 << GPDMA_C3CONTROL_SBSIZE_SHIFT) -#define GPDMA_C3CONTROL_SBSIZE(x) ((x) << GPDMA_C3CONTROL_SBSIZE_SHIFT) - -/* DBSIZE: Destination burst size */ -#define GPDMA_C3CONTROL_DBSIZE_SHIFT (15) -#define GPDMA_C3CONTROL_DBSIZE_MASK (0x7 << GPDMA_C3CONTROL_DBSIZE_SHIFT) -#define GPDMA_C3CONTROL_DBSIZE(x) ((x) << GPDMA_C3CONTROL_DBSIZE_SHIFT) - -/* SWIDTH: Source transfer width */ -#define GPDMA_C3CONTROL_SWIDTH_SHIFT (18) -#define GPDMA_C3CONTROL_SWIDTH_MASK (0x7 << GPDMA_C3CONTROL_SWIDTH_SHIFT) -#define GPDMA_C3CONTROL_SWIDTH(x) ((x) << GPDMA_C3CONTROL_SWIDTH_SHIFT) - -/* DWIDTH: Destination transfer width */ -#define GPDMA_C3CONTROL_DWIDTH_SHIFT (21) -#define GPDMA_C3CONTROL_DWIDTH_MASK (0x7 << GPDMA_C3CONTROL_DWIDTH_SHIFT) -#define GPDMA_C3CONTROL_DWIDTH(x) ((x) << GPDMA_C3CONTROL_DWIDTH_SHIFT) - -/* S: Source AHB master select */ -#define GPDMA_C3CONTROL_S_SHIFT (24) -#define GPDMA_C3CONTROL_S_MASK (0x1 << GPDMA_C3CONTROL_S_SHIFT) -#define GPDMA_C3CONTROL_S(x) ((x) << GPDMA_C3CONTROL_S_SHIFT) - -/* D: Destination AHB master select */ -#define GPDMA_C3CONTROL_D_SHIFT (25) -#define GPDMA_C3CONTROL_D_MASK (0x1 << GPDMA_C3CONTROL_D_SHIFT) -#define GPDMA_C3CONTROL_D(x) ((x) << GPDMA_C3CONTROL_D_SHIFT) - -/* SI: Source increment */ -#define GPDMA_C3CONTROL_SI_SHIFT (26) -#define GPDMA_C3CONTROL_SI_MASK (0x1 << GPDMA_C3CONTROL_SI_SHIFT) -#define GPDMA_C3CONTROL_SI(x) ((x) << GPDMA_C3CONTROL_SI_SHIFT) - -/* DI: Destination increment */ -#define GPDMA_C3CONTROL_DI_SHIFT (27) -#define GPDMA_C3CONTROL_DI_MASK (0x1 << GPDMA_C3CONTROL_DI_SHIFT) -#define GPDMA_C3CONTROL_DI(x) ((x) << GPDMA_C3CONTROL_DI_SHIFT) - -/* PROT1: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode */ -#define GPDMA_C3CONTROL_PROT1_SHIFT (28) -#define GPDMA_C3CONTROL_PROT1_MASK (0x1 << GPDMA_C3CONTROL_PROT1_SHIFT) -#define GPDMA_C3CONTROL_PROT1(x) ((x) << GPDMA_C3CONTROL_PROT1_SHIFT) - -/* PROT2: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable */ -#define GPDMA_C3CONTROL_PROT2_SHIFT (29) -#define GPDMA_C3CONTROL_PROT2_MASK (0x1 << GPDMA_C3CONTROL_PROT2_SHIFT) -#define GPDMA_C3CONTROL_PROT2(x) ((x) << GPDMA_C3CONTROL_PROT2_SHIFT) - -/* PROT3: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable */ -#define GPDMA_C3CONTROL_PROT3_SHIFT (30) -#define GPDMA_C3CONTROL_PROT3_MASK (0x1 << GPDMA_C3CONTROL_PROT3_SHIFT) -#define GPDMA_C3CONTROL_PROT3(x) ((x) << GPDMA_C3CONTROL_PROT3_SHIFT) - -/* I: Terminal count interrupt enable bit */ -#define GPDMA_C3CONTROL_I_SHIFT (31) -#define GPDMA_C3CONTROL_I_MASK (0x1 << GPDMA_C3CONTROL_I_SHIFT) -#define GPDMA_C3CONTROL_I(x) ((x) << GPDMA_C3CONTROL_I_SHIFT) - -/* --- GPDMA_C4CONTROL values ----------------------------------- */ - -/* TRANSFERSIZE: Transfer size in number of transfers */ -#define GPDMA_C4CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C4CONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_C4CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C4CONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_C4CONTROL_TRANSFERSIZE_SHIFT) - -/* SBSIZE: Source burst size */ -#define GPDMA_C4CONTROL_SBSIZE_SHIFT (12) -#define GPDMA_C4CONTROL_SBSIZE_MASK (0x7 << GPDMA_C4CONTROL_SBSIZE_SHIFT) -#define GPDMA_C4CONTROL_SBSIZE(x) ((x) << GPDMA_C4CONTROL_SBSIZE_SHIFT) - -/* DBSIZE: Destination burst size */ -#define GPDMA_C4CONTROL_DBSIZE_SHIFT (15) -#define GPDMA_C4CONTROL_DBSIZE_MASK (0x7 << GPDMA_C4CONTROL_DBSIZE_SHIFT) -#define GPDMA_C4CONTROL_DBSIZE(x) ((x) << GPDMA_C4CONTROL_DBSIZE_SHIFT) - -/* SWIDTH: Source transfer width */ -#define GPDMA_C4CONTROL_SWIDTH_SHIFT (18) -#define GPDMA_C4CONTROL_SWIDTH_MASK (0x7 << GPDMA_C4CONTROL_SWIDTH_SHIFT) -#define GPDMA_C4CONTROL_SWIDTH(x) ((x) << GPDMA_C4CONTROL_SWIDTH_SHIFT) - -/* DWIDTH: Destination transfer width */ -#define GPDMA_C4CONTROL_DWIDTH_SHIFT (21) -#define GPDMA_C4CONTROL_DWIDTH_MASK (0x7 << GPDMA_C4CONTROL_DWIDTH_SHIFT) -#define GPDMA_C4CONTROL_DWIDTH(x) ((x) << GPDMA_C4CONTROL_DWIDTH_SHIFT) - -/* S: Source AHB master select */ -#define GPDMA_C4CONTROL_S_SHIFT (24) -#define GPDMA_C4CONTROL_S_MASK (0x1 << GPDMA_C4CONTROL_S_SHIFT) -#define GPDMA_C4CONTROL_S(x) ((x) << GPDMA_C4CONTROL_S_SHIFT) - -/* D: Destination AHB master select */ -#define GPDMA_C4CONTROL_D_SHIFT (25) -#define GPDMA_C4CONTROL_D_MASK (0x1 << GPDMA_C4CONTROL_D_SHIFT) -#define GPDMA_C4CONTROL_D(x) ((x) << GPDMA_C4CONTROL_D_SHIFT) - -/* SI: Source increment */ -#define GPDMA_C4CONTROL_SI_SHIFT (26) -#define GPDMA_C4CONTROL_SI_MASK (0x1 << GPDMA_C4CONTROL_SI_SHIFT) -#define GPDMA_C4CONTROL_SI(x) ((x) << GPDMA_C4CONTROL_SI_SHIFT) - -/* DI: Destination increment */ -#define GPDMA_C4CONTROL_DI_SHIFT (27) -#define GPDMA_C4CONTROL_DI_MASK (0x1 << GPDMA_C4CONTROL_DI_SHIFT) -#define GPDMA_C4CONTROL_DI(x) ((x) << GPDMA_C4CONTROL_DI_SHIFT) - -/* PROT1: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode */ -#define GPDMA_C4CONTROL_PROT1_SHIFT (28) -#define GPDMA_C4CONTROL_PROT1_MASK (0x1 << GPDMA_C4CONTROL_PROT1_SHIFT) -#define GPDMA_C4CONTROL_PROT1(x) ((x) << GPDMA_C4CONTROL_PROT1_SHIFT) - -/* PROT2: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable */ -#define GPDMA_C4CONTROL_PROT2_SHIFT (29) -#define GPDMA_C4CONTROL_PROT2_MASK (0x1 << GPDMA_C4CONTROL_PROT2_SHIFT) -#define GPDMA_C4CONTROL_PROT2(x) ((x) << GPDMA_C4CONTROL_PROT2_SHIFT) - -/* PROT3: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable */ -#define GPDMA_C4CONTROL_PROT3_SHIFT (30) -#define GPDMA_C4CONTROL_PROT3_MASK (0x1 << GPDMA_C4CONTROL_PROT3_SHIFT) -#define GPDMA_C4CONTROL_PROT3(x) ((x) << GPDMA_C4CONTROL_PROT3_SHIFT) - -/* I: Terminal count interrupt enable bit */ -#define GPDMA_C4CONTROL_I_SHIFT (31) -#define GPDMA_C4CONTROL_I_MASK (0x1 << GPDMA_C4CONTROL_I_SHIFT) -#define GPDMA_C4CONTROL_I(x) ((x) << GPDMA_C4CONTROL_I_SHIFT) - -/* --- GPDMA_C5CONTROL values ----------------------------------- */ - -/* TRANSFERSIZE: Transfer size in number of transfers */ -#define GPDMA_C5CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C5CONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_C5CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C5CONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_C5CONTROL_TRANSFERSIZE_SHIFT) - -/* SBSIZE: Source burst size */ -#define GPDMA_C5CONTROL_SBSIZE_SHIFT (12) -#define GPDMA_C5CONTROL_SBSIZE_MASK (0x7 << GPDMA_C5CONTROL_SBSIZE_SHIFT) -#define GPDMA_C5CONTROL_SBSIZE(x) ((x) << GPDMA_C5CONTROL_SBSIZE_SHIFT) - -/* DBSIZE: Destination burst size */ -#define GPDMA_C5CONTROL_DBSIZE_SHIFT (15) -#define GPDMA_C5CONTROL_DBSIZE_MASK (0x7 << GPDMA_C5CONTROL_DBSIZE_SHIFT) -#define GPDMA_C5CONTROL_DBSIZE(x) ((x) << GPDMA_C5CONTROL_DBSIZE_SHIFT) - -/* SWIDTH: Source transfer width */ -#define GPDMA_C5CONTROL_SWIDTH_SHIFT (18) -#define GPDMA_C5CONTROL_SWIDTH_MASK (0x7 << GPDMA_C5CONTROL_SWIDTH_SHIFT) -#define GPDMA_C5CONTROL_SWIDTH(x) ((x) << GPDMA_C5CONTROL_SWIDTH_SHIFT) - -/* DWIDTH: Destination transfer width */ -#define GPDMA_C5CONTROL_DWIDTH_SHIFT (21) -#define GPDMA_C5CONTROL_DWIDTH_MASK (0x7 << GPDMA_C5CONTROL_DWIDTH_SHIFT) -#define GPDMA_C5CONTROL_DWIDTH(x) ((x) << GPDMA_C5CONTROL_DWIDTH_SHIFT) - -/* S: Source AHB master select */ -#define GPDMA_C5CONTROL_S_SHIFT (24) -#define GPDMA_C5CONTROL_S_MASK (0x1 << GPDMA_C5CONTROL_S_SHIFT) -#define GPDMA_C5CONTROL_S(x) ((x) << GPDMA_C5CONTROL_S_SHIFT) - -/* D: Destination AHB master select */ -#define GPDMA_C5CONTROL_D_SHIFT (25) -#define GPDMA_C5CONTROL_D_MASK (0x1 << GPDMA_C5CONTROL_D_SHIFT) -#define GPDMA_C5CONTROL_D(x) ((x) << GPDMA_C5CONTROL_D_SHIFT) - -/* SI: Source increment */ -#define GPDMA_C5CONTROL_SI_SHIFT (26) -#define GPDMA_C5CONTROL_SI_MASK (0x1 << GPDMA_C5CONTROL_SI_SHIFT) -#define GPDMA_C5CONTROL_SI(x) ((x) << GPDMA_C5CONTROL_SI_SHIFT) - -/* DI: Destination increment */ -#define GPDMA_C5CONTROL_DI_SHIFT (27) -#define GPDMA_C5CONTROL_DI_MASK (0x1 << GPDMA_C5CONTROL_DI_SHIFT) -#define GPDMA_C5CONTROL_DI(x) ((x) << GPDMA_C5CONTROL_DI_SHIFT) - -/* PROT1: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode */ -#define GPDMA_C5CONTROL_PROT1_SHIFT (28) -#define GPDMA_C5CONTROL_PROT1_MASK (0x1 << GPDMA_C5CONTROL_PROT1_SHIFT) -#define GPDMA_C5CONTROL_PROT1(x) ((x) << GPDMA_C5CONTROL_PROT1_SHIFT) - -/* PROT2: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable */ -#define GPDMA_C5CONTROL_PROT2_SHIFT (29) -#define GPDMA_C5CONTROL_PROT2_MASK (0x1 << GPDMA_C5CONTROL_PROT2_SHIFT) -#define GPDMA_C5CONTROL_PROT2(x) ((x) << GPDMA_C5CONTROL_PROT2_SHIFT) - -/* PROT3: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable */ -#define GPDMA_C5CONTROL_PROT3_SHIFT (30) -#define GPDMA_C5CONTROL_PROT3_MASK (0x1 << GPDMA_C5CONTROL_PROT3_SHIFT) -#define GPDMA_C5CONTROL_PROT3(x) ((x) << GPDMA_C5CONTROL_PROT3_SHIFT) - -/* I: Terminal count interrupt enable bit */ -#define GPDMA_C5CONTROL_I_SHIFT (31) -#define GPDMA_C5CONTROL_I_MASK (0x1 << GPDMA_C5CONTROL_I_SHIFT) -#define GPDMA_C5CONTROL_I(x) ((x) << GPDMA_C5CONTROL_I_SHIFT) - -/* --- GPDMA_C6CONTROL values ----------------------------------- */ - -/* TRANSFERSIZE: Transfer size in number of transfers */ -#define GPDMA_C6CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C6CONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_C6CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C6CONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_C6CONTROL_TRANSFERSIZE_SHIFT) - -/* SBSIZE: Source burst size */ -#define GPDMA_C6CONTROL_SBSIZE_SHIFT (12) -#define GPDMA_C6CONTROL_SBSIZE_MASK (0x7 << GPDMA_C6CONTROL_SBSIZE_SHIFT) -#define GPDMA_C6CONTROL_SBSIZE(x) ((x) << GPDMA_C6CONTROL_SBSIZE_SHIFT) - -/* DBSIZE: Destination burst size */ -#define GPDMA_C6CONTROL_DBSIZE_SHIFT (15) -#define GPDMA_C6CONTROL_DBSIZE_MASK (0x7 << GPDMA_C6CONTROL_DBSIZE_SHIFT) -#define GPDMA_C6CONTROL_DBSIZE(x) ((x) << GPDMA_C6CONTROL_DBSIZE_SHIFT) - -/* SWIDTH: Source transfer width */ -#define GPDMA_C6CONTROL_SWIDTH_SHIFT (18) -#define GPDMA_C6CONTROL_SWIDTH_MASK (0x7 << GPDMA_C6CONTROL_SWIDTH_SHIFT) -#define GPDMA_C6CONTROL_SWIDTH(x) ((x) << GPDMA_C6CONTROL_SWIDTH_SHIFT) - -/* DWIDTH: Destination transfer width */ -#define GPDMA_C6CONTROL_DWIDTH_SHIFT (21) -#define GPDMA_C6CONTROL_DWIDTH_MASK (0x7 << GPDMA_C6CONTROL_DWIDTH_SHIFT) -#define GPDMA_C6CONTROL_DWIDTH(x) ((x) << GPDMA_C6CONTROL_DWIDTH_SHIFT) - -/* S: Source AHB master select */ -#define GPDMA_C6CONTROL_S_SHIFT (24) -#define GPDMA_C6CONTROL_S_MASK (0x1 << GPDMA_C6CONTROL_S_SHIFT) -#define GPDMA_C6CONTROL_S(x) ((x) << GPDMA_C6CONTROL_S_SHIFT) - -/* D: Destination AHB master select */ -#define GPDMA_C6CONTROL_D_SHIFT (25) -#define GPDMA_C6CONTROL_D_MASK (0x1 << GPDMA_C6CONTROL_D_SHIFT) -#define GPDMA_C6CONTROL_D(x) ((x) << GPDMA_C6CONTROL_D_SHIFT) - -/* SI: Source increment */ -#define GPDMA_C6CONTROL_SI_SHIFT (26) -#define GPDMA_C6CONTROL_SI_MASK (0x1 << GPDMA_C6CONTROL_SI_SHIFT) -#define GPDMA_C6CONTROL_SI(x) ((x) << GPDMA_C6CONTROL_SI_SHIFT) - -/* DI: Destination increment */ -#define GPDMA_C6CONTROL_DI_SHIFT (27) -#define GPDMA_C6CONTROL_DI_MASK (0x1 << GPDMA_C6CONTROL_DI_SHIFT) -#define GPDMA_C6CONTROL_DI(x) ((x) << GPDMA_C6CONTROL_DI_SHIFT) - -/* PROT1: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode */ -#define GPDMA_C6CONTROL_PROT1_SHIFT (28) -#define GPDMA_C6CONTROL_PROT1_MASK (0x1 << GPDMA_C6CONTROL_PROT1_SHIFT) -#define GPDMA_C6CONTROL_PROT1(x) ((x) << GPDMA_C6CONTROL_PROT1_SHIFT) - -/* PROT2: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or not - bufferable */ -#define GPDMA_C6CONTROL_PROT2_SHIFT (29) -#define GPDMA_C6CONTROL_PROT2_MASK (0x1 << GPDMA_C6CONTROL_PROT2_SHIFT) -#define GPDMA_C6CONTROL_PROT2(x) ((x) << GPDMA_C6CONTROL_PROT2_SHIFT) - -/* PROT3: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or - not cacheable */ -#define GPDMA_C6CONTROL_PROT3_SHIFT (30) -#define GPDMA_C6CONTROL_PROT3_MASK (0x1 << GPDMA_C6CONTROL_PROT3_SHIFT) -#define GPDMA_C6CONTROL_PROT3(x) ((x) << GPDMA_C6CONTROL_PROT3_SHIFT) - -/* I: Terminal count interrupt enable bit */ -#define GPDMA_C6CONTROL_I_SHIFT (31) -#define GPDMA_C6CONTROL_I_MASK (0x1 << GPDMA_C6CONTROL_I_SHIFT) -#define GPDMA_C6CONTROL_I(x) ((x) << GPDMA_C6CONTROL_I_SHIFT) - -/* --- GPDMA_C7CONTROL values ----------------------------------- */ - -/* TRANSFERSIZE: Transfer size in number of transfers */ -#define GPDMA_C7CONTROL_TRANSFERSIZE_SHIFT (0) -#define GPDMA_C7CONTROL_TRANSFERSIZE_MASK \ - (0xfff << GPDMA_C7CONTROL_TRANSFERSIZE_SHIFT) -#define GPDMA_C7CONTROL_TRANSFERSIZE(x) \ - ((x) << GPDMA_C7CONTROL_TRANSFERSIZE_SHIFT) - -/* SBSIZE: Source burst size */ -#define GPDMA_C7CONTROL_SBSIZE_SHIFT (12) -#define GPDMA_C7CONTROL_SBSIZE_MASK (0x7 << GPDMA_C7CONTROL_SBSIZE_SHIFT) -#define GPDMA_C7CONTROL_SBSIZE(x) ((x) << GPDMA_C7CONTROL_SBSIZE_SHIFT) - -/* DBSIZE: Destination burst size */ -#define GPDMA_C7CONTROL_DBSIZE_SHIFT (15) -#define GPDMA_C7CONTROL_DBSIZE_MASK (0x7 << GPDMA_C7CONTROL_DBSIZE_SHIFT) -#define GPDMA_C7CONTROL_DBSIZE(x) ((x) << GPDMA_C7CONTROL_DBSIZE_SHIFT) - -/* SWIDTH: Source transfer width */ -#define GPDMA_C7CONTROL_SWIDTH_SHIFT (18) -#define GPDMA_C7CONTROL_SWIDTH_MASK (0x7 << GPDMA_C7CONTROL_SWIDTH_SHIFT) -#define GPDMA_C7CONTROL_SWIDTH(x) ((x) << GPDMA_C7CONTROL_SWIDTH_SHIFT) - -/* DWIDTH: Destination transfer width */ -#define GPDMA_C7CONTROL_DWIDTH_SHIFT (21) -#define GPDMA_C7CONTROL_DWIDTH_MASK (0x7 << GPDMA_C7CONTROL_DWIDTH_SHIFT) -#define GPDMA_C7CONTROL_DWIDTH(x) ((x) << GPDMA_C7CONTROL_DWIDTH_SHIFT) - -/* S: Source AHB master select */ -#define GPDMA_C7CONTROL_S_SHIFT (24) -#define GPDMA_C7CONTROL_S_MASK (0x1 << GPDMA_C7CONTROL_S_SHIFT) -#define GPDMA_C7CONTROL_S(x) ((x) << GPDMA_C7CONTROL_S_SHIFT) - -/* D: Destination AHB master select */ -#define GPDMA_C7CONTROL_D_SHIFT (25) -#define GPDMA_C7CONTROL_D_MASK (0x1 << GPDMA_C7CONTROL_D_SHIFT) -#define GPDMA_C7CONTROL_D(x) ((x) << GPDMA_C7CONTROL_D_SHIFT) - -/* SI: Source increment */ -#define GPDMA_C7CONTROL_SI_SHIFT (26) -#define GPDMA_C7CONTROL_SI_MASK (0x1 << GPDMA_C7CONTROL_SI_SHIFT) -#define GPDMA_C7CONTROL_SI(x) ((x) << GPDMA_C7CONTROL_SI_SHIFT) - -/* DI: Destination increment */ -#define GPDMA_C7CONTROL_DI_SHIFT (27) -#define GPDMA_C7CONTROL_DI_MASK (0x1 << GPDMA_C7CONTROL_DI_SHIFT) -#define GPDMA_C7CONTROL_DI(x) ((x) << GPDMA_C7CONTROL_DI_SHIFT) - -/* PROT1: This information is provided to the peripheral during a DMA bus - access and indicates that the access is in user mode or privileged mode */ -#define GPDMA_C7CONTROL_PROT1_SHIFT (28) -#define GPDMA_C7CONTROL_PROT1_MASK (0x1 << GPDMA_C7CONTROL_PROT1_SHIFT) -#define GPDMA_C7CONTROL_PROT1(x) ((x) << GPDMA_C7CONTROL_PROT1_SHIFT) - -/* PROT2: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is bufferable or - not bufferable */ -#define GPDMA_C7CONTROL_PROT2_SHIFT (29) -#define GPDMA_C7CONTROL_PROT2_MASK (0x1 << GPDMA_C7CONTROL_PROT2_SHIFT) -#define GPDMA_C7CONTROL_PROT2(x) ((x) << GPDMA_C7CONTROL_PROT2_SHIFT) - -/* PROT3: This information is provided to the peripheral during a DMA bus - access and indicates to the peripheral that the access is cacheable or not - cacheable */ -#define GPDMA_C7CONTROL_PROT3_SHIFT (30) -#define GPDMA_C7CONTROL_PROT3_MASK (0x1 << GPDMA_C7CONTROL_PROT3_SHIFT) -#define GPDMA_C7CONTROL_PROT3(x) ((x) << GPDMA_C7CONTROL_PROT3_SHIFT) - -/* I: Terminal count interrupt enable bit */ -#define GPDMA_C7CONTROL_I_SHIFT (31) -#define GPDMA_C7CONTROL_I_MASK (0x1 << GPDMA_C7CONTROL_I_SHIFT) -#define GPDMA_C7CONTROL_I(x) ((x) << GPDMA_C7CONTROL_I_SHIFT) - -/* --- GPDMA_C0CONFIG values ------------------------------------ */ +/* --- GPDMA_C[0..7]CONFIG values ------------------------------------ */ /* E: Channel enable */ -#define GPDMA_C0CONFIG_E_SHIFT (0) -#define GPDMA_C0CONFIG_E_MASK (0x1 << GPDMA_C0CONFIG_E_SHIFT) -#define GPDMA_C0CONFIG_E(x) ((x) << GPDMA_C0CONFIG_E_SHIFT) +#define GPDMA_CxCONFIG_E_SHIFT (0) +#define GPDMA_CxCONFIG_E_MASK (0x1 << GPDMA_CxCONFIG_E_SHIFT) +#define GPDMA_CxCONFIG_E(x) ((x) << GPDMA_CxCONFIG_E_SHIFT) /* SRCPERIPHERAL: Source peripheral */ -#define GPDMA_C0CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C0CONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_C0CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C0CONFIG_SRCPERIPHERAL(x) - ((x) << GPDMA_C0CONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT (1) +#define GPDMA_CxCONFIG_SRCPERIPHERAL_MASK \ + (0x1f << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) +#define GPDMA_CxCONFIG_SRCPERIPHERAL(x) + ((x) << GPDMA_CxCONFIG_SRCPERIPHERAL_SHIFT) /* DESTPERIPHERAL: Destination peripheral */ -#define GPDMA_C0CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C0CONFIG_DESTPERIPHERAL_MASK - (0x1f << GPDMA_C0CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C0CONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_C0CONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT (6) +#define GPDMA_CxCONFIG_DESTPERIPHERAL_MASK + (0x1f << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) +#define GPDMA_CxCONFIG_DESTPERIPHERAL(x) \ + ((x) << GPDMA_CxCONFIG_DESTPERIPHERAL_SHIFT) /* FLOWCNTRL: Flow control and transfer type */ -#define GPDMA_C0CONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_C0CONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_C0CONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_C0CONFIG_FLOWCNTRL(x) ((x) << GPDMA_C0CONFIG_FLOWCNTRL_SHIFT) +#define GPDMA_CxCONFIG_FLOWCNTRL_SHIFT (11) +#define GPDMA_CxCONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) +#define GPDMA_CxCONFIG_FLOWCNTRL(x) ((x) << GPDMA_CxCONFIG_FLOWCNTRL_SHIFT) /* IE: Interrupt error mask */ -#define GPDMA_C0CONFIG_IE_SHIFT (14) -#define GPDMA_C0CONFIG_IE_MASK (0x1 << GPDMA_C0CONFIG_IE_SHIFT) -#define GPDMA_C0CONFIG_IE(x) ((x) << GPDMA_C0CONFIG_IE_SHIFT) +#define GPDMA_CxCONFIG_IE_SHIFT (14) +#define GPDMA_CxCONFIG_IE_MASK (0x1 << GPDMA_CxCONFIG_IE_SHIFT) +#define GPDMA_CxCONFIG_IE(x) ((x) << GPDMA_CxCONFIG_IE_SHIFT) /* ITC: Terminal count interrupt mask */ -#define GPDMA_C0CONFIG_ITC_SHIFT (15) -#define GPDMA_C0CONFIG_ITC_MASK (0x1 << GPDMA_C0CONFIG_ITC_SHIFT) -#define GPDMA_C0CONFIG_ITC(x) ((x) << GPDMA_C0CONFIG_ITC_SHIFT) +#define GPDMA_CxCONFIG_ITC_SHIFT (15) +#define GPDMA_CxCONFIG_ITC_MASK (0x1 << GPDMA_CxCONFIG_ITC_SHIFT) +#define GPDMA_CxCONFIG_ITC(x) ((x) << GPDMA_CxCONFIG_ITC_SHIFT) /* L: Lock */ -#define GPDMA_C0CONFIG_L_SHIFT (16) -#define GPDMA_C0CONFIG_L_MASK (0x1 << GPDMA_C0CONFIG_L_SHIFT) -#define GPDMA_C0CONFIG_L(x) ((x) << GPDMA_C0CONFIG_L_SHIFT) +#define GPDMA_CxCONFIG_L_SHIFT (16) +#define GPDMA_CxCONFIG_L_MASK (0x1 << GPDMA_CxCONFIG_L_SHIFT) +#define GPDMA_CxCONFIG_L(x) ((x) << GPDMA_CxCONFIG_L_SHIFT) /* A: Active */ -#define GPDMA_C0CONFIG_A_SHIFT (17) -#define GPDMA_C0CONFIG_A_MASK (0x1 << GPDMA_C0CONFIG_A_SHIFT) -#define GPDMA_C0CONFIG_A(x) ((x) << GPDMA_C0CONFIG_A_SHIFT) +#define GPDMA_CxCONFIG_A_SHIFT (17) +#define GPDMA_CxCONFIG_A_MASK (0x1 << GPDMA_CxCONFIG_A_SHIFT) +#define GPDMA_CxCONFIG_A(x) ((x) << GPDMA_CxCONFIG_A_SHIFT) /* H: Halt */ -#define GPDMA_C0CONFIG_H_SHIFT (18) -#define GPDMA_C0CONFIG_H_MASK (0x1 << GPDMA_C0CONFIG_H_SHIFT) -#define GPDMA_C0CONFIG_H(x) ((x) << GPDMA_C0CONFIG_H_SHIFT) - -/* --- GPDMA_C1CONFIG values ------------------------------------ */ - -/* E: Channel enable */ -#define GPDMA_C1CONFIG_E_SHIFT (0) -#define GPDMA_C1CONFIG_E_MASK (0x1 << GPDMA_C1CONFIG_E_SHIFT) -#define GPDMA_C1CONFIG_E(x) ((x) << GPDMA_C1CONFIG_E_SHIFT) - -/* SRCPERIPHERAL: Source peripheral */ -#define GPDMA_C1CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C1CONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_C1CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C1CONFIG_SRCPERIPHERAL(x) \ - ((x) << GPDMA_C1CONFIG_SRCPERIPHERAL_SHIFT) - -/* DESTPERIPHERAL: Destination peripheral */ -#define GPDMA_C1CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C1CONFIG_DESTPERIPHERAL_MASK \ - (0x1f << GPDMA_C1CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C1CONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_C1CONFIG_DESTPERIPHERAL_SHIFT) - -/* FLOWCNTRL: Flow control and transfer type */ -#define GPDMA_C1CONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_C1CONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_C1CONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_C1CONFIG_FLOWCNTRL(x) ((x) << GPDMA_C1CONFIG_FLOWCNTRL_SHIFT) - -/* IE: Interrupt error mask */ -#define GPDMA_C1CONFIG_IE_SHIFT (14) -#define GPDMA_C1CONFIG_IE_MASK (0x1 << GPDMA_C1CONFIG_IE_SHIFT) -#define GPDMA_C1CONFIG_IE(x) ((x) << GPDMA_C1CONFIG_IE_SHIFT) - -/* ITC: Terminal count interrupt mask */ -#define GPDMA_C1CONFIG_ITC_SHIFT (15) -#define GPDMA_C1CONFIG_ITC_MASK (0x1 << GPDMA_C1CONFIG_ITC_SHIFT) -#define GPDMA_C1CONFIG_ITC(x) ((x) << GPDMA_C1CONFIG_ITC_SHIFT) - -/* L: Lock */ -#define GPDMA_C1CONFIG_L_SHIFT (16) -#define GPDMA_C1CONFIG_L_MASK (0x1 << GPDMA_C1CONFIG_L_SHIFT) -#define GPDMA_C1CONFIG_L(x) ((x) << GPDMA_C1CONFIG_L_SHIFT) - -/* A: Active */ -#define GPDMA_C1CONFIG_A_SHIFT (17) -#define GPDMA_C1CONFIG_A_MASK (0x1 << GPDMA_C1CONFIG_A_SHIFT) -#define GPDMA_C1CONFIG_A(x) ((x) << GPDMA_C1CONFIG_A_SHIFT) - -/* H: Halt */ -#define GPDMA_C1CONFIG_H_SHIFT (18) -#define GPDMA_C1CONFIG_H_MASK (0x1 << GPDMA_C1CONFIG_H_SHIFT) -#define GPDMA_C1CONFIG_H(x) ((x) << GPDMA_C1CONFIG_H_SHIFT) - -/* --- GPDMA_C2CONFIG values ------------------------------------ */ - -/* E: Channel enable */ -#define GPDMA_C2CONFIG_E_SHIFT (0) -#define GPDMA_C2CONFIG_E_MASK (0x1 << GPDMA_C2CONFIG_E_SHIFT) -#define GPDMA_C2CONFIG_E(x) ((x) << GPDMA_C2CONFIG_E_SHIFT) - -/* SRCPERIPHERAL: Source peripheral */ -#define GPDMA_C2CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C2CONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_C2CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C2CONFIG_SRCPERIPHERAL(x) \ - ((x) << GPDMA_C2CONFIG_SRCPERIPHERAL_SHIFT) - -/* DESTPERIPHERAL: Destination peripheral */ -#define GPDMA_C2CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C2CONFIG_DESTPERIPHERAL_MASK \ - (0x1f << GPDMA_C2CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C2CONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_C2CONFIG_DESTPERIPHERAL_SHIFT) - -/* FLOWCNTRL: Flow control and transfer type */ -#define GPDMA_C2CONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_C2CONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_C2CONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_C2CONFIG_FLOWCNTRL(x) ((x) << GPDMA_C2CONFIG_FLOWCNTRL_SHIFT) - -/* IE: Interrupt error mask */ -#define GPDMA_C2CONFIG_IE_SHIFT (14) -#define GPDMA_C2CONFIG_IE_MASK (0x1 << GPDMA_C2CONFIG_IE_SHIFT) -#define GPDMA_C2CONFIG_IE(x) ((x) << GPDMA_C2CONFIG_IE_SHIFT) - -/* ITC: Terminal count interrupt mask */ -#define GPDMA_C2CONFIG_ITC_SHIFT (15) -#define GPDMA_C2CONFIG_ITC_MASK (0x1 << GPDMA_C2CONFIG_ITC_SHIFT) -#define GPDMA_C2CONFIG_ITC(x) ((x) << GPDMA_C2CONFIG_ITC_SHIFT) - -/* L: Lock */ -#define GPDMA_C2CONFIG_L_SHIFT (16) -#define GPDMA_C2CONFIG_L_MASK (0x1 << GPDMA_C2CONFIG_L_SHIFT) -#define GPDMA_C2CONFIG_L(x) ((x) << GPDMA_C2CONFIG_L_SHIFT) - -/* A: Active */ -#define GPDMA_C2CONFIG_A_SHIFT (17) -#define GPDMA_C2CONFIG_A_MASK (0x1 << GPDMA_C2CONFIG_A_SHIFT) -#define GPDMA_C2CONFIG_A(x) ((x) << GPDMA_C2CONFIG_A_SHIFT) - -/* H: Halt */ -#define GPDMA_C2CONFIG_H_SHIFT (18) -#define GPDMA_C2CONFIG_H_MASK (0x1 << GPDMA_C2CONFIG_H_SHIFT) -#define GPDMA_C2CONFIG_H(x) ((x) << GPDMA_C2CONFIG_H_SHIFT) - -/* --- GPDMA_C3CONFIG values ------------------------------------ */ - -/* E: Channel enable */ -#define GPDMA_C3CONFIG_E_SHIFT (0) -#define GPDMA_C3CONFIG_E_MASK (0x1 << GPDMA_C3CONFIG_E_SHIFT) -#define GPDMA_C3CONFIG_E(x) ((x) << GPDMA_C3CONFIG_E_SHIFT) - -/* SRCPERIPHERAL: Source peripheral */ -#define GPDMA_C3CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C3CONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_C3CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C3CONFIG_SRCPERIPHERAL(x) \ - ((x) << GPDMA_C3CONFIG_SRCPERIPHERAL_SHIFT) - -/* DESTPERIPHERAL: Destination peripheral */ -#define GPDMA_C3CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C3CONFIG_DESTPERIPHERAL_MASK \ - (0x1f << GPDMA_C3CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C3CONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_C3CONFIG_DESTPERIPHERAL_SHIFT) - -/* FLOWCNTRL: Flow control and transfer type */ -#define GPDMA_C3CONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_C3CONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_C3CONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_C3CONFIG_FLOWCNTRL(x) ((x) << GPDMA_C3CONFIG_FLOWCNTRL_SHIFT) - -/* IE: Interrupt error mask */ -#define GPDMA_C3CONFIG_IE_SHIFT (14) -#define GPDMA_C3CONFIG_IE_MASK (0x1 << GPDMA_C3CONFIG_IE_SHIFT) -#define GPDMA_C3CONFIG_IE(x) ((x) << GPDMA_C3CONFIG_IE_SHIFT) - -/* ITC: Terminal count interrupt mask */ -#define GPDMA_C3CONFIG_ITC_SHIFT (15) -#define GPDMA_C3CONFIG_ITC_MASK (0x1 << GPDMA_C3CONFIG_ITC_SHIFT) -#define GPDMA_C3CONFIG_ITC(x) ((x) << GPDMA_C3CONFIG_ITC_SHIFT) - -/* L: Lock */ -#define GPDMA_C3CONFIG_L_SHIFT (16) -#define GPDMA_C3CONFIG_L_MASK (0x1 << GPDMA_C3CONFIG_L_SHIFT) -#define GPDMA_C3CONFIG_L(x) ((x) << GPDMA_C3CONFIG_L_SHIFT) - -/* A: Active */ -#define GPDMA_C3CONFIG_A_SHIFT (17) -#define GPDMA_C3CONFIG_A_MASK (0x1 << GPDMA_C3CONFIG_A_SHIFT) -#define GPDMA_C3CONFIG_A(x) ((x) << GPDMA_C3CONFIG_A_SHIFT) - -/* H: Halt */ -#define GPDMA_C3CONFIG_H_SHIFT (18) -#define GPDMA_C3CONFIG_H_MASK (0x1 << GPDMA_C3CONFIG_H_SHIFT) -#define GPDMA_C3CONFIG_H(x) ((x) << GPDMA_C3CONFIG_H_SHIFT) - -/* --- GPDMA_C4CONFIG values ------------------------------------ */ - -/* E: Channel enable */ -#define GPDMA_C4CONFIG_E_SHIFT (0) -#define GPDMA_C4CONFIG_E_MASK (0x1 << GPDMA_C4CONFIG_E_SHIFT) -#define GPDMA_C4CONFIG_E(x) ((x) << GPDMA_C4CONFIG_E_SHIFT) - -/* SRCPERIPHERAL: Source peripheral */ -#define GPDMA_C4CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C4CONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_C4CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C4CONFIG_SRCPERIPHERAL(x) \ - ((x) << GPDMA_C4CONFIG_SRCPERIPHERAL_SHIFT) - -/* DESTPERIPHERAL: Destination peripheral */ -#define GPDMA_C4CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C4CONFIG_DESTPERIPHERAL_MASK \ - (0x1f << GPDMA_C4CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C4CONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_C4CONFIG_DESTPERIPHERAL_SHIFT) - -/* FLOWCNTRL: Flow control and transfer type */ -#define GPDMA_C4CONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_C4CONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_C4CONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_C4CONFIG_FLOWCNTRL(x) ((x) << GPDMA_C4CONFIG_FLOWCNTRL_SHIFT) - -/* IE: Interrupt error mask */ -#define GPDMA_C4CONFIG_IE_SHIFT (14) -#define GPDMA_C4CONFIG_IE_MASK (0x1 << GPDMA_C4CONFIG_IE_SHIFT) -#define GPDMA_C4CONFIG_IE(x) ((x) << GPDMA_C4CONFIG_IE_SHIFT) - -/* ITC: Terminal count interrupt mask */ -#define GPDMA_C4CONFIG_ITC_SHIFT (15) -#define GPDMA_C4CONFIG_ITC_MASK (0x1 << GPDMA_C4CONFIG_ITC_SHIFT) -#define GPDMA_C4CONFIG_ITC(x) ((x) << GPDMA_C4CONFIG_ITC_SHIFT) - -/* L: Lock */ -#define GPDMA_C4CONFIG_L_SHIFT (16) -#define GPDMA_C4CONFIG_L_MASK (0x1 << GPDMA_C4CONFIG_L_SHIFT) -#define GPDMA_C4CONFIG_L(x) ((x) << GPDMA_C4CONFIG_L_SHIFT) - -/* A: Active */ -#define GPDMA_C4CONFIG_A_SHIFT (17) -#define GPDMA_C4CONFIG_A_MASK (0x1 << GPDMA_C4CONFIG_A_SHIFT) -#define GPDMA_C4CONFIG_A(x) ((x) << GPDMA_C4CONFIG_A_SHIFT) - -/* H: Halt */ -#define GPDMA_C4CONFIG_H_SHIFT (18) -#define GPDMA_C4CONFIG_H_MASK (0x1 << GPDMA_C4CONFIG_H_SHIFT) -#define GPDMA_C4CONFIG_H(x) ((x) << GPDMA_C4CONFIG_H_SHIFT) - -/* --- GPDMA_C5CONFIG values ------------------------------------ */ - -/* E: Channel enable */ -#define GPDMA_C5CONFIG_E_SHIFT (0) -#define GPDMA_C5CONFIG_E_MASK (0x1 << GPDMA_C5CONFIG_E_SHIFT) -#define GPDMA_C5CONFIG_E(x) ((x) << GPDMA_C5CONFIG_E_SHIFT) - -/* SRCPERIPHERAL: Source peripheral */ -#define GPDMA_C5CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C5CONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_C5CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C5CONFIG_SRCPERIPHERAL(x) \ - ((x) << GPDMA_C5CONFIG_SRCPERIPHERAL_SHIFT) - -/* DESTPERIPHERAL: Destination peripheral */ -#define GPDMA_C5CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C5CONFIG_DESTPERIPHERAL_MASK \ - (0x1f << GPDMA_C5CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C5CONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_C5CONFIG_DESTPERIPHERAL_SHIFT) - -/* FLOWCNTRL: Flow control and transfer type */ -#define GPDMA_C5CONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_C5CONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_C5CONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_C5CONFIG_FLOWCNTRL(x) ((x) << GPDMA_C5CONFIG_FLOWCNTRL_SHIFT) - -/* IE: Interrupt error mask */ -#define GPDMA_C5CONFIG_IE_SHIFT (14) -#define GPDMA_C5CONFIG_IE_MASK (0x1 << GPDMA_C5CONFIG_IE_SHIFT) -#define GPDMA_C5CONFIG_IE(x) ((x) << GPDMA_C5CONFIG_IE_SHIFT) - -/* ITC: Terminal count interrupt mask */ -#define GPDMA_C5CONFIG_ITC_SHIFT (15) -#define GPDMA_C5CONFIG_ITC_MASK (0x1 << GPDMA_C5CONFIG_ITC_SHIFT) -#define GPDMA_C5CONFIG_ITC(x) ((x) << GPDMA_C5CONFIG_ITC_SHIFT) - -/* L: Lock */ -#define GPDMA_C5CONFIG_L_SHIFT (16) -#define GPDMA_C5CONFIG_L_MASK (0x1 << GPDMA_C5CONFIG_L_SHIFT) -#define GPDMA_C5CONFIG_L(x) ((x) << GPDMA_C5CONFIG_L_SHIFT) - -/* A: Active */ -#define GPDMA_C5CONFIG_A_SHIFT (17) -#define GPDMA_C5CONFIG_A_MASK (0x1 << GPDMA_C5CONFIG_A_SHIFT) -#define GPDMA_C5CONFIG_A(x) ((x) << GPDMA_C5CONFIG_A_SHIFT) - -/* H: Halt */ -#define GPDMA_C5CONFIG_H_SHIFT (18) -#define GPDMA_C5CONFIG_H_MASK (0x1 << GPDMA_C5CONFIG_H_SHIFT) -#define GPDMA_C5CONFIG_H(x) ((x) << GPDMA_C5CONFIG_H_SHIFT) - -/* --- GPDMA_C6CONFIG values ------------------------------------ */ - -/* E: Channel enable */ -#define GPDMA_C6CONFIG_E_SHIFT (0) -#define GPDMA_C6CONFIG_E_MASK (0x1 << GPDMA_C6CONFIG_E_SHIFT) -#define GPDMA_C6CONFIG_E(x) ((x) << GPDMA_C6CONFIG_E_SHIFT) - -/* SRCPERIPHERAL: Source peripheral */ -#define GPDMA_C6CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C6CONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_C6CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C6CONFIG_SRCPERIPHERAL(x) \ - ((x) << GPDMA_C6CONFIG_SRCPERIPHERAL_SHIFT) - -/* DESTPERIPHERAL: Destination peripheral */ -#define GPDMA_C6CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C6CONFIG_DESTPERIPHERAL_MASK \ - (0x1f << GPDMA_C6CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C6CONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_C6CONFIG_DESTPERIPHERAL_SHIFT) - -/* FLOWCNTRL: Flow control and transfer type */ -#define GPDMA_C6CONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_C6CONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_C6CONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_C6CONFIG_FLOWCNTRL(x) ((x) << GPDMA_C6CONFIG_FLOWCNTRL_SHIFT) - -/* IE: Interrupt error mask */ -#define GPDMA_C6CONFIG_IE_SHIFT (14) -#define GPDMA_C6CONFIG_IE_MASK (0x1 << GPDMA_C6CONFIG_IE_SHIFT) -#define GPDMA_C6CONFIG_IE(x) ((x) << GPDMA_C6CONFIG_IE_SHIFT) - -/* ITC: Terminal count interrupt mask */ -#define GPDMA_C6CONFIG_ITC_SHIFT (15) -#define GPDMA_C6CONFIG_ITC_MASK (0x1 << GPDMA_C6CONFIG_ITC_SHIFT) -#define GPDMA_C6CONFIG_ITC(x) ((x) << GPDMA_C6CONFIG_ITC_SHIFT) - -/* L: Lock */ -#define GPDMA_C6CONFIG_L_SHIFT (16) -#define GPDMA_C6CONFIG_L_MASK (0x1 << GPDMA_C6CONFIG_L_SHIFT) -#define GPDMA_C6CONFIG_L(x) ((x) << GPDMA_C6CONFIG_L_SHIFT) - -/* A: Active */ -#define GPDMA_C6CONFIG_A_SHIFT (17) -#define GPDMA_C6CONFIG_A_MASK (0x1 << GPDMA_C6CONFIG_A_SHIFT) -#define GPDMA_C6CONFIG_A(x) ((x) << GPDMA_C6CONFIG_A_SHIFT) - -/* H: Halt */ -#define GPDMA_C6CONFIG_H_SHIFT (18) -#define GPDMA_C6CONFIG_H_MASK (0x1 << GPDMA_C6CONFIG_H_SHIFT) -#define GPDMA_C6CONFIG_H(x) ((x) << GPDMA_C6CONFIG_H_SHIFT) - -/* --- GPDMA_C7CONFIG values ------------------------------------ */ - -/* E: Channel enable */ -#define GPDMA_C7CONFIG_E_SHIFT (0) -#define GPDMA_C7CONFIG_E_MASK (0x1 << GPDMA_C7CONFIG_E_SHIFT) -#define GPDMA_C7CONFIG_E(x) ((x) << GPDMA_C7CONFIG_E_SHIFT) - -/* SRCPERIPHERAL: Source peripheral */ -#define GPDMA_C7CONFIG_SRCPERIPHERAL_SHIFT (1) -#define GPDMA_C7CONFIG_SRCPERIPHERAL_MASK \ - (0x1f << GPDMA_C7CONFIG_SRCPERIPHERAL_SHIFT) -#define GPDMA_C7CONFIG_SRCPERIPHERAL(x) \ - ((x) << GPDMA_C7CONFIG_SRCPERIPHERAL_SHIFT) - -/* DESTPERIPHERAL: Destination peripheral */ -#define GPDMA_C7CONFIG_DESTPERIPHERAL_SHIFT (6) -#define GPDMA_C7CONFIG_DESTPERIPHERAL_MASK \ - (0x1f << GPDMA_C7CONFIG_DESTPERIPHERAL_SHIFT) -#define GPDMA_C7CONFIG_DESTPERIPHERAL(x) \ - ((x) << GPDMA_C7CONFIG_DESTPERIPHERAL_SHIFT) - -/* FLOWCNTRL: Flow control and transfer type */ -#define GPDMA_C7CONFIG_FLOWCNTRL_SHIFT (11) -#define GPDMA_C7CONFIG_FLOWCNTRL_MASK (0x7 << GPDMA_C7CONFIG_FLOWCNTRL_SHIFT) -#define GPDMA_C7CONFIG_FLOWCNTRL(x) ((x) << GPDMA_C7CONFIG_FLOWCNTRL_SHIFT) - -/* IE: Interrupt error mask */ -#define GPDMA_C7CONFIG_IE_SHIFT (14) -#define GPDMA_C7CONFIG_IE_MASK (0x1 << GPDMA_C7CONFIG_IE_SHIFT) -#define GPDMA_C7CONFIG_IE(x) ((x) << GPDMA_C7CONFIG_IE_SHIFT) - -/* ITC: Terminal count interrupt mask */ -#define GPDMA_C7CONFIG_ITC_SHIFT (15) -#define GPDMA_C7CONFIG_ITC_MASK (0x1 << GPDMA_C7CONFIG_ITC_SHIFT) -#define GPDMA_C7CONFIG_ITC(x) ((x) << GPDMA_C7CONFIG_ITC_SHIFT) - -/* L: Lock */ -#define GPDMA_C7CONFIG_L_SHIFT (16) -#define GPDMA_C7CONFIG_L_MASK (0x1 << GPDMA_C7CONFIG_L_SHIFT) -#define GPDMA_C7CONFIG_L(x) ((x) << GPDMA_C7CONFIG_L_SHIFT) - -/* A: Active */ -#define GPDMA_C7CONFIG_A_SHIFT (17) -#define GPDMA_C7CONFIG_A_MASK (0x1 << GPDMA_C7CONFIG_A_SHIFT) -#define GPDMA_C7CONFIG_A(x) ((x) << GPDMA_C7CONFIG_A_SHIFT) - -/* H: Halt */ -#define GPDMA_C7CONFIG_H_SHIFT (18) -#define GPDMA_C7CONFIG_H_MASK (0x1 << GPDMA_C7CONFIG_H_SHIFT) -#define GPDMA_C7CONFIG_H(x) ((x) << GPDMA_C7CONFIG_H_SHIFT) - +#define GPDMA_CxCONFIG_H_SHIFT (18) +#define GPDMA_CxCONFIG_H_MASK (0x1 << GPDMA_CxCONFIG_H_SHIFT) +#define GPDMA_CxCONFIG_H(x) ((x) << GPDMA_CxCONFIG_H_SHIFT) /**@}*/ diff --git a/include/libopencm3/lpc43xx/gpio.h b/include/libopencm3/lpc43xx/gpio.h index 78e94bdb..67474707 100644 --- a/include/libopencm3/lpc43xx/gpio.h +++ b/include/libopencm3/lpc43xx/gpio.h @@ -126,69 +126,13 @@ LGPL License Terms @ref lgpl_license #define GPIO_GROUP0_INTERRUPT_CTRL \ MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x000) -/* GPIO grouped interrupt port 0 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL0 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020) +/* GPIO grouped interrupt port [0..7] polarity register */ +#define GPIO_GROUP0_INTERRUPT_PORT_POL(x) \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x020 + ((x)*4)) -/* GPIO grouped interrupt port 1 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL1 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x024) - -/* GPIO grouped interrupt port 2 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL2 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x028) - -/* GPIO grouped interrupt port 3 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL3 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x02C) - -/* GPIO grouped interrupt port 4 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL4 - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x030) - -/* GPIO grouped interrupt port 5 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL5 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x034) - -/* GPIO grouped interrupt port 6 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL6 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x038) - -/* GPIO grouped interrupt port 7 polarity register */ -#define GPIO_GROUP0_INTERRUPT_PORT_POL7 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x03C) - -/* GPIO grouped interrupt port 0 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA0 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040) - -/* GPIO grouped interrupt port 1 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA1 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x044) - -/* GPIO grouped interrupt port 2 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA2 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x048) - -/* GPIO grouped interrupt port 3 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA3 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x04C) - -/* GPIO grouped interrupt port 4 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA4 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x050) - -/* GPIO grouped interrupt port 5 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA5 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x054) - -/* GPIO grouped interrupt port 6 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA6 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x058) - -/* GPIO grouped interrupt port 7 enable register */ -#define GPIO_GROUP0_INTERRUPT_PORT_ENA7 \ - MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x05C) +/* GPIO grouped interrupt port [0..7] enable register */ +#define GPIO_GROUP0_INTERRUPT_PORT_ENA(x) \ + MMIO32(GPIO_GROUP0_INTERRUPT_BASE + 0x040 + ((x)*4)) /* GPIO GROUP1 interrupt */ @@ -196,69 +140,13 @@ LGPL License Terms @ref lgpl_license #define GPIO_GROUP1_INTERRUPT_CTRL \ MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x000) -/* GPIO grouped interrupt port 0 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL0 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020) +/* GPIO grouped interrupt port [0..7] polarity register */ +#define GPIO_GROUP1_INTERRUPT_PORT_POL(x) \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x020 + ((x)*4)) -/* GPIO grouped interrupt port 1 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL1 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x024) - -/* GPIO grouped interrupt port 2 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL2 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x028) - -/* GPIO grouped interrupt port 3 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL3 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x02C) - -/* GPIO grouped interrupt port 4 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL4 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x030) - -/* GPIO grouped interrupt port 5 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL5 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x034) - -/* GPIO grouped interrupt port 6 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL6 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x038) - -/* GPIO grouped interrupt port 7 polarity register */ -#define GPIO_GROUP1_INTERRUPT_PORT_POL7 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x03C) - -/* GPIO grouped interrupt port 0 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA0 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040) - -/* GPIO grouped interrupt port 1 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA1 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x044) - -/* GPIO grouped interrupt port 2 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA2 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x048) - -/* GPIO grouped interrupt port 3 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA3 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x04C) - -/* GPIO grouped interrupt port 4 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA4 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x050) - -/* GPIO grouped interrupt port 5 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA5 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x054) - -/* GPIO grouped interrupt port 6 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA6 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x058) - -/* GPIO grouped interrupt port 7 enable register */ -#define GPIO_GROUP1_INTERRUPT_PORT_ENA7 \ - MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x05C) +/* GPIO grouped interrupt port [0..7] enable register */ +#define GPIO_GROUP1_INTERRUPT_PORT_ENA(x) \ + MMIO32(GPIO_GROUP1_INTERRUPT_BASE + 0x040 + ((x)*4)) /* Byte pin registers port 0; pins PIO0_0 to PIO0_31 (R/W) */ #define GPIO_B0 (GPIO_PORT_BASE + 0x0000) diff --git a/include/libopencm3/lpc43xx/sgpio.h b/include/libopencm3/lpc43xx/sgpio.h index 82dbcee6..4c8cebbb 100644 --- a/include/libopencm3/lpc43xx/sgpio.h +++ b/include/libopencm3/lpc43xx/sgpio.h @@ -449,1665 +449,130 @@ LGPL License Terms @ref lgpl_license /* --- AUTO-GENERATED STUFF FOLLOWS ----------------------------- */ -/* --- SGPIO_OUT_MUX_CFG0 values -------------------------------- */ +/* --- SGPIO_OUT_MUX_CFG[0..15] values ------------------------------------ */ /* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG0_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG0_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT (0) +#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG_MASK \ + (0xf << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFGx_P_OUT_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFGx_P_OUT_CFG_SHIFT) /* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG0_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG0_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG0_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT (4) +#define SGPIO_OUT_MUX_CFGx_P_OE_CFG_MASK \ + (0x7 << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) +#define SGPIO_OUT_MUX_CFGx_P_OE_CFG(x) \ + ((x) << SGPIO_OUT_MUX_CFGx_P_OE_CFG_SHIFT) -/* --- SGPIO_OUT_MUX_CFG1 values -------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG1_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG1_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG1_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG1_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG1_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG2 values -------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG2_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG2_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG2_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG2_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG2_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG3 values -------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG3_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG3_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG3_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG3_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG3_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG4 values -------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG4_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG4_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG4_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG4_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG4_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG5 values -------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG5_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG5_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG5_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG5_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG5_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG6 values -------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG6_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG6_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG6_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG6_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG6_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG7 values -------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG7_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG7_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG7_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG7_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG7_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG8 values -------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG8_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG8_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG8_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG8_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG8_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG9 values -------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG9_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG9_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG9_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG9_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG9_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG10 values ------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG10_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG10_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG10_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG10_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG10_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG11 values ------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG11_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG11_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG11_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG11_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG11_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG12 values ------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG12_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG12_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG12_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG12_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG12_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG13 values ------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG13_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG13_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG13_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG13_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG13_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG14 values ------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG14_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG14_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG14_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG14_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG14_P_OE_CFG_SHIFT) - -/* --- SGPIO_OUT_MUX_CFG15 values ------------------------------- */ - -/* P_OUT_CFG: Output control of output SGPIOn */ -#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT (0) -#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG_MASK \ - (0xf << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG15_P_OUT_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG15_P_OUT_CFG_SHIFT) - -/* P_OE_CFG: Output enable source */ -#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT (4) -#define SGPIO_OUT_MUX_CFG15_P_OE_CFG_MASK \ - (0x7 << SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT) -#define SGPIO_OUT_MUX_CFG15_P_OE_CFG(x) \ - ((x) << SGPIO_OUT_MUX_CFG15_P_OE_CFG_SHIFT) - -/* --- SGPIO_MUX_CFG0 values ------------------------------------ */ +/* --- SGPIO_MUX_CFG[0..15] values ---------------------------------------- */ /* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG0_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG0_EXT_CLK_ENABLE \ - (1 << SGPIO_MUX_CFG0_EXT_CLK_ENABLE_SHIFT) +#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT (0) +#define SGPIO_MUX_CFGx_EXT_CLK_ENABLE \ + (1 << SGPIO_MUX_CFGx_EXT_CLK_ENABLE_SHIFT) /* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG0_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT (1) +#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_PIN_MODE_SHIFT) /* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE(x) - ((x) << SGPIO_MUX_CFG0_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3) +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x) + ((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT) /* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG0_QUALIFIER_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG0_QUALIFIER_MODE(x) \ - ((x) << SGPIO_MUX_CFG0_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT (5) +#define SGPIO_MUX_CFGx_QUALIFIER_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_QUALIFIER_MODE_SHIFT) /* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG0_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT (7) +#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE(x) \ + ((x) << SGPIO_MUX_CFGx_QUALIFIER_PIN_MODE_SHIFT) /* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE(x) \ +#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT (9) +#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_MASK \ + (0x3 << SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE_SHIFT) +#define SGPIO_MUX_CFGx_QUALIFIER_SLICE_MODE(x) \ ((x) << SGPIO_MUX_CFG0_QUALIFIER_SLICE_MODE_SHIFT) /* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG0_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG0_CONCAT_ENABLE (1 << SGPIO_MUX_CFG0_CONCAT_ENABLE_SHIFT) +#define SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT (11) +#define SGPIO_MUX_CFGx_CONCAT_ENABLE \ + (1 << SGPIO_MUX_CFGx_CONCAT_ENABLE_SHIFT) /* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG0_CONCAT_ORDER_MASK \ - (0x3 << SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG0_CONCAT_ORDER(x) \ - ((x) << SGPIO_MUX_CFG0_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT (12) +#define SGPIO_MUX_CFGx_CONCAT_ORDER_MASK \ + (0x3 << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) +#define SGPIO_MUX_CFGx_CONCAT_ORDER(x) \ + ((x) << SGPIO_MUX_CFGx_CONCAT_ORDER_SHIFT) -/* --- SGPIO_MUX_CFG1 values ------------------------------------ */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG1_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG1_EXT_CLK_ENABLE \ - (1 << SGPIO_MUX_CFG1_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG1_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG1_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG1_QUALIFIER_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG1_QUALIFIER_MODE(x) \ - ((x) << SGPIO_MUX_CFG1_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG1_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG1_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG1_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG1_CONCAT_ENABLE \ - (1 << SGPIO_MUX_CFG1_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG1_CONCAT_ORDER_MASK \ - (0x3 << SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG1_CONCAT_ORDER(x) \ - ((x) << SGPIO_MUX_CFG1_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG2 values ------------------------------------ */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG2_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG2_EXT_CLK_ENABLE \ - (1 << SGPIO_MUX_CFG2_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG2_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG2_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG2_QUALIFIER_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG2_QUALIFIER_MODE(x) \ - ((x) << SGPIO_MUX_CFG2_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG2_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG2_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG2_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG2_CONCAT_ENABLE - (1 << SGPIO_MUX_CFG2_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG2_CONCAT_ORDER_MASK \ - (0x3 << SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG2_CONCAT_ORDER(x) \ - ((x) << SGPIO_MUX_CFG2_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG3 values ------------------------------------ */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG3_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG3_EXT_CLK_ENABLE \ - (1 << SGPIO_MUX_CFG3_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG3_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG3_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG3_QUALIFIER_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG3_QUALIFIER_MODE(x) \ - ((x) << SGPIO_MUX_CFG3_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG3_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG3_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG3_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG3_CONCAT_ENABLE \ - (1 << SGPIO_MUX_CFG3_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG3_CONCAT_ORDER_MASK \ - (0x3 << SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG3_CONCAT_ORDER(x) \ - ((x) << SGPIO_MUX_CFG3_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG4 values ------------------------------------ */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG4_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG4_EXT_CLK_ENABLE \ - (1 << SGPIO_MUX_CFG4_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE(x) \ - ((x) << SGPIO_MUX_CFG4_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_MASK \ - (0x3 << SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE(x) \ - ((x) << SGPIO_MUX_CFG4_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG4_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG4_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG4_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG4_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG4_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG4_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG4_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG4_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG4_CONCAT_ENABLE (1 << SGPIO_MUX_CFG4_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG4_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG4_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG4_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG4_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG4_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG5 values ------------------------------------ */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG5_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG5_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG5_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG5_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG5_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG5_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG5_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG5_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG5_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG5_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG5_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG5_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG5_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG5_CONCAT_ENABLE (1 << SGPIO_MUX_CFG5_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG5_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG5_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG5_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG5_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG5_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG6 values ------------------------------------ */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG6_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG6_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG6_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG6_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG6_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG6_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG6_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG6_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG6_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG6_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG6_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG6_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG6_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG6_CONCAT_ENABLE (1 << SGPIO_MUX_CFG6_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG6_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG6_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG6_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG6_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG6_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG7 values ------------------------------------ */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG7_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG7_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG7_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG7_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG7_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG7_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG7_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG7_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG7_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG7_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG7_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG7_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG7_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG7_CONCAT_ENABLE (1 << SGPIO_MUX_CFG7_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG7_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG7_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG7_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG7_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG7_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG8 values ------------------------------------ */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG8_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG8_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG8_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG8_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG8_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG8_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG8_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG8_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG8_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG8_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG8_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG8_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG8_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG8_CONCAT_ENABLE (1 << SGPIO_MUX_CFG8_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG8_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG8_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG8_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG8_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG8_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG9 values ------------------------------------ */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG9_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG9_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG9_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG9_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG9_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG9_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG9_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG9_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG9_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG9_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG9_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG9_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG9_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG9_CONCAT_ENABLE (1 << SGPIO_MUX_CFG9_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG9_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG9_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG9_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG9_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG9_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG10 values ----------------------------------- */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG10_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG10_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG10_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG10_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG10_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG10_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG10_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG10_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG10_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG10_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG10_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG10_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG10_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG10_CONCAT_ENABLE (1 << SGPIO_MUX_CFG10_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG10_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG10_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG10_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG10_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG10_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG11 values ----------------------------------- */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG11_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG11_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG11_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG11_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG11_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG11_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG11_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG11_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG11_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG11_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG11_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG11_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG11_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG11_CONCAT_ENABLE (1 << SGPIO_MUX_CFG11_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG11_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG11_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG11_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG11_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG11_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG12 values ----------------------------------- */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG12_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG12_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG12_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG12_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG12_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG12_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG12_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG12_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG12_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG12_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG12_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG12_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG12_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG12_CONCAT_ENABLE (1 << SGPIO_MUX_CFG12_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG12_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG12_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG12_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG12_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG12_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG13 values ----------------------------------- */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG13_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG13_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG13_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG13_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG13_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG13_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG13_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG13_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG13_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG13_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG13_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG13_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG13_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG13_CONCAT_ENABLE (1 << SGPIO_MUX_CFG13_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG13_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG13_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG13_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG13_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG13_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG14 values ----------------------------------- */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG14_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG14_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG14_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG14_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG14_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG14_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG14_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG14_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG14_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG14_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG14_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG14_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG14_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG14_CONCAT_ENABLE (1 << SGPIO_MUX_CFG14_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG14_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG14_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG14_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG14_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG14_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_MUX_CFG15 values ----------------------------------- */ - -/* EXT_CLK_ENABLE: Select clock signal */ -#define SGPIO_MUX_CFG15_EXT_CLK_ENABLE_SHIFT (0) -#define SGPIO_MUX_CFG15_EXT_CLK_ENABLE (1 << SGPIO_MUX_CFG15_EXT_CLK_ENABLE_SHIFT) - -/* CLK_SOURCE_PIN_MODE: Select source clock pin */ -#define SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_SHIFT (1) -#define SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE(x) ((x) << SGPIO_MUX_CFG15_CLK_SOURCE_PIN_MODE_SHIFT) - -/* CLK_SOURCE_SLICE_MODE: Select clock source slice */ -#define SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_SHIFT (3) -#define SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG15_CLK_SOURCE_SLICE_MODE_SHIFT) - -/* QUALIFIER_MODE: Select qualifier mode */ -#define SGPIO_MUX_CFG15_QUALIFIER_MODE_SHIFT (5) -#define SGPIO_MUX_CFG15_QUALIFIER_MODE_MASK (0x3 << SGPIO_MUX_CFG15_QUALIFIER_MODE_SHIFT) -#define SGPIO_MUX_CFG15_QUALIFIER_MODE(x) ((x) << SGPIO_MUX_CFG15_QUALIFIER_MODE_SHIFT) - -/* QUALIFIER_PIN_MODE: Select qualifier pin */ -#define SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_SHIFT (7) -#define SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_MASK (0x3 << SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_SHIFT) -#define SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE(x) ((x) << SGPIO_MUX_CFG15_QUALIFIER_PIN_MODE_SHIFT) - -/* QUALIFIER_SLICE_MODE: Select qualifier slice */ -#define SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_SHIFT (9) -#define SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_MASK (0x3 << SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_SHIFT) -#define SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE(x) ((x) << SGPIO_MUX_CFG15_QUALIFIER_SLICE_MODE_SHIFT) - -/* CONCAT_ENABLE: Enable concatenation */ -#define SGPIO_MUX_CFG15_CONCAT_ENABLE_SHIFT (11) -#define SGPIO_MUX_CFG15_CONCAT_ENABLE (1 << SGPIO_MUX_CFG15_CONCAT_ENABLE_SHIFT) - -/* CONCAT_ORDER: Select concatenation order */ -#define SGPIO_MUX_CFG15_CONCAT_ORDER_SHIFT (12) -#define SGPIO_MUX_CFG15_CONCAT_ORDER_MASK (0x3 << SGPIO_MUX_CFG15_CONCAT_ORDER_SHIFT) -#define SGPIO_MUX_CFG15_CONCAT_ORDER(x) ((x) << SGPIO_MUX_CFG15_CONCAT_ORDER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG0 values ------------------------------ */ +/* --- SGPIO_SLICE_MUX_CFG[0..15] values ---------------------------------- */ /* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG0_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE_SHIFT (0) +#define SGPIO_SLICE_MUX_CFGx_MATCH_MODE \ + (1 << SGPIO_SLICE_MUX_CFG0_MATCH_MODE_SHIFT) /* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG0_CLK_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT (1) +#define SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE \ + (1 << SGPIO_SLICE_MUX_CFGx_CLK_CAPTURE_MODE_SHIFT) /* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG0_CLKGEN_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT (2) +#define SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE \ + (1 << SGPIO_SLICE_MUX_CFGx_CLKGEN_MODE_SHIFT) /* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG0_INV_OUT_CLK_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT (3) +#define SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK \ + (1 << SGPIO_SLICE_MUX_CFGx_INV_OUT_CLK_SHIFT) /* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG0_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT (4) +#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFGx_DATA_CAPTURE_MODE_SHIFT) /* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG0_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT (6) +#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_MASK \ + (0x3 << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE(x) \ + ((x) << SGPIO_SLICE_MUX_CFGx_PARALLEL_MODE_SHIFT) /* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG0_INV_QUALIFIER_SHIFT) +#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT (8) +#define SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER \ + (1 << SGPIO_SLICE_MUX_CFGx_INV_QUALIFIER_SHIFT) -/* --- SGPIO_SLICE_MUX_CFG1 values ------------------------------ */ -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG1_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG1_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG1_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG1_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG1_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG1_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG1_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG1_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG2 values ------------------------------ */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG2_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG2_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG2_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG2_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG2_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG2_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG2_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG2_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG3 values ------------------------------ */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG3_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG3_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG3_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG3_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG3_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG3_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG3_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG3_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG4 values ------------------------------ */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG4_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG4_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG4_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG4_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG4_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG4_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG4_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG4_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG5 values ------------------------------ */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG5_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG5_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG5_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG5_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG5_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG5_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG5_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG5_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG6 values ------------------------------ */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG6_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG6_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG6_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG6_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG6_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG6_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG6_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG6_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG7 values ------------------------------ */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG7_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG7_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG7_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG7_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG7_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG7_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG7_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG7_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG8 values ------------------------------ */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG8_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG8_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG8_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG8_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG8_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG8_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG8_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG8_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG9 values ------------------------------ */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG9_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG9_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG9_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG9_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG9_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG9_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG9_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG9_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG10 values ----------------------------- */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG10_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG10_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG10_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG10_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG10_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG10_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG10_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG10_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG11 values ----------------------------- */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG11_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG11_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG11_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG11_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG11_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG11_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG11_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG11_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG12 values ----------------------------- */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG12_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG12_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG12_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG12_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG12_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG12_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG12_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG12_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG13 values ----------------------------- */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG13_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG13_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG13_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG13_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG13_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG13_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG13_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG13_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG14 values ----------------------------- */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG14_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG14_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG14_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG14_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG14_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG14_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG14_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG14_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_SLICE_MUX_CFG15 values ----------------------------- */ - -/* MATCH_MODE: Match mode */ -#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE_SHIFT (0) -#define SGPIO_SLICE_MUX_CFG15_MATCH_MODE (1 << SGPIO_SLICE_MUX_CFG15_MATCH_MODE_SHIFT) - -/* CLK_CAPTURE_MODE: Capture clock mode */ -#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_SHIFT (1) -#define SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE (1 << SGPIO_SLICE_MUX_CFG15_CLK_CAPTURE_MODE_SHIFT) - -/* CLKGEN_MODE: Clock generation mode */ -#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_SHIFT (2) -#define SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE (1 << SGPIO_SLICE_MUX_CFG15_CLKGEN_MODE_SHIFT) - -/* INV_OUT_CLK: Invert output clock */ -#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_SHIFT (3) -#define SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK (1 << SGPIO_SLICE_MUX_CFG15_INV_OUT_CLK_SHIFT) - -/* DATA_CAPTURE_MODE: Condition for input bit match interrupt */ -#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_SHIFT (4) -#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG15_DATA_CAPTURE_MODE_SHIFT) - -/* PARALLEL_MODE: Parallel mode */ -#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_SHIFT (6) -#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_MASK (0x3 << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_SHIFT) -#define SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE(x) ((x) << SGPIO_SLICE_MUX_CFG15_PARALLEL_MODE_SHIFT) - -/* INV_QUALIFIER: Inversion qualifier */ -#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_SHIFT (8) -#define SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER (1 << SGPIO_SLICE_MUX_CFG15_INV_QUALIFIER_SHIFT) - -/* --- SGPIO_POS0 values ---------------------------------------- */ +/* --- SGPIO_POS[0..15] values -------------------------------------------- */ /* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS0_POS_SHIFT (0) -#define SGPIO_POS0_POS_MASK (0xff << SGPIO_POS0_POS_SHIFT) -#define SGPIO_POS0_POS(x) ((x) << SGPIO_POS0_POS_SHIFT) +#define SGPIO_POSx_POS_SHIFT (0) +#define SGPIO_POSx_POS_MASK (0xff << SGPIO_POSx_POS_SHIFT) +#define SGPIO_POSx_POS(x) ((x) << SGPIO_POSx_POS_SHIFT) /* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS0_POS_RESET_SHIFT (8) -#define SGPIO_POS0_POS_RESET_MASK (0xff << SGPIO_POS0_POS_RESET_SHIFT) -#define SGPIO_POS0_POS_RESET(x) ((x) << SGPIO_POS0_POS_RESET_SHIFT) +#define SGPIO_POSx_POS_RESET_SHIFT (8) +#define SGPIO_POSx_POS_RESET_MASK (0xff << SGPIO_POSx_POS_RESET_SHIFT) +#define SGPIO_POSx_POS_RESET(x) ((x) << SGPIO_POSx_POS_RESET_SHIFT) -/* --- SGPIO_POS1 values ---------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS1_POS_SHIFT (0) -#define SGPIO_POS1_POS_MASK (0xff << SGPIO_POS1_POS_SHIFT) -#define SGPIO_POS1_POS(x) ((x) << SGPIO_POS1_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS1_POS_RESET_SHIFT (8) -#define SGPIO_POS1_POS_RESET_MASK (0xff << SGPIO_POS1_POS_RESET_SHIFT) -#define SGPIO_POS1_POS_RESET(x) ((x) << SGPIO_POS1_POS_RESET_SHIFT) - -/* --- SGPIO_POS2 values ---------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS2_POS_SHIFT (0) -#define SGPIO_POS2_POS_MASK (0xff << SGPIO_POS2_POS_SHIFT) -#define SGPIO_POS2_POS(x) ((x) << SGPIO_POS2_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS2_POS_RESET_SHIFT (8) -#define SGPIO_POS2_POS_RESET_MASK (0xff << SGPIO_POS2_POS_RESET_SHIFT) -#define SGPIO_POS2_POS_RESET(x) ((x) << SGPIO_POS2_POS_RESET_SHIFT) - -/* --- SGPIO_POS3 values ---------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS3_POS_SHIFT (0) -#define SGPIO_POS3_POS_MASK (0xff << SGPIO_POS3_POS_SHIFT) -#define SGPIO_POS3_POS(x) ((x) << SGPIO_POS3_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS3_POS_RESET_SHIFT (8) -#define SGPIO_POS3_POS_RESET_MASK (0xff << SGPIO_POS3_POS_RESET_SHIFT) -#define SGPIO_POS3_POS_RESET(x) ((x) << SGPIO_POS3_POS_RESET_SHIFT) - -/* --- SGPIO_POS4 values ---------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS4_POS_SHIFT (0) -#define SGPIO_POS4_POS_MASK (0xff << SGPIO_POS4_POS_SHIFT) -#define SGPIO_POS4_POS(x) ((x) << SGPIO_POS4_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS4_POS_RESET_SHIFT (8) -#define SGPIO_POS4_POS_RESET_MASK (0xff << SGPIO_POS4_POS_RESET_SHIFT) -#define SGPIO_POS4_POS_RESET(x) ((x) << SGPIO_POS4_POS_RESET_SHIFT) - -/* --- SGPIO_POS5 values ---------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS5_POS_SHIFT (0) -#define SGPIO_POS5_POS_MASK (0xff << SGPIO_POS5_POS_SHIFT) -#define SGPIO_POS5_POS(x) ((x) << SGPIO_POS5_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS5_POS_RESET_SHIFT (8) -#define SGPIO_POS5_POS_RESET_MASK (0xff << SGPIO_POS5_POS_RESET_SHIFT) -#define SGPIO_POS5_POS_RESET(x) ((x) << SGPIO_POS5_POS_RESET_SHIFT) - -/* --- SGPIO_POS6 values ---------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS6_POS_SHIFT (0) -#define SGPIO_POS6_POS_MASK (0xff << SGPIO_POS6_POS_SHIFT) -#define SGPIO_POS6_POS(x) ((x) << SGPIO_POS6_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS6_POS_RESET_SHIFT (8) -#define SGPIO_POS6_POS_RESET_MASK (0xff << SGPIO_POS6_POS_RESET_SHIFT) -#define SGPIO_POS6_POS_RESET(x) ((x) << SGPIO_POS6_POS_RESET_SHIFT) - -/* --- SGPIO_POS7 values ---------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS7_POS_SHIFT (0) -#define SGPIO_POS7_POS_MASK (0xff << SGPIO_POS7_POS_SHIFT) -#define SGPIO_POS7_POS(x) ((x) << SGPIO_POS7_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS7_POS_RESET_SHIFT (8) -#define SGPIO_POS7_POS_RESET_MASK (0xff << SGPIO_POS7_POS_RESET_SHIFT) -#define SGPIO_POS7_POS_RESET(x) ((x) << SGPIO_POS7_POS_RESET_SHIFT) - -/* --- SGPIO_POS8 values ---------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS8_POS_SHIFT (0) -#define SGPIO_POS8_POS_MASK (0xff << SGPIO_POS8_POS_SHIFT) -#define SGPIO_POS8_POS(x) ((x) << SGPIO_POS8_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS8_POS_RESET_SHIFT (8) -#define SGPIO_POS8_POS_RESET_MASK (0xff << SGPIO_POS8_POS_RESET_SHIFT) -#define SGPIO_POS8_POS_RESET(x) ((x) << SGPIO_POS8_POS_RESET_SHIFT) - -/* --- SGPIO_POS9 values ---------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS9_POS_SHIFT (0) -#define SGPIO_POS9_POS_MASK (0xff << SGPIO_POS9_POS_SHIFT) -#define SGPIO_POS9_POS(x) ((x) << SGPIO_POS9_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS9_POS_RESET_SHIFT (8) -#define SGPIO_POS9_POS_RESET_MASK (0xff << SGPIO_POS9_POS_RESET_SHIFT) -#define SGPIO_POS9_POS_RESET(x) ((x) << SGPIO_POS9_POS_RESET_SHIFT) - -/* --- SGPIO_POS10 values --------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS10_POS_SHIFT (0) -#define SGPIO_POS10_POS_MASK (0xff << SGPIO_POS10_POS_SHIFT) -#define SGPIO_POS10_POS(x) ((x) << SGPIO_POS10_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS10_POS_RESET_SHIFT (8) -#define SGPIO_POS10_POS_RESET_MASK (0xff << SGPIO_POS10_POS_RESET_SHIFT) -#define SGPIO_POS10_POS_RESET(x) ((x) << SGPIO_POS10_POS_RESET_SHIFT) - -/* --- SGPIO_POS11 values --------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS11_POS_SHIFT (0) -#define SGPIO_POS11_POS_MASK (0xff << SGPIO_POS11_POS_SHIFT) -#define SGPIO_POS11_POS(x) ((x) << SGPIO_POS11_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS11_POS_RESET_SHIFT (8) -#define SGPIO_POS11_POS_RESET_MASK (0xff << SGPIO_POS11_POS_RESET_SHIFT) -#define SGPIO_POS11_POS_RESET(x) ((x) << SGPIO_POS11_POS_RESET_SHIFT) - -/* --- SGPIO_POS12 values --------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS12_POS_SHIFT (0) -#define SGPIO_POS12_POS_MASK (0xff << SGPIO_POS12_POS_SHIFT) -#define SGPIO_POS12_POS(x) ((x) << SGPIO_POS12_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS12_POS_RESET_SHIFT (8) -#define SGPIO_POS12_POS_RESET_MASK (0xff << SGPIO_POS12_POS_RESET_SHIFT) -#define SGPIO_POS12_POS_RESET(x) ((x) << SGPIO_POS12_POS_RESET_SHIFT) - -/* --- SGPIO_POS13 values --------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS13_POS_SHIFT (0) -#define SGPIO_POS13_POS_MASK (0xff << SGPIO_POS13_POS_SHIFT) -#define SGPIO_POS13_POS(x) ((x) << SGPIO_POS13_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS13_POS_RESET_SHIFT (8) -#define SGPIO_POS13_POS_RESET_MASK (0xff << SGPIO_POS13_POS_RESET_SHIFT) -#define SGPIO_POS13_POS_RESET(x) ((x) << SGPIO_POS13_POS_RESET_SHIFT) - -/* --- SGPIO_POS14 values --------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS14_POS_SHIFT (0) -#define SGPIO_POS14_POS_MASK (0xff << SGPIO_POS14_POS_SHIFT) -#define SGPIO_POS14_POS(x) ((x) << SGPIO_POS14_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS14_POS_RESET_SHIFT (8) -#define SGPIO_POS14_POS_RESET_MASK (0xff << SGPIO_POS14_POS_RESET_SHIFT) -#define SGPIO_POS14_POS_RESET(x) ((x) << SGPIO_POS14_POS_RESET_SHIFT) - -/* --- SGPIO_POS15 values --------------------------------------- */ - -/* POS: Each time COUNT reaches 0x0 POS counts down */ -#define SGPIO_POS15_POS_SHIFT (0) -#define SGPIO_POS15_POS_MASK (0xff << SGPIO_POS15_POS_SHIFT) -#define SGPIO_POS15_POS(x) ((x) << SGPIO_POS15_POS_SHIFT) - -/* POS_RESET: Reload value for POS after POS reaches 0x0 */ -#define SGPIO_POS15_POS_RESET_SHIFT (8) -#define SGPIO_POS15_POS_RESET_MASK (0xff << SGPIO_POS15_POS_RESET_SHIFT) -#define SGPIO_POS15_POS_RESET(x) ((x) << SGPIO_POS15_POS_RESET_SHIFT) /* SGPIO structure for faster/better code generation (especially when optimized with -O2/-O3) */ /* This structure is compliant with LPC43xx User Manual UM10503 Rev.1.4 - 3 September 2012 */