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stm32/common: Fixed some of the Flash headers defining constants in UB ways

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dragonmux
2024-05-01 23:54:46 +01:00
committed by Piotr Esden-Tempski
parent 94411df91f
commit c13dd75d55
2 changed files with 69 additions and 70 deletions
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102
include/libopencm3/stm32/common/flash_common_f24.h
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@@ -46,88 +46,88 @@
* @ingroup flash_defines * @ingroup flash_defines
@{*/ @{*/
/** Flash Access Control register */ /** Flash Access Control register */
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00) #define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00U)
/** Flash Key register */ /** Flash Key register */
#define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04) #define FLASH_KEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04U)
/** Flash Option bytes key register */ /** Flash Option bytes key register */
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08) #define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08U)
/** Flash Status register*/ /** Flash Status register*/
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C) #define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0CU)
/** Flash Control register */ /** Flash Control register */
#define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10) #define FLASH_CR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10U)
/** Flash Option Control register */ /** Flash Option Control register */
#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) #define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14U)
/** Flash Option Control register 1 (bank 2) */ /** Flash Option Control register 1 (bank 2) */
#define FLASH_OPTCR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) #define FLASH_OPTCR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18U)
/**@}*/ /**@}*/
/** @defgroup flash_latency FLASH Wait States /** @defgroup flash_latency FLASH Wait States
@ingroup flash_defines @ingroup flash_defines
@{*/ @{*/
#define FLASH_ACR_LATENCY(w) ((w) & FLASH_ACR_LATENCY_MASK) #define FLASH_ACR_LATENCY(w) ((w) & FLASH_ACR_LATENCY_MASK)
#define FLASH_ACR_LATENCY_0WS 0x00 #define FLASH_ACR_LATENCY_0WS 0x00U
#define FLASH_ACR_LATENCY_1WS 0x01 #define FLASH_ACR_LATENCY_1WS 0x01U
#define FLASH_ACR_LATENCY_2WS 0x02 #define FLASH_ACR_LATENCY_2WS 0x02U
#define FLASH_ACR_LATENCY_3WS 0x03 #define FLASH_ACR_LATENCY_3WS 0x03U
#define FLASH_ACR_LATENCY_4WS 0x04 #define FLASH_ACR_LATENCY_4WS 0x04U
#define FLASH_ACR_LATENCY_5WS 0x05 #define FLASH_ACR_LATENCY_5WS 0x05U
#define FLASH_ACR_LATENCY_6WS 0x06 #define FLASH_ACR_LATENCY_6WS 0x06U
#define FLASH_ACR_LATENCY_7WS 0x07 #define FLASH_ACR_LATENCY_7WS 0x07U
/**@}*/ /**@}*/
#define FLASH_ACR_LATENCY_SHIFT 0 #define FLASH_ACR_LATENCY_SHIFT 0U
#define FLASH_ACR_LATENCY_MASK 0x0f #define FLASH_ACR_LATENCY_MASK 0x0fU
/** @defgroup flash_acr_values FLASH_ACR values /** @defgroup flash_acr_values FLASH_ACR values
* @ingroup flash_registers * @ingroup flash_registers
* @brief Access Control register values * @brief Access Control register values
* @{*/ * @{*/
#define FLASH_ACR_PRFTEN (1 << 8) #define FLASH_ACR_PRFTEN (1U << 8U)
/**@}*/ /**@}*/
/* --- FLASH_SR values ----------------------------------------------------- */ /* --- FLASH_SR values ----------------------------------------------------- */
#define FLASH_SR_BSY (1 << 16) #define FLASH_SR_BSY (1U << 16U)
#define FLASH_SR_PGPERR (1 << 6) #define FLASH_SR_PGPERR (1U << 6U)
#define FLASH_SR_PGAERR (1 << 5) #define FLASH_SR_PGAERR (1U << 5U)
#define FLASH_SR_WRPERR (1 << 4) #define FLASH_SR_WRPERR (1U << 4U)
#define FLASH_SR_OPERR (1 << 1) #define FLASH_SR_OPERR (1U << 1U)
#define FLASH_SR_EOP (1 << 0) #define FLASH_SR_EOP (1U << 0U)
/* --- FLASH_CR values ----------------------------------------------------- */ /* --- FLASH_CR values ----------------------------------------------------- */
#define FLASH_CR_LOCK (1 << 31) #define FLASH_CR_LOCK (1U << 31U)
#define FLASH_CR_ERRIE (1 << 25) #define FLASH_CR_ERRIE (1U << 25U)
#define FLASH_CR_EOPIE (1 << 24) #define FLASH_CR_EOPIE (1U << 24U)
#define FLASH_CR_STRT (1 << 16) #define FLASH_CR_STRT (1U << 16U)
#define FLASH_CR_MER (1 << 2) #define FLASH_CR_MER (1U << 2U)
#define FLASH_CR_SER (1 << 1) #define FLASH_CR_SER (1U << 1U)
#define FLASH_CR_PG (1 << 0) #define FLASH_CR_PG (1U << 0U)
#define FLASH_CR_SNB_SHIFT 3 #define FLASH_CR_SNB_SHIFT 3U
#define FLASH_CR_SNB_MASK 0x1f #define FLASH_CR_SNB_MASK 0x1fU
#define FLASH_CR_PROGRAM_MASK 0x3 #define FLASH_CR_PROGRAM_MASK 0x3U
#define FLASH_CR_PROGRAM_SHIFT 8 #define FLASH_CR_PROGRAM_SHIFT 8U
/** @defgroup flash_cr_program_width Flash programming width /** @defgroup flash_cr_program_width Flash programming width
@ingroup flash_group @ingroup flash_group
@{*/ @{*/
#define FLASH_CR_PROGRAM_X8 0 #define FLASH_CR_PROGRAM_X8 0U
#define FLASH_CR_PROGRAM_X16 1 #define FLASH_CR_PROGRAM_X16 1U
#define FLASH_CR_PROGRAM_X32 2 #define FLASH_CR_PROGRAM_X32 2U
#define FLASH_CR_PROGRAM_X64 3 #define FLASH_CR_PROGRAM_X64 3U
/**@}*/ /**@}*/
/* --- FLASH_OPTCR values -------------------------------------------------- */ /* --- FLASH_OPTCR values -------------------------------------------------- */
/* FLASH_OPTCR[27:16]: nWRP */ /* FLASH_OPTCR[27:16]: nWRP */
/* FLASH_OBR[15:8]: RDP */ /* FLASH_OBR[15:8]: RDP */
#define FLASH_OPTCR_NRST_STDBY (1 << 7) #define FLASH_OPTCR_NRST_STDBY (1U << 7U)
#define FLASH_OPTCR_NRST_STOP (1 << 6) #define FLASH_OPTCR_NRST_STOP (1U << 6U)
#define FLASH_OPTCR_OPTSTRT (1 << 1) #define FLASH_OPTCR_OPTSTRT (1U << 1U)
#define FLASH_OPTCR_OPTLOCK (1 << 0) #define FLASH_OPTCR_OPTLOCK (1U << 0U)
#define FLASH_OPTCR_BOR_LEVEL_3 (0x00 << 2) #define FLASH_OPTCR_BOR_LEVEL_3 (0x00U << 2U)
#define FLASH_OPTCR_BOR_LEVEL_2 (0x01 << 2) #define FLASH_OPTCR_BOR_LEVEL_2 (0x01U << 2U)
#define FLASH_OPTCR_BOR_LEVEL_1 (0x02 << 2) #define FLASH_OPTCR_BOR_LEVEL_1 (0x02U << 2U)
#define FLASH_OPTCR_BOR_OFF (0x03 << 2) #define FLASH_OPTCR_BOR_OFF (0x03U << 2U)
/* --- FLASH_OPTCR1 values ------------------------------------------------- */ /* --- FLASH_OPTCR1 values ------------------------------------------------- */
/* Only on some devices */ /* Only on some devices */
@@ -135,11 +135,11 @@
/* --- FLASH Keys -----------------------------------------------------------*/ /* --- FLASH Keys -----------------------------------------------------------*/
#define FLASH_KEYR_KEY1 ((uint32_t)0x45670123) #define FLASH_KEYR_KEY1 (0x45670123U)
#define FLASH_KEYR_KEY2 ((uint32_t)0xcdef89ab) #define FLASH_KEYR_KEY2 (0xcdef89abU)
#define FLASH_OPTKEYR_KEY1 ((uint32_t)0x08192a3b) #define FLASH_OPTKEYR_KEY1 (0x08192a3bU)
#define FLASH_OPTKEYR_KEY2 ((uint32_t)0x4c5d6e7f) #define FLASH_OPTKEYR_KEY2 (0x4c5d6e7fU)
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */

37
include/libopencm3/stm32/f7/flash.h
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@@ -54,35 +54,35 @@
/** @addtogroup flash_acr_values FLASH_ACR values /** @addtogroup flash_acr_values FLASH_ACR values
* @ingroup flash_registers * @ingroup flash_registers
@{*/ @{*/
#define FLASH_ACR_ARTRST (1 << 11) #define FLASH_ACR_ARTRST (1U << 11U)
#define FLASH_ACR_ARTEN (1 << 9) #define FLASH_ACR_ARTEN (1U << 9U)
#define FLASH_ACR_PRFTEN (1 << 8) #define FLASH_ACR_PRFTEN (1U << 8U)
/**@}*/ /**@}*/
#define FLASH_SR_ERSERR (1 << 7) #define FLASH_SR_ERSERR (1U << 7U)
/* --- FLASH_OPTCR values -------------------------------------------------- */ /* --- FLASH_OPTCR values -------------------------------------------------- */
#define FLASH_OPTCR_IWDG_STOP (1 << 31) #define FLASH_OPTCR_IWDG_STOP (1U << 31U)
#define FLASH_OPTCR_IWDG_STDBY (1 << 30) #define FLASH_OPTCR_IWDG_STDBY (1U << 30U)
#define FLASH_OPTCR_NWRP_SHIFT 16 #define FLASH_OPTCR_NWRP_SHIFT 16U
#define FLASH_OPTCR_NWRP_MASK 0xff #define FLASH_OPTCR_NWRP_MASK 0xffU
#define FLASH_OPTCR_RDP_SHIFT 8 #define FLASH_OPTCR_RDP_SHIFT 8U
#define FLASH_OPTCR_RDP_MASK 0xff #define FLASH_OPTCR_RDP_MASK 0xffU
#define FLASH_OPTCR_IWDG_SW (1 << 5) #define FLASH_OPTCR_IWDG_SW (1U << 5U)
#define FLASH_OPTCR_WWDG_SW (1 << 4) #define FLASH_OPTCR_WWDG_SW (1U << 4U)
#define FLASH_OPTCR_OPTSTRT (1 << 1) #define FLASH_OPTCR_OPTSTRT (1U << 1U)
#define FLASH_OPTCR_OPTLOCK (1 << 0) #define FLASH_OPTCR_OPTLOCK (1U << 0U)
/* --- FLASH_OPTCR1 values ------------------------------------------------- */ /* --- FLASH_OPTCR1 values ------------------------------------------------- */
#define FLASH_OPTCR1_BOOT_ADD1_MASK 0xffff #define FLASH_OPTCR1_BOOT_ADD1_MASK 0xffffU
#define FLASH_OPTCR1_BOOT_ADD1_SHIFT 16 #define FLASH_OPTCR1_BOOT_ADD1_SHIFT 16U
#define FLASH_OPTCR1_BOOT_ADD0_MASK 0xffff #define FLASH_OPTCR1_BOOT_ADD0_MASK 0xffffU
#define FLASH_OPTCR1_BOOT_ADD0_SHIFT 0 #define FLASH_OPTCR1_BOOT_ADD0_SHIFT 0U
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */
@@ -96,4 +96,3 @@ END_DECLS
/**@}*/ /**@}*/
#endif #endif