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[flash] l1: use "proper" bit definition naming.

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Part 1 of 4: updated l1 to use flash_<reg>_bit instead of just flash_bit
This commit is contained in:
Karl Palsson
2013-01-23 12:54:17 +00:00
parent 20bfcaeb1c
commit c0ea749452
3 changed files with 56 additions and 56 deletions
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8
lib/stm32/l1/flash.c
View File

@@ -23,22 +23,22 @@
void flash_64bit_enable(void)
{
FLASH_ACR |= FLASH_ACC64;
FLASH_ACR |= FLASH_ACR_ACC64;
}
void flash_64bit_disable(void)
{
FLASH_ACR &= ~FLASH_ACC64;
FLASH_ACR &= ~FLASH_ACR_ACC64;
}
void flash_prefetch_enable(void)
{
FLASH_ACR |= FLASH_PRFTEN;
FLASH_ACR |= FLASH_ACR_PRFTEN;
}
void flash_prefetch_disable(void)
{
FLASH_ACR &= ~FLASH_PRFTEN;
FLASH_ACR &= ~FLASH_ACR_PRFTEN;
}
void flash_set_ws(u32 ws)

6
lib/stm32/l1/rcc.c
View File

@@ -39,7 +39,7 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
.flash_config = FLASH_LATENCY_1WS,
.flash_config = FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 24000000,
.apb2_frequency = 24000000,
},
@@ -51,7 +51,7 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
.flash_config = FLASH_LATENCY_1WS,
.flash_config = FLASH_ACR_LATENCY_1WS,
.apb1_frequency = 32000000,
.apb2_frequency = 32000000,
},
@@ -60,7 +60,7 @@ const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END] =
.ppre1 = RCC_CFGR_PPRE1_HCLK_NODIV,
.ppre2 = RCC_CFGR_PPRE2_HCLK_NODIV,
.voltage_scale = RANGE1,
.flash_config = FLASH_LATENCY_0WS,
.flash_config = FLASH_ACR_LATENCY_0WS,
.apb1_frequency = 16000000,
.apb2_frequency = 16000000,
},