stm32: rework spi, based on PR #740 and #742.

split spi stuff in three part:
 - v1 : basic spi peripheral
 - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
 - v2 : spi with variable datasize, fifo and other fancy stuff.

v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4

This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.

lib/stm32/l1/Makefile

@@ -42,7 +42,8 @@ OBJS		+= flash_common_l01.o
 OBJS		+= gpio_common_all.o gpio_common_f0234.o
 OBJS		+= i2c_common_v1.o iwdg_common_all.o
 OBJS		+= pwr_common_v1.o pwr_common_v2.o rtc_common_l1f024.o
-OBJS		+= spi_common_all.o spi_common_l1f124.o timer_common_all.o
+OBJS		+= spi_common_all.o spi_common_v1.o spi_common_v1_frf.o
+OBJS		+= timer_common_all.o
 OBJS		+= usart_common_all.o usart_common_f124.o
 OBJS		+= exti_common_all.o
 OBJS		+= rcc_common_all.o