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stm32: rework spi, based on PR #740 and #742.

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split spi stuff in three part:
 - v1 : basic spi peripheral
 - v1_frf : v1 spi with frf mode additional bit in spi_cr2 / spi_sr
 - v2 : spi with variable datasize, fifo and other fancy stuff.

v1 maps to f1 chips
v1_frf to f2, f4 and l0,l1
v2 to f0, f3 and l4

This breaks spi_master_init API for v2 devices : function prototype from
common spi header used to be abused, with DFF bit reused for CRCL bit.
New v2 spi_master_init does not handle anymore CRCL bits, as it does not
usually mess with other crc configuration.
This commit is contained in:
Guillaume Revaillot
2018-04-04 16:27:59 +02:00
committed by Karl Palsson
parent 0deb58c73c
commit bf125e91f9
24 changed files with 205 additions and 83 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
lib/stm32/common/spi_common_l1f124.c → lib/stm32/common/spi_common_v1.c
View File

@@ -1,3 +1,4 @@
/** @addtogroup spi_file
@author @htmlonly © @endhtmlonly 2009
@@ -53,6 +54,7 @@ LSB first.
#include <libopencm3/stm32/spi.h>
#include <libopencm3/stm32/rcc.h>
/**@{*/
/*---------------------------------------------------------------------------*/
@@ -96,7 +98,7 @@ int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
SPI_CR2(spi) |= SPI_CR2_SSOE; /* common case */
SPI_CR1(spi) = reg32;
return 0; /* TODO */
return 0;
}
/*---------------------------------------------------------------------------*/

67
lib/stm32/common/spi_common_v1_frf.c Normal file
View File

@@ -0,0 +1,67 @@
/** @addtogroup spi_file
@author @htmlonly &copy; @endhtmlonly 2009
Uwe Hermann <uwe@hermann-uwe.de>
@author @htmlonly &copy; @endhtmlonly 2012
Ken Sarkies <ksarkies@internode.on.net>
@author @htmlonly &copy; @endhtmlonly 2018
Guillaume Revaillot <revaillot@archos.com>
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/spi.h>
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Frame Format to TI
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_frf_ti(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_FRF;
}
/*---------------------------------------------------------------------------*/
/** @brief SPI Set Frame Format to Motorola
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_set_frf_motorola(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_FRF;
}
#define SPI_CR2_FRF (1 << 4)
#define SPI_CR2_FRF_MOTOROLA_MODE (0 << 4)
#define SPI_CR2_FRF_TI_MODE (1 << 4)
/* --- SPI_SR values ------------------------------------------------------- */
/* FRE / TIFRFE: TI frame format error */
#define SPI_SR_TIFRFE (1 << 8) //F2
#define SPI_SR_FRE (1 << 8) //others
/**@}*/

40
lib/stm32/common/spi_common_f03.c → lib/stm32/common/spi_common_v2.c
View File

@@ -59,36 +59,32 @@ LSB first.
/** @brief Configure the SPI as Master.
The SPI peripheral is configured as a master with communication parameters
baudrate, crc length 8/16 bits, frame format lsb/msb first, clock polarity
and phase. The SPI enable, CRC enable and CRC next controls are not affected.
baudrate, frame format lsb/msb first, clock polarity and phase. The SPI
enable, CRC enable, CRC next CRC length controls are not affected.
These must be controlled separately.
@todo NSS pin handling.
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@param[in] br Unsigned int32. Baudrate @ref spi_baudrate.
@param[in] cpol Unsigned int32. Clock polarity @ref spi_cpol.
@param[in] cpha Unsigned int32. Clock Phase @ref spi_cpha.
@param[in] crcl Unsigned int32. CRC length 8/16 bits @ref spi_crcl.
@param[in] lsbfirst Unsigned int32. Frame format lsb/msb first @ref
spi_lsbfirst.
@returns int. Error code.
*/
int spi_init_master(uint32_t spi, uint32_t br, uint32_t cpol, uint32_t cpha,
uint32_t crcl, uint32_t lsbfirst)
uint32_t lsbfirst)
{
uint32_t reg32 = SPI_CR1(spi);
/* Reset all bits omitting SPE, CRCEN and CRCNEXT bits. */
reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT;
/* Reset all bits omitting SPE, CRCEN, CRCNEXT and CRCL bits. */
reg32 &= SPI_CR1_SPE | SPI_CR1_CRCEN | SPI_CR1_CRCNEXT | SPI_CR1_CRCL;
reg32 |= SPI_CR1_MSTR; /* Configure SPI as master. */
reg32 |= br; /* Set baud rate bits. */
reg32 |= cpol; /* Set CPOL value. */
reg32 |= cpha; /* Set CPHA value. */
reg32 |= crcl; /* Set crc length (8 or 16 bits). */
reg32 |= lsbfirst; /* Set frame format (LSB- or MSB-first). */
/* TODO: NSS pin handling. */
@@ -103,7 +99,6 @@ void spi_send8(uint32_t spi, uint8_t data)
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_TXE));
/* Write data (8 or 16 bits, depending on DFF) into DR. */
SPI_DR8(spi) = data;
}
@@ -112,7 +107,6 @@ uint8_t spi_read8(uint32_t spi)
/* Wait for transfer finished. */
while (!(SPI_SR(spi) & SPI_SR_RXNE));
/* Read the data (8 or 16 bits, depending on DFF bit) from DR. */
return SPI_DR8(spi);
}
@@ -138,26 +132,38 @@ void spi_set_crcl_16bit(uint32_t spi)
SPI_CR1(spi) |= SPI_CR1_CRCL;
}
/** @brief SPI Set data size
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
@param[in] data_s Unsigned int16. data size @ref spi_ds.
*/
void spi_set_data_size(uint32_t spi, uint16_t data_s)
{
SPI_CR2(spi) = (SPI_CR2(spi) & ~SPI_CR2_DS_MASK) |
(data_s & SPI_CR2_DS_MASK);
}
/*---------------------------------------------------------------------------*/
/** @brief SPI Set reception threshold to 8 bits
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_fifo_reception_threshold_8bit(uint32_t spi)
{
SPI_CR2(spi) |= SPI_CR2_FRXTH;
}
/*---------------------------------------------------------------------------*/
/** @brief SPI Set reception threshold to 16 bits
@param[in] spi Unsigned int32. SPI peripheral identifier @ref spi_reg_base.
*/
void spi_fifo_reception_threshold_16bit(uint32_t spi)
{
SPI_CR2(spi) &= ~SPI_CR2_FRXTH;
}
void spi_i2s_mode_spi_mode(uint32_t spi)
{
SPI_I2SCFGR(spi) &= ~SPI_I2SCFGR_I2SMOD;
}
/**@}*/