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[Style] Stylefix sweep over the whole codebase.

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This commit is contained in:
Piotr Esden-Tempski
2015-12-14 22:57:15 +01:00
parent 1f6fd11dd9
commit b1049f9a6f
39 changed files with 445 additions and 359 deletions
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lib/stm32/common/spi_common_all.c
+2 -2
View File
@@ -730,10 +730,10 @@ Mode | CPOL | CPHA
void spi_set_standard_mode(uint32_t spi, uint8_t mode)
{
if(mode > 3) {
if (mode > 3) {
return;
}
uint32_t reg32 = SPI_CR1(spi) & ~(SPI_CR1_CPOL | SPI_CR1_CPHA);
SPI_CR1(spi) = reg32 | mode;
}
lib/stm32/common/st_usbfs_core.h
+4 -2
View File
@@ -44,8 +44,10 @@ void st_usbfs_endpoints_reset(usbd_device *usbd_dev);
void st_usbfs_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
uint8_t st_usbfs_ep_stall_get(usbd_device *usbd_dev, uint8_t addr);
void st_usbfs_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);
uint16_t st_usbfs_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len);
uint16_t st_usbfs_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len);
uint16_t st_usbfs_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len);
uint16_t st_usbfs_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
void *buf, uint16_t len);
void st_usbfs_poll(usbd_device *usbd_dev);
/* These must be implemented by the device specific driver */
lib/stm32/f0/flash.c
+2 -2
View File
@@ -76,10 +76,10 @@ error, bit 5: end of operation.
uint32_t flash_get_status_flags(void)
{
return (FLASH_SR & (FLASH_SR_PGERR |
return FLASH_SR & (FLASH_SR_PGERR |
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY));
FLASH_SR_BSY);
}
/*---------------------------------------------------------------------------*/
lib/stm32/f0/rcc.c
+3 -3
View File
@@ -523,7 +523,7 @@ enum rcc_osc rcc_system_clock_source(void)
*
* @returns ::osc_t USB clock source:
*/
enum rcc_osc rcc_usb_clock_source(void)
{
return (RCC_CFGR3 & RCC_CFGR3_USBSW) ? PLL : HSI48;
@@ -669,10 +669,10 @@ void rcc_clock_setup_in_hsi48_out_48mhz(void)
{
rcc_osc_on(HSI48);
rcc_wait_for_osc_ready(HSI48);
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
rcc_set_sysclk_source(HSI48);
lib/stm32/f1/flash.c
+26 -13
View File
@@ -128,8 +128,9 @@ void flash_lock_upper(void)
void flash_clear_pgerr_flag_upper(void)
{
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
FLASH_SR2 |= FLASH_SR_PGERR;
}
}
/*---------------------------------------------------------------------------*/
@@ -139,8 +140,9 @@ void flash_clear_pgerr_flag_upper(void)
void flash_clear_eop_flag_upper(void)
{
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
FLASH_SR2 |= FLASH_SR_EOP;
}
}
/*---------------------------------------------------------------------------*/
@@ -150,8 +152,9 @@ void flash_clear_eop_flag_upper(void)
void flash_clear_wrprterr_flag_upper(void)
{
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
FLASH_SR2 |= FLASH_SR_WRPRTERR;
}
}
/*---------------------------------------------------------------------------*/
@@ -161,8 +164,9 @@ void flash_clear_wrprterr_flag_upper(void)
void flash_clear_bsy_flag_upper(void)
{
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
FLASH_SR2 &= ~FLASH_SR_BSY;
}
}
/*---------------------------------------------------------------------------*/
@@ -204,12 +208,14 @@ uint32_t flash_get_status_flags(void)
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY));
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
flags |= (FLASH_SR2 & (FLASH_SR_PGERR |
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY));
return flags;
}
return flags;
}
/*---------------------------------------------------------------------------*/
@@ -229,17 +235,21 @@ void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000))
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000)) {
FLASH_CR2 |= FLASH_CR_PG;
else FLASH_CR |= FLASH_CR_PG;
} else {
FLASH_CR |= FLASH_CR_PG;
}
MMIO16(address) = data;
flash_wait_for_last_operation();
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000))
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000)) {
FLASH_CR2 &= ~FLASH_CR_PG;
else FLASH_CR &= ~FLASH_CR_PG;
} else {
FLASH_CR &= ~FLASH_CR_PG;
}
}
/*---------------------------------------------------------------------------*/
@@ -259,7 +269,8 @@ void flash_erase_page(uint32_t page_address)
{
flash_wait_for_last_operation();
if ((MEMORY_SIZE_REG > 512) && (page_address >= FLASH_BASE+0x00080000)) {
if ((MEMORY_SIZE_REG > 512)
&& (page_address >= FLASH_BASE+0x00080000)) {
FLASH_CR2 |= FLASH_CR_PER;
FLASH_AR2 = page_address;
FLASH_CR2 |= FLASH_CR_STRT;
@@ -271,10 +282,12 @@ void flash_erase_page(uint32_t page_address)
flash_wait_for_last_operation();
if ((MEMORY_SIZE_REG > 512) && (page_address >= FLASH_BASE+0x00080000))
if ((MEMORY_SIZE_REG > 512)
&& (page_address >= FLASH_BASE+0x00080000)) {
FLASH_CR2 &= ~FLASH_CR_PER;
else
} else {
FLASH_CR &= ~FLASH_CR_PER;
}
}
/*---------------------------------------------------------------------------*/
lib/stm32/f1/rcc.c
+7 -5
View File
@@ -509,7 +509,7 @@ void rcc_set_pllxtpre(uint32_t pllxtpre)
uint32_t rcc_rtc_clock_enabled_flag(void)
{
return RCC_BDCR & RCC_BDCR_RTCEN;
return RCC_BDCR & RCC_BDCR_RTCEN;
}
/*---------------------------------------------------------------------------*/
@@ -638,10 +638,11 @@ The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
void rcc_set_usbpre(uint32_t usbpre)
{
if (usbpre)
if (usbpre) {
RCC_CFGR |= RCC_CFGR_USBPRE;
else
} else {
RCC_CFGR &= ~RCC_CFGR_USBPRE;
}
}
void rcc_set_prediv1(uint32_t prediv)
@@ -658,10 +659,11 @@ void rcc_set_prediv2(uint32_t prediv)
void rcc_set_prediv1_source(uint32_t rccsrc)
{
if (rccsrc)
if (rccsrc) {
RCC_CFGR2 |= RCC_CFGR2_PREDIV1SRC;
else
} else {
RCC_CFGR2 &= ~RCC_CFGR2_PREDIV1SRC;
}
}
/*---------------------------------------------------------------------------*/
lib/stm32/f3/adc.c
+4 -4
View File
@@ -375,7 +375,7 @@ void adc_disable_eoc_interrupt_injected(uint32_t adc)
void adc_enable_eos_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_JEOSIE;
ADC_IER(adc) |= ADC_IER_JEOSIE;
}
/*---------------------------------------------------------------------------*/
@@ -387,7 +387,7 @@ void adc_enable_eos_interrupt_injected(uint32_t adc)
void adc_disable_eos_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_JEOSIE;
ADC_IER(adc) &= ~ADC_IER_JEOSIE;
}
@@ -452,7 +452,7 @@ void adc_disable_eoc_interrupt(uint32_t adc)
void adc_enable_eos_interrupt(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_EOSIE;
ADC_IER(adc) |= ADC_IER_EOSIE;
}
/*---------------------------------------------------------------------------*/
@@ -464,7 +464,7 @@ void adc_enable_eos_interrupt(uint32_t adc)
void adc_disable_eos_interrupt(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_EOSIE;
ADC_IER(adc) &= ~ADC_IER_EOSIE;
}
lib/stm32/f3/rcc.c
+4 -2
View File
@@ -475,8 +475,10 @@ void rcc_usb_prescale_1(void)
void rcc_adc_prescale(uint32_t prescale1, uint32_t prescale2)
{
uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC12PRES_SHIFT) |
(RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC34PRES_SHIFT);
uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK
<< RCC_CFGR2_ADC12PRES_SHIFT)
| (RCC_CFGR2_ADCxPRES_MASK
<< RCC_CFGR2_ADC34PRES_SHIFT);
uint32_t set = (prescale1 << RCC_CFGR2_ADC12PRES_SHIFT) |
(prescale2 << RCC_CFGR2_ADC34PRES_SHIFT);
RCC_CFGR2 &= ~(clear_mask);
lib/stm32/f4/fmc.c
+23 -23
View File
@@ -51,7 +51,7 @@ sdram_timing(struct sdram_timing *t) {
*/
void
sdram_command(enum fmc_sdram_bank bank,
enum fmc_sdram_command cmd, int autorefresh, int modereg) {
enum fmc_sdram_command cmd, int autorefresh, int modereg) {
uint32_t tmp_reg = 0;
switch (bank) {
@@ -68,31 +68,31 @@ sdram_command(enum fmc_sdram_bank bank,
tmp_reg |= autorefresh << FMC_SDCMR_NRFS_SHIFT;
tmp_reg |= modereg << FMC_SDCMR_MRD_SHIFT;
switch (cmd) {
case SDRAM_CLK_CONF:
tmp_reg |= FMC_SDCMR_MODE_CLOCK_CONFIG_ENA;
break;
case SDRAM_AUTO_REFRESH:
tmp_reg |= FMC_SDCMR_MODE_AUTO_REFRESH;
break;
case SDRAM_LOAD_MODE:
tmp_reg |= FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
break;
case SDRAM_PALL:
tmp_reg |= FMC_SDCMR_MODE_PALL;
break;
case SDRAM_SELF_REFRESH:
tmp_reg |= FMC_SDCMR_MODE_SELF_REFRESH;
break;
case SDRAM_POWER_DOWN:
tmp_reg |= FMC_SDCMR_MODE_POWER_DOWN;
break;
case SDRAM_NORMAL:
default:
break;
case SDRAM_CLK_CONF:
tmp_reg |= FMC_SDCMR_MODE_CLOCK_CONFIG_ENA;
break;
case SDRAM_AUTO_REFRESH:
tmp_reg |= FMC_SDCMR_MODE_AUTO_REFRESH;
break;
case SDRAM_LOAD_MODE:
tmp_reg |= FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
break;
case SDRAM_PALL:
tmp_reg |= FMC_SDCMR_MODE_PALL;
break;
case SDRAM_SELF_REFRESH:
tmp_reg |= FMC_SDCMR_MODE_SELF_REFRESH;
break;
case SDRAM_POWER_DOWN:
tmp_reg |= FMC_SDCMR_MODE_POWER_DOWN;
break;
case SDRAM_NORMAL:
default:
break;
}
/* Wait for the next chance to talk to the controller */
while (FMC_SDSR & FMC_SDSR_BUSY) ;
while (FMC_SDSR & FMC_SDSR_BUSY);
/* Send the next command */
FMC_SDCMR = tmp_reg;
lib/stm32/l0/rcc.c
+12 -6
View File
@@ -293,14 +293,16 @@ void rcc_wait_for_osc_ready(enum rcc_osc osc)
/*---------------------------------------------------------------------------*/
/** @brief RCC Set HSI48 clock source to the RC48 (CRS)
*/
void rcc_set_hsi48_source_rc48(void) {
void rcc_set_hsi48_source_rc48(void)
{
RCC_CCIPR |= RCC_CCIPR_HSI48SEL;
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set HSI48 clock source to the PLL
*/
void rcc_set_hsi48_source_pll(void) {
void rcc_set_hsi48_source_pll(void)
{
RCC_CCIPR &= ~RCC_CCIPR_HSI48SEL;
}
@@ -343,7 +345,8 @@ void rcc_set_sysclk_source(enum rcc_osc osc)
void rcc_set_pll_multiplier(uint32_t factor)
{
uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PLLMUL_MASK<<RCC_CFGR_PLLMUL_SHIFT);
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
RCC_CFGR = reg | (factor << RCC_CFGR_PLLMUL_SHIFT);
}
@@ -358,7 +361,8 @@ void rcc_set_pll_multiplier(uint32_t factor)
void rcc_set_pll_divider(uint32_t factor)
{
uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PLLDIV_MASK<<RCC_CFGR_PLLDIV_SHIFT);
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT);
RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT);
}
@@ -372,7 +376,8 @@ void rcc_set_pll_divider(uint32_t factor)
void rcc_set_ppre1(uint32_t ppre)
{
uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE1_SHIFT);
}
@@ -386,7 +391,8 @@ void rcc_set_ppre1(uint32_t ppre)
void rcc_set_ppre2(uint32_t ppre)
{
uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE2_SHIFT);
}
lib/stm32/l1/flash.c
+31 -21
View File
@@ -121,39 +121,46 @@ void flash_set_ws(uint32_t ws)
FLASH_ACR = reg32;
}
void flash_unlock_pecr(void) {
void flash_unlock_pecr(void)
{
FLASH_PEKEYR = FLASH_PEKEYR_PEKEY1;
FLASH_PEKEYR = FLASH_PEKEYR_PEKEY2;
}
void flash_lock_pecr(void) {
void flash_lock_pecr(void)
{
FLASH_PECR |= FLASH_PECR_PELOCK;
}
void flash_unlock_progmem(void) {
void flash_unlock_progmem(void)
{
flash_unlock_pecr();
FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY1;
FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY2;
}
void flash_lock_progmem(void) {
void flash_lock_progmem(void)
{
FLASH_PECR |= FLASH_PECR_PRGLOCK;
}
void flash_unlock_option_bytes(void) {
void flash_unlock_option_bytes(void)
{
flash_unlock_pecr();
FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY1;
FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY2;
}
void flash_lock_option_bytes(void) {
void flash_lock_option_bytes(void)
{
FLASH_PECR |= FLASH_PECR_OPTLOCK;
}
/** @brief Unlock all segments of flash
*
*/
void flash_unlock(void) {
void flash_unlock(void)
{
flash_unlock_pecr();
flash_unlock_progmem();
flash_unlock_option_bytes();
@@ -162,7 +169,8 @@ void flash_unlock(void) {
/** @brief Lock all segments of flash
*
*/
void flash_lock(void) {
void flash_lock(void)
{
flash_lock_option_bytes();
flash_lock_progmem();
flash_lock_pecr();
@@ -173,7 +181,8 @@ void flash_lock(void) {
* @param address assumed to be in the eeprom space, no checking
* @param data word to write
*/
void eeprom_program_word(uint32_t address, uint32_t data) {
void eeprom_program_word(uint32_t address, uint32_t data)
{
flash_unlock_pecr();
/* erase only if needed */
FLASH_PECR &= ~FLASH_PECR_FTDW;
@@ -183,8 +192,9 @@ void eeprom_program_word(uint32_t address, uint32_t data) {
/** @brief Write a block of words to eeprom
*
* Writes a block of words to EEPROM at the requested address, erasing if necessary,
* and locking afterwards. Only wordwise writing is safe for writing any value
* Writes a block of words to EEPROM at the requested address, erasing if
* necessary, and locking afterwards. Only wordwise writing is safe for
* writing any value
*
* @param[in] address must point to EEPROM space, no checking!
* @param[in] data pointer to data to write
@@ -192,16 +202,16 @@ void eeprom_program_word(uint32_t address, uint32_t data) {
*/
void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words)
{
int i;
flash_unlock_pecr();
while (FLASH_SR & FLASH_SR_BSY);
/* erase only if needed */
FLASH_PECR &= ~FLASH_PECR_FTDW;
for (i = 0; i < length_in_words; i++) {
MMIO32(address + (i * sizeof(uint32_t))) = *(data+i);
while (FLASH_SR & FLASH_SR_BSY);
}
flash_lock_pecr();
int i;
flash_unlock_pecr();
while (FLASH_SR & FLASH_SR_BSY);
/* erase only if needed */
FLASH_PECR &= ~FLASH_PECR_FTDW;
for (i = 0; i < length_in_words; i++) {
MMIO32(address + (i * sizeof(uint32_t))) = *(data+i);
while (FLASH_SR & FLASH_SR_BSY);
}
flash_lock_pecr();
}