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[Style] Stylefix sweep over the whole codebase.

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This commit is contained in:
Piotr Esden-Tempski
2015-12-14 22:57:15 +01:00
parent 1f6fd11dd9
commit b1049f9a6f
39 changed files with 445 additions and 359 deletions
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2
lib/efm32/lg/adc.c
View File

@@ -87,7 +87,7 @@ void adc_disable_tailgating(uint32_t adc)
*/
void adc_set_warm_up_mode(uint32_t adc, uint32_t warmupmode)
{
ADC_CTRL(adc) = (ADC_CTRL(adc) & ~ADC_CTRL_WARMUPMODE_MASK)
ADC_CTRL(adc) = (ADC_CTRL(adc) & ~ADC_CTRL_WARMUPMODE_MASK)
| warmupmode;
}

4
lib/stm32/common/spi_common_all.c
View File

@@ -730,10 +730,10 @@ Mode | CPOL | CPHA
void spi_set_standard_mode(uint32_t spi, uint8_t mode)
{
if(mode > 3) {
if (mode > 3) {
return;
}
uint32_t reg32 = SPI_CR1(spi) & ~(SPI_CR1_CPOL | SPI_CR1_CPHA);
SPI_CR1(spi) = reg32 | mode;
}

6
lib/stm32/common/st_usbfs_core.h
View File

@@ -44,8 +44,10 @@ void st_usbfs_endpoints_reset(usbd_device *usbd_dev);
void st_usbfs_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall);
uint8_t st_usbfs_ep_stall_get(usbd_device *usbd_dev, uint8_t addr);
void st_usbfs_ep_nak_set(usbd_device *usbd_dev, uint8_t addr, uint8_t nak);
uint16_t st_usbfs_ep_write_packet(usbd_device *usbd_dev, uint8_t addr, const void *buf, uint16_t len);
uint16_t st_usbfs_ep_read_packet(usbd_device *usbd_dev, uint8_t addr, void *buf, uint16_t len);
uint16_t st_usbfs_ep_write_packet(usbd_device *usbd_dev, uint8_t addr,
const void *buf, uint16_t len);
uint16_t st_usbfs_ep_read_packet(usbd_device *usbd_dev, uint8_t addr,
void *buf, uint16_t len);
void st_usbfs_poll(usbd_device *usbd_dev);
/* These must be implemented by the device specific driver */

4
lib/stm32/f0/flash.c
View File

@@ -76,10 +76,10 @@ error, bit 5: end of operation.
uint32_t flash_get_status_flags(void)
{
return (FLASH_SR & (FLASH_SR_PGERR |
return FLASH_SR & (FLASH_SR_PGERR |
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY));
FLASH_SR_BSY);
}
/*---------------------------------------------------------------------------*/

6
lib/stm32/f0/rcc.c
View File

@@ -523,7 +523,7 @@ enum rcc_osc rcc_system_clock_source(void)
*
* @returns ::osc_t USB clock source:
*/
enum rcc_osc rcc_usb_clock_source(void)
{
return (RCC_CFGR3 & RCC_CFGR3_USBSW) ? PLL : HSI48;
@@ -669,10 +669,10 @@ void rcc_clock_setup_in_hsi48_out_48mhz(void)
{
rcc_osc_on(HSI48);
rcc_wait_for_osc_ready(HSI48);
rcc_set_hpre(RCC_CFGR_HPRE_NODIV);
rcc_set_ppre(RCC_CFGR_PPRE_NODIV);
flash_set_ws(FLASH_ACR_LATENCY_024_048MHZ);
rcc_set_sysclk_source(HSI48);

39
lib/stm32/f1/flash.c
View File

@@ -128,8 +128,9 @@ void flash_lock_upper(void)
void flash_clear_pgerr_flag_upper(void)
{
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
FLASH_SR2 |= FLASH_SR_PGERR;
}
}
/*---------------------------------------------------------------------------*/
@@ -139,8 +140,9 @@ void flash_clear_pgerr_flag_upper(void)
void flash_clear_eop_flag_upper(void)
{
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
FLASH_SR2 |= FLASH_SR_EOP;
}
}
/*---------------------------------------------------------------------------*/
@@ -150,8 +152,9 @@ void flash_clear_eop_flag_upper(void)
void flash_clear_wrprterr_flag_upper(void)
{
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
FLASH_SR2 |= FLASH_SR_WRPRTERR;
}
}
/*---------------------------------------------------------------------------*/
@@ -161,8 +164,9 @@ void flash_clear_wrprterr_flag_upper(void)
void flash_clear_bsy_flag_upper(void)
{
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
FLASH_SR2 &= ~FLASH_SR_BSY;
}
}
/*---------------------------------------------------------------------------*/
@@ -204,12 +208,14 @@ uint32_t flash_get_status_flags(void)
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY));
if (MEMORY_SIZE_REG > 512)
if (MEMORY_SIZE_REG > 512) {
flags |= (FLASH_SR2 & (FLASH_SR_PGERR |
FLASH_SR_EOP |
FLASH_SR_WRPRTERR |
FLASH_SR_BSY));
return flags;
}
return flags;
}
/*---------------------------------------------------------------------------*/
@@ -229,17 +235,21 @@ void flash_program_half_word(uint32_t address, uint16_t data)
{
flash_wait_for_last_operation();
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000))
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000)) {
FLASH_CR2 |= FLASH_CR_PG;
else FLASH_CR |= FLASH_CR_PG;
} else {
FLASH_CR |= FLASH_CR_PG;
}
MMIO16(address) = data;
flash_wait_for_last_operation();
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000))
if ((MEMORY_SIZE_REG > 512) && (address >= FLASH_BASE+0x00080000)) {
FLASH_CR2 &= ~FLASH_CR_PG;
else FLASH_CR &= ~FLASH_CR_PG;
} else {
FLASH_CR &= ~FLASH_CR_PG;
}
}
/*---------------------------------------------------------------------------*/
@@ -259,7 +269,8 @@ void flash_erase_page(uint32_t page_address)
{
flash_wait_for_last_operation();
if ((MEMORY_SIZE_REG > 512) && (page_address >= FLASH_BASE+0x00080000)) {
if ((MEMORY_SIZE_REG > 512)
&& (page_address >= FLASH_BASE+0x00080000)) {
FLASH_CR2 |= FLASH_CR_PER;
FLASH_AR2 = page_address;
FLASH_CR2 |= FLASH_CR_STRT;
@@ -271,10 +282,12 @@ void flash_erase_page(uint32_t page_address)
flash_wait_for_last_operation();
if ((MEMORY_SIZE_REG > 512) && (page_address >= FLASH_BASE+0x00080000))
if ((MEMORY_SIZE_REG > 512)
&& (page_address >= FLASH_BASE+0x00080000)) {
FLASH_CR2 &= ~FLASH_CR_PER;
else
} else {
FLASH_CR &= ~FLASH_CR_PER;
}
}
/*---------------------------------------------------------------------------*/

12
lib/stm32/f1/rcc.c
View File

@@ -509,7 +509,7 @@ void rcc_set_pllxtpre(uint32_t pllxtpre)
uint32_t rcc_rtc_clock_enabled_flag(void)
{
return RCC_BDCR & RCC_BDCR_RTCEN;
return RCC_BDCR & RCC_BDCR_RTCEN;
}
/*---------------------------------------------------------------------------*/
@@ -638,10 +638,11 @@ The prescale factor can be set to 1 (no prescale) for use when the PLL clock is
void rcc_set_usbpre(uint32_t usbpre)
{
if (usbpre)
if (usbpre) {
RCC_CFGR |= RCC_CFGR_USBPRE;
else
} else {
RCC_CFGR &= ~RCC_CFGR_USBPRE;
}
}
void rcc_set_prediv1(uint32_t prediv)
@@ -658,10 +659,11 @@ void rcc_set_prediv2(uint32_t prediv)
void rcc_set_prediv1_source(uint32_t rccsrc)
{
if (rccsrc)
if (rccsrc) {
RCC_CFGR2 |= RCC_CFGR2_PREDIV1SRC;
else
} else {
RCC_CFGR2 &= ~RCC_CFGR2_PREDIV1SRC;
}
}
/*---------------------------------------------------------------------------*/

8
lib/stm32/f3/adc.c
View File

@@ -375,7 +375,7 @@ void adc_disable_eoc_interrupt_injected(uint32_t adc)
void adc_enable_eos_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_JEOSIE;
ADC_IER(adc) |= ADC_IER_JEOSIE;
}
/*---------------------------------------------------------------------------*/
@@ -387,7 +387,7 @@ void adc_enable_eos_interrupt_injected(uint32_t adc)
void adc_disable_eos_interrupt_injected(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_JEOSIE;
ADC_IER(adc) &= ~ADC_IER_JEOSIE;
}
@@ -452,7 +452,7 @@ void adc_disable_eoc_interrupt(uint32_t adc)
void adc_enable_eos_interrupt(uint32_t adc)
{
ADC_IER(adc) |= ADC_IER_EOSIE;
ADC_IER(adc) |= ADC_IER_EOSIE;
}
/*---------------------------------------------------------------------------*/
@@ -464,7 +464,7 @@ void adc_enable_eos_interrupt(uint32_t adc)
void adc_disable_eos_interrupt(uint32_t adc)
{
ADC_IER(adc) &= ~ADC_IER_EOSIE;
ADC_IER(adc) &= ~ADC_IER_EOSIE;
}

6
lib/stm32/f3/rcc.c
View File

@@ -475,8 +475,10 @@ void rcc_usb_prescale_1(void)
void rcc_adc_prescale(uint32_t prescale1, uint32_t prescale2)
{
uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC12PRES_SHIFT) |
(RCC_CFGR2_ADCxPRES_MASK << RCC_CFGR2_ADC34PRES_SHIFT);
uint32_t clear_mask = (RCC_CFGR2_ADCxPRES_MASK
<< RCC_CFGR2_ADC12PRES_SHIFT)
| (RCC_CFGR2_ADCxPRES_MASK
<< RCC_CFGR2_ADC34PRES_SHIFT);
uint32_t set = (prescale1 << RCC_CFGR2_ADC12PRES_SHIFT) |
(prescale2 << RCC_CFGR2_ADC34PRES_SHIFT);
RCC_CFGR2 &= ~(clear_mask);

46
lib/stm32/f4/fmc.c
View File

@@ -51,7 +51,7 @@ sdram_timing(struct sdram_timing *t) {
*/
void
sdram_command(enum fmc_sdram_bank bank,
enum fmc_sdram_command cmd, int autorefresh, int modereg) {
enum fmc_sdram_command cmd, int autorefresh, int modereg) {
uint32_t tmp_reg = 0;
switch (bank) {
@@ -68,31 +68,31 @@ sdram_command(enum fmc_sdram_bank bank,
tmp_reg |= autorefresh << FMC_SDCMR_NRFS_SHIFT;
tmp_reg |= modereg << FMC_SDCMR_MRD_SHIFT;
switch (cmd) {
case SDRAM_CLK_CONF:
tmp_reg |= FMC_SDCMR_MODE_CLOCK_CONFIG_ENA;
break;
case SDRAM_AUTO_REFRESH:
tmp_reg |= FMC_SDCMR_MODE_AUTO_REFRESH;
break;
case SDRAM_LOAD_MODE:
tmp_reg |= FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
break;
case SDRAM_PALL:
tmp_reg |= FMC_SDCMR_MODE_PALL;
break;
case SDRAM_SELF_REFRESH:
tmp_reg |= FMC_SDCMR_MODE_SELF_REFRESH;
break;
case SDRAM_POWER_DOWN:
tmp_reg |= FMC_SDCMR_MODE_POWER_DOWN;
break;
case SDRAM_NORMAL:
default:
break;
case SDRAM_CLK_CONF:
tmp_reg |= FMC_SDCMR_MODE_CLOCK_CONFIG_ENA;
break;
case SDRAM_AUTO_REFRESH:
tmp_reg |= FMC_SDCMR_MODE_AUTO_REFRESH;
break;
case SDRAM_LOAD_MODE:
tmp_reg |= FMC_SDCMR_MODE_LOAD_MODE_REGISTER;
break;
case SDRAM_PALL:
tmp_reg |= FMC_SDCMR_MODE_PALL;
break;
case SDRAM_SELF_REFRESH:
tmp_reg |= FMC_SDCMR_MODE_SELF_REFRESH;
break;
case SDRAM_POWER_DOWN:
tmp_reg |= FMC_SDCMR_MODE_POWER_DOWN;
break;
case SDRAM_NORMAL:
default:
break;
}
/* Wait for the next chance to talk to the controller */
while (FMC_SDSR & FMC_SDSR_BUSY) ;
while (FMC_SDSR & FMC_SDSR_BUSY);
/* Send the next command */
FMC_SDCMR = tmp_reg;

18
lib/stm32/l0/rcc.c
View File

@@ -293,14 +293,16 @@ void rcc_wait_for_osc_ready(enum rcc_osc osc)
/*---------------------------------------------------------------------------*/
/** @brief RCC Set HSI48 clock source to the RC48 (CRS)
*/
void rcc_set_hsi48_source_rc48(void) {
void rcc_set_hsi48_source_rc48(void)
{
RCC_CCIPR |= RCC_CCIPR_HSI48SEL;
}
/*---------------------------------------------------------------------------*/
/** @brief RCC Set HSI48 clock source to the PLL
*/
void rcc_set_hsi48_source_pll(void) {
void rcc_set_hsi48_source_pll(void)
{
RCC_CCIPR &= ~RCC_CCIPR_HSI48SEL;
}
@@ -343,7 +345,8 @@ void rcc_set_sysclk_source(enum rcc_osc osc)
void rcc_set_pll_multiplier(uint32_t factor)
{
uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PLLMUL_MASK<<RCC_CFGR_PLLMUL_SHIFT);
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PLLMUL_MASK << RCC_CFGR_PLLMUL_SHIFT);
RCC_CFGR = reg | (factor << RCC_CFGR_PLLMUL_SHIFT);
}
@@ -358,7 +361,8 @@ void rcc_set_pll_multiplier(uint32_t factor)
void rcc_set_pll_divider(uint32_t factor)
{
uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PLLDIV_MASK<<RCC_CFGR_PLLDIV_SHIFT);
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PLLDIV_MASK << RCC_CFGR_PLLDIV_SHIFT);
RCC_CFGR = reg | (factor << RCC_CFGR_PLLDIV_SHIFT);
}
@@ -372,7 +376,8 @@ void rcc_set_pll_divider(uint32_t factor)
void rcc_set_ppre1(uint32_t ppre)
{
uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE1_SHIFT);
}
@@ -386,7 +391,8 @@ void rcc_set_ppre1(uint32_t ppre)
void rcc_set_ppre2(uint32_t ppre)
{
uint32_t reg = RCC_CFGR & ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
uint32_t reg = RCC_CFGR
& ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
RCC_CFGR = reg | (ppre << RCC_CFGR_PPRE2_SHIFT);
}

52
lib/stm32/l1/flash.c
View File

@@ -121,39 +121,46 @@ void flash_set_ws(uint32_t ws)
FLASH_ACR = reg32;
}
void flash_unlock_pecr(void) {
void flash_unlock_pecr(void)
{
FLASH_PEKEYR = FLASH_PEKEYR_PEKEY1;
FLASH_PEKEYR = FLASH_PEKEYR_PEKEY2;
}
void flash_lock_pecr(void) {
void flash_lock_pecr(void)
{
FLASH_PECR |= FLASH_PECR_PELOCK;
}
void flash_unlock_progmem(void) {
void flash_unlock_progmem(void)
{
flash_unlock_pecr();
FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY1;
FLASH_PRGKEYR = FLASH_PRGKEYR_PRGKEY2;
}
void flash_lock_progmem(void) {
void flash_lock_progmem(void)
{
FLASH_PECR |= FLASH_PECR_PRGLOCK;
}
void flash_unlock_option_bytes(void) {
void flash_unlock_option_bytes(void)
{
flash_unlock_pecr();
FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY1;
FLASH_OPTKEYR = FLASH_OPTKEYR_OPTKEY2;
}
void flash_lock_option_bytes(void) {
void flash_lock_option_bytes(void)
{
FLASH_PECR |= FLASH_PECR_OPTLOCK;
}
/** @brief Unlock all segments of flash
*
*/
void flash_unlock(void) {
void flash_unlock(void)
{
flash_unlock_pecr();
flash_unlock_progmem();
flash_unlock_option_bytes();
@@ -162,7 +169,8 @@ void flash_unlock(void) {
/** @brief Lock all segments of flash
*
*/
void flash_lock(void) {
void flash_lock(void)
{
flash_lock_option_bytes();
flash_lock_progmem();
flash_lock_pecr();
@@ -173,7 +181,8 @@ void flash_lock(void) {
* @param address assumed to be in the eeprom space, no checking
* @param data word to write
*/
void eeprom_program_word(uint32_t address, uint32_t data) {
void eeprom_program_word(uint32_t address, uint32_t data)
{
flash_unlock_pecr();
/* erase only if needed */
FLASH_PECR &= ~FLASH_PECR_FTDW;
@@ -183,8 +192,9 @@ void eeprom_program_word(uint32_t address, uint32_t data) {
/** @brief Write a block of words to eeprom
*
* Writes a block of words to EEPROM at the requested address, erasing if necessary,
* and locking afterwards. Only wordwise writing is safe for writing any value
* Writes a block of words to EEPROM at the requested address, erasing if
* necessary, and locking afterwards. Only wordwise writing is safe for
* writing any value
*
* @param[in] address must point to EEPROM space, no checking!
* @param[in] data pointer to data to write
@@ -192,16 +202,16 @@ void eeprom_program_word(uint32_t address, uint32_t data) {
*/
void eeprom_program_words(uint32_t address, uint32_t *data, int length_in_words)
{
int i;
flash_unlock_pecr();
while (FLASH_SR & FLASH_SR_BSY);
/* erase only if needed */
FLASH_PECR &= ~FLASH_PECR_FTDW;
for (i = 0; i < length_in_words; i++) {
MMIO32(address + (i * sizeof(uint32_t))) = *(data+i);
while (FLASH_SR & FLASH_SR_BSY);
}
flash_lock_pecr();
int i;
flash_unlock_pecr();
while (FLASH_SR & FLASH_SR_BSY);
/* erase only if needed */
FLASH_PECR &= ~FLASH_PECR_FTDW;
for (i = 0; i < length_in_words; i++) {
MMIO32(address + (i * sizeof(uint32_t))) = *(data+i);
while (FLASH_SR & FLASH_SR_BSY);
}
flash_lock_pecr();
}

6
lib/usb/usb_control.c
View File

@@ -59,7 +59,8 @@ static void stall_transaction(usbd_device *usbd_dev)
* @param ep_size
* @return
*/
static bool needs_zlp(uint16_t len, uint16_t wLength, uint8_t ep_size) {
static bool needs_zlp(uint16_t len, uint16_t wLength, uint8_t ep_size)
{
if (len < wLength) {
if (len && (len % ep_size == 0)) {
return true;
@@ -109,7 +110,8 @@ static void usb_control_send_chunk(usbd_device *usbd_dev)
usbd_dev->control_state.ctrl_len);
usbd_dev->control_state.state =
usbd_dev->control_state.needs_zlp ? DATA_IN : LAST_DATA_IN;
usbd_dev->control_state.needs_zlp ?
DATA_IN : LAST_DATA_IN;
usbd_dev->control_state.needs_zlp = false;
usbd_dev->control_state.ctrl_len = 0;
usbd_dev->control_state.ctrl_buf = NULL;

5
lib/usb/usb_efm32lg.c
View File

@@ -51,7 +51,7 @@ static usbd_device *efm32lg_usbd_init(void)
CMU_CMD = CMU_CMD_USBCCLKSEL_HFCLKNODIV;
/* wait till clock not selected */
while(!(CMU_STATUS & CMU_STATUS_USBCHFCLKSEL));
while (!(CMU_STATUS & CMU_STATUS_USBCHFCLKSEL));
USB_GINTSTS = USB_GINTSTS_MMIS;
@@ -179,7 +179,8 @@ static void efm32lg_endpoints_reset(usbd_device *usbd_dev)
usbd_dev->fifo_mem_top = usbd_dev->fifo_mem_top_ep0;
}
static void efm32lg_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)
static void efm32lg_ep_stall_set(usbd_device *usbd_dev, uint8_t addr,
uint8_t stall)
{
(void)usbd_dev;
if (addr == 0) {

3
lib/usb/usb_fx07_common.c
View File

@@ -132,7 +132,8 @@ void stm32fx07_endpoints_reset(usbd_device *usbd_dev)
}
/* Flush all tx/rx fifos */
REBASE(OTG_GRSTCTL) = OTG_GRSTCTL_TXFFLSH | OTG_GRSTCTL_TXFNUM_ALL | OTG_GRSTCTL_RXFFLSH;
REBASE(OTG_GRSTCTL) = OTG_GRSTCTL_TXFFLSH | OTG_GRSTCTL_TXFNUM_ALL
| OTG_GRSTCTL_RXFFLSH;
}
void stm32fx07_ep_stall_set(usbd_device *usbd_dev, uint8_t addr, uint8_t stall)

55
lib/usb/usb_msc.c
View File

@@ -153,8 +153,9 @@ struct usb_msc_trans {
uint32_t bytes_to_read;
uint32_t bytes_to_write;
uint32_t byte_count; /* Either read until equal to bytes_to_read or
write until equal to bytes_to_write. */
uint32_t byte_count; /* Either read until equal to
bytes_to_read or write until equal
to bytes_to_write. */
uint32_t lba_start;
uint32_t block_count;
uint32_t current_block;
@@ -288,7 +289,8 @@ static void scsi_write_6(usbd_mass_storage *ms,
buf = get_cbw_buf(trans);
trans->lba_start = ((0x1f & buf[1]) << 16) | (buf[2] << 8) | buf[3];
trans->lba_start = ((0x1f & buf[1]) << 16)
| (buf[2] << 8) | buf[3];
trans->block_count = buf[4];
trans->current_block = 0;
@@ -325,7 +327,8 @@ static void scsi_read_10(usbd_mass_storage *ms,
buf = get_cbw_buf(trans);
trans->lba_start = (buf[2] << 24) | (buf[3] << 16) | (buf[4] << 8) | buf[5];
trans->lba_start = (buf[2] << 24) | (buf[3] << 16)
| (buf[4] << 8) | buf[5];
trans->block_count = (buf[7] << 8) | buf[8];
/* TODO: Check the lba & block_count for range. */
@@ -384,7 +387,8 @@ static void scsi_request_sense(usbd_mass_storage *ms,
buf = &trans->cbw.cbw.CBWCB[0];
trans->bytes_to_write = buf[4]; /* allocation length */
memcpy(trans->msd_buf, _spc3_request_sense, sizeof(_spc3_request_sense));
memcpy(trans->msd_buf, _spc3_request_sense,
sizeof(_spc3_request_sense));
trans->msd_buf[2] = ms->sense.key;
trans->msd_buf[12] = ms->sense.asc;
@@ -445,7 +449,8 @@ static void scsi_inquiry(usbd_mass_storage *ms,
if (0 == evpd) {
size_t len;
trans->bytes_to_write = sizeof(_spc3_inquiry_response);
memcpy(trans->msd_buf, _spc3_inquiry_response, sizeof(_spc3_inquiry_response));
memcpy(trans->msd_buf, _spc3_inquiry_response,
sizeof(_spc3_inquiry_response));
len = strlen(ms->vendor_id);
len = MIN(len, 8);
@@ -457,9 +462,11 @@ static void scsi_inquiry(usbd_mass_storage *ms,
len = strlen(ms->product_revision_level);
len = MIN(len, 4);
memcpy(&trans->msd_buf[32], ms->product_revision_level, len);
memcpy(&trans->msd_buf[32], ms->product_revision_level,
len);
trans->csw.csw.dCSWDataResidue = sizeof(_spc3_inquiry_response);
trans->csw.csw.dCSWDataResidue =
sizeof(_spc3_inquiry_response);
set_sbc_status_good(ms);
} else {
@@ -564,7 +571,7 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)
if (trans->byte_count < trans->bytes_to_read) {
if (0 < trans->block_count) {
if ((0 == trans->byte_count) && (NULL != ms->lock)){
if ((0 == trans->byte_count) && (NULL != ms->lock)) {
(*ms->lock)();
}
}
@@ -580,7 +587,8 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)
uint32_t lba;
lba = trans->lba_start + trans->current_block;
if (0 != (*ms->write_block)(lba, trans->msd_buf)) {
if (0 != (*ms->write_block)(lba,
trans->msd_buf)) {
/* Error */
}
trans->current_block++;
@@ -596,7 +604,8 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)
uint32_t lba;
lba = trans->lba_start + trans->current_block;
if (0 != (*ms->read_block)(lba, trans->msd_buf)) {
if (0 != (*ms->read_block)(lba,
trans->msd_buf)) {
/* Error */
}
trans->current_block++;
@@ -614,12 +623,13 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)
uint32_t lba;
lba = trans->lba_start + trans->current_block;
if (0 != (*ms->write_block)(lba, trans->msd_buf)) {
if (0 != (*ms->write_block)(lba,
trans->msd_buf)) {
/* Error */
}
trans->current_block = 0;
if (NULL != ms->unlock){
if (NULL != ms->unlock) {
(*ms->unlock)();
}
}
@@ -633,7 +643,8 @@ static void msc_data_rx_cb(usbd_device *usbd_dev, uint8_t ep)
if (0 < left) {
max_len = MIN(ms->ep_out_size, left);
p = &trans->csw.buf[trans->csw_sent];
len = usbd_ep_write_packet(usbd_dev, ms->ep_in, p, max_len);
len = usbd_ep_write_packet(usbd_dev, ms->ep_in, p,
max_len);
trans->csw_sent += len;
}
}
@@ -656,7 +667,8 @@ static void msc_data_tx_cb(usbd_device *usbd_dev, uint8_t ep)
uint32_t lba;
lba = trans->lba_start + trans->current_block;
if (0 != (*ms->read_block)(lba, trans->msd_buf)) {
if (0 != (*ms->read_block)(lba,
trans->msd_buf)) {
/* Error */
}
trans->current_block++;
@@ -672,7 +684,7 @@ static void msc_data_tx_cb(usbd_device *usbd_dev, uint8_t ep)
if (0 < trans->block_count) {
if (trans->current_block == trans->block_count) {
trans->current_block = 0;
if (NULL != ms->unlock){
if (NULL != ms->unlock) {
(*ms->unlock)();
}
}
@@ -707,8 +719,9 @@ static void msc_data_tx_cb(usbd_device *usbd_dev, uint8_t ep)
* interface.
*/
static int msc_control_request(usbd_device *usbd_dev,
struct usb_setup_data *req, uint8_t **buf, uint16_t *len,
usbd_control_complete_callback *complete)
struct usb_setup_data *req, uint8_t **buf,
uint16_t *len,
usbd_control_complete_callback *complete)
{
(void)complete;
(void)usbd_dev;
@@ -777,8 +790,10 @@ usbd_mass_storage *usb_msc_init(usbd_device *usbd_dev,
const char *product_id,
const char *product_revision_level,
const uint32_t block_count,
int (*read_block)(uint32_t lba, uint8_t *copy_to),
int (*write_block)(uint32_t lba, const uint8_t *copy_from))
int (*read_block)(uint32_t lba,
uint8_t *copy_to),
int (*write_block)(uint32_t lba,
const uint8_t *copy_from))
{
_mass_storage.usbd_dev = usbd_dev;
_mass_storage.ep_in = ep_in;

22
lib/usb/usb_standard.c
View File

@@ -45,8 +45,9 @@ int usbd_register_set_config_callback(usbd_device *usbd_dev,
int i;
for (i = 0; i < MAX_USER_SET_CONFIG_CALLBACK; i++) {
if (usbd_dev->user_callback_set_config[i])
if (usbd_dev->user_callback_set_config[i]) {
continue;
}
usbd_dev->user_callback_set_config[i] = callback;
return 0;
@@ -56,7 +57,7 @@ int usbd_register_set_config_callback(usbd_device *usbd_dev,
}
void usbd_register_set_altsetting_callback(usbd_device *usbd_dev,
usbd_set_altsetting_callback callback)
usbd_set_altsetting_callback callback)
{
usbd_dev->user_callback_set_altsetting = callback;
}
@@ -253,9 +254,10 @@ static int usb_standard_set_configuration(usbd_device *usbd_dev,
(void)buf;
(void)len;
if(req->wValue > 0) {
if (req->wValue > 0) {
for (i = 0; i < usbd_dev->desc->bNumConfigurations; i++) {
if (req->wValue == usbd_dev->config[i].bConfigurationValue) {
if (req->wValue
== usbd_dev->config[i].bConfigurationValue) {
found_index = i;
break;
}
@@ -310,7 +312,8 @@ static int usb_standard_get_configuration(usbd_device *usbd_dev,
if (*len > 1) {
*len = 1;
}
const struct usb_config_descriptor *cfg = &usbd_dev->config[usbd_dev->current_config - 1];
const struct usb_config_descriptor *cfg =
&usbd_dev->config[usbd_dev->current_config - 1];
(*buf)[0] = cfg->bConfigurationValue;
return 1;
@@ -320,7 +323,8 @@ static int usb_standard_set_interface(usbd_device *usbd_dev,
struct usb_setup_data *req,
uint8_t **buf, uint16_t *len)
{
const struct usb_config_descriptor *cfx = &usbd_dev->config[usbd_dev->current_config - 1];
const struct usb_config_descriptor *cfx =
&usbd_dev->config[usbd_dev->current_config - 1];
const struct usb_interface *iface;
(void)buf;
@@ -343,7 +347,8 @@ static int usb_standard_set_interface(usbd_device *usbd_dev,
if (usbd_dev->user_callback_set_altsetting) {
usbd_dev->user_callback_set_altsetting(usbd_dev,
req->wIndex, req->wValue);
req->wIndex,
req->wValue);
}
*len = 0;
@@ -356,7 +361,8 @@ static int usb_standard_get_interface(usbd_device *usbd_dev,
uint8_t **buf, uint16_t *len)
{
uint8_t *cur_altsetting;
const struct usb_config_descriptor *cfx = &usbd_dev->config[usbd_dev->current_config - 1];
const struct usb_config_descriptor *cfx =
&usbd_dev->config[usbd_dev->current_config - 1];
if (req->wIndex >= cfx->bNumInterfaces) {
return USBD_REQ_NOTSUPP;

6
lib/vf6xx/ccm.c
View File

@@ -102,8 +102,7 @@ uint32_t ccm_get_pll_pfd(uint32_t pfd_sel, uint32_t pll_pfd, uint32_t pll_clk)
uint64_t pll_pfd_clk;
uint32_t pll_pfd_frac = pll_pfd;
switch(pfd_sel)
{
switch (pfd_sel) {
case CCM_CCSR_PLL_PFD_CLK_SEL_MAIN:
return pll_clk;
case CCM_CCSR_PLL_PFD_CLK_SEL_PFD1:
@@ -164,8 +163,7 @@ void ccm_calculate_clocks()
ipg_clk_div += 1;
/* Get Cortex-A5 core clock from system clock selection */
switch(ccsr & CCM_CCSR_SYS_CLK_SEL_MASK)
{
switch (ccsr & CCM_CCSR_SYS_CLK_SEL_MASK) {
case CCM_CCSR_SYS_CLK_SEL_FAST:
ccm_core_clk = 24000000;
break;