[Style] Stylefix sweep over the whole codebase.
This commit is contained in:
Piotr Esden-Tempski
@@ -1,16 +1,16 @@
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/** @defgroup ssi_defines Synchronous Serial Interface
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*
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*
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* @brief <b>Defined Constants and Types for the LM4F Synchronous Serial Interface (SSI)</b>
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*
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*
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* @ingroup LM4Fxx_defines
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*
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*
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* @version 1.0.0
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*
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*
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* @author @htmlonly © @endhtmlonly 2014
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* Tiago Costa <nippius+github@gmail.com>
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*
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*
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* @date 11 June 2014
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*
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*
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* LGPL License Terms @ref lgpl_license
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*/
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@@ -67,7 +67,7 @@
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/* SSI Satus */
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#define SSI_SR(port) MMIO32((port) + 0x00C)
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/* SSI Clock Prescale */
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#define SSI_CPSR(port) MMIO32((port) + 0x010)
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@@ -84,7 +84,7 @@
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#define SSI_ICR(port) MMIO32((port) + 0x020)
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/* SSI DMA Control */
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#define SSI_DMACTL(port) MMIO32((port) + 0x024)
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#define SSI_DMACTL(port) MMIO32((port) + 0x024)
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/* SSI Clock Configuration */
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#define SSI_CC(port) MMIO32((port) + 0xFC8)
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@@ -115,4 +115,4 @@ END_DECLS
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/**@}*/
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#endif /* LM4F_SSI_H */
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@@ -33,16 +33,20 @@
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/* --- Static Memory Controller (SMC) registers ---------------------------- */
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/* Setup Register */
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#define SMC_SETUP(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) + 0x00)
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#define SMC_SETUP(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
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+ 0x00)
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/* Pulse Register */
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#define SMC_PULSE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) + 0x04)
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#define SMC_PULSE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
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+ 0x04)
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/* Cycle Register */
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#define SMC_CYCLE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) + 0x08)
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#define SMC_CYCLE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
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+ 0x08)
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/* Mode Register */
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#define SMC_MODE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) + 0x0C)
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#define SMC_MODE(CS_number) MMIO32(SMC_BASE + 0x10*(CS_number) \
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+ 0x0C)
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/* Off Chip Memory Scrambling Mode Register */
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#define SMC_OCMS MMIO32(SMC_BASE + 0x80)
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@@ -117,19 +117,24 @@
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#define SMC_ECC_PR15 MMIO32(SMC_BASE + 0x6C)
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/* Setup Register */
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#define SMC_SETUP(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x70)
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#define SMC_SETUP(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \
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+ 0x70)
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/* Pulse Register */
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#define SMC_PULSE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x74)
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#define SMC_PULSE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \
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+ 0x74)
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/* Cycle Register */
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#define SMC_CYCLE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x78)
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#define SMC_CYCLE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \
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+ 0x78)
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/* Timings Register */
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#define SMC_TIMINGS(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x7C)
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#define SMC_TIMINGS(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \
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+ 0x7C)
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/* Mode Register */
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#define SMC_MODE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) + 0x80)
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#define SMC_MODE(CS_number) MMIO32(SMC_BASE + 0x14*(CS_number) \
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+ 0x80)
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/* Off Chip Memory Scrambling Mode Register */
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#define SMC_OCMS MMIO32(SMC_BASE + 0x110)
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@@ -374,10 +379,14 @@
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#define SMC_ECC_MD_ECC_PAGESIZE_MASK (0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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/* ECC Page Size Values */
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#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 (0x00 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 (0x01 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 (0x02 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 (0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS512_16 \
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(0x00 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32 \
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(0x01 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64 \
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(0x02 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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#define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128 \
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(0x03 << SMC_ECC_MD_ECC_PAGESIZE_SHIFT)
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/* --- SMC ECC Status Register 1 (SMC_ECC_SR1) ----------------------------- */
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@@ -144,10 +144,10 @@ error "This file should not be included directly, it is included with fsmc.h"
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* out those bits after you have computed values for CR2 and
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* TR2 and put them into CR1 and TR1
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*/
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#define FMC_SDTR_DNC_MASK ( FMC_SDTR_TRP_MASK| FMC_SDTR_TRC_MASK )
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#define FMC_SDCR_DNC_MASK ( FMC_SDCR_SDCLK_MASK |\
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FMC_SDCR_RPIPE_MASK |\
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FMC_SDCR_RBURST )
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#define FMC_SDTR_DNC_MASK (FMC_SDTR_TRP_MASK | FMC_SDTR_TRC_MASK)
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#define FMC_SDCR_DNC_MASK (FMC_SDCR_SDCLK_MASK | \
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FMC_SDCR_RPIPE_MASK | \
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FMC_SDCR_RBURST)
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/* --- FMC_SDCMR values --------------------------------------------------- */
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@@ -240,7 +240,9 @@ enum fmc_sdram_command { SDRAM_CLK_CONF, SDRAM_NORMAL, SDRAM_PALL,
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SDRAM_AUTO_REFRESH, SDRAM_LOAD_MODE,
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SDRAM_SELF_REFRESH, SDRAM_POWER_DOWN };
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/* Send an array of timing parameters (indices above) to create SDTR register value */
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/* Send an array of timing parameters (indices above) to create SDTR register
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* value
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*/
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uint32_t sdram_timing(struct sdram_timing *t);
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void sdram_command(enum fmc_sdram_bank bank, enum fmc_sdram_command cmd,
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int autorefresh, int modereg);
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@@ -74,12 +74,12 @@
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#define USART1_BASE (PERIPH_BASE_APB2 + 0x1000)
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#define USART6_BASE (PERIPH_BASE_APB2 + 0x1400)
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/* PERIPH_BASE_APB2 + 0x1800 (0x4001 1800 - 0x4001 1FFF): Reserved */
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#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) /* TODO */
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#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) /* TODO */
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#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) /* TODO */
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#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) /* TODO */
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#define ADC1_BASE (PERIPH_BASE_APB2 + 0x2000) /* TODO */
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#define ADC2_BASE (PERIPH_BASE_APB2 + 0x2100) /* TODO */
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#define ADC3_BASE (PERIPH_BASE_APB2 + 0x2200) /* TODO */
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#define ADC_COMMON_BASE (PERIPH_BASE_APB2 + 0x2300) /* TODO */
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/* PERIPH_BASE_APB2 + 0x2400 (0x4001 2400 - 0x4001 27FF): Reserved */
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#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) /* SDMMC */
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#define SDIO_BASE (PERIPH_BASE_APB2 + 0x2C00) /* SDMMC */
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/* PERIPH_BASE_APB2 + 0x2C00 (0x4001 2C00 - 0x4001 2FFF): Reserved */
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#define SPI1_BASE (PERIPH_BASE_APB2 + 0x3000)
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#define SPI4_BASE (PERIPH_BASE_APB2 + 0x3400)
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@@ -766,7 +766,7 @@ enum rcc_periph_clken {
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SCC_FLASH = _REG_BIT(RCC_AHB1SMENR_OFFSET, 8),
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SCC_DMA2 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 1),
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SCC_DMA1 = _REG_BIT(RCC_AHB1SMENR_OFFSET, 0),
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/* AHB2 peripherals in sleep mode */
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SCC_RNG = _REG_BIT(RCC_AHB2SMENR_OFFSET, 18),
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SCC_AES = _REG_BIT(RCC_AHB2SMENR_OFFSET, 16),
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@@ -895,7 +895,7 @@ enum rcc_periph_rst {
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RST_TIM1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 11),
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RST_SDMMC1 = _REG_BIT(RCC_APB2RSTR_OFFSET, 10),
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RST_SYSCFG = _REG_BIT(RCC_APB2RSTR_OFFSET, 0),
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};
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#include <libopencm3/stm32/common/rcc_common_all.h>
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@@ -443,12 +443,12 @@
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#define OTG_HCINT_FRMOR (1 << 9)
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#define OTG_HCINT_BBERR (1 << 8)
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#define OTG_HCINT_TXERR (1 << 7)
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// Note: OTG_HCINT_NYET: Only in OTG_HS
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/* Note: OTG_HCINT_NYET: Only in OTG_HS */
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#define OTG_HCINT_NYET (1 << 6)
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#define OTG_HCINT_ACK (1 << 5)
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#define OTG_HCINT_NAK (1 << 4)
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#define OTG_HCINT_STALL (1 << 3)
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// Note: OTG_HCINT_AHBERR: Only in OTG_HS
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/* Note: OTG_HCINT_AHBERR: Only in OTG_HS */
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#define OTG_HCINT_AHBERR (1 << 2)
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#define OTG_HCINT_CHH (1 << 1)
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#define OTG_HCINT_XFRC (1 << 0)
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@@ -459,18 +459,18 @@
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#define OTG_HCINTMSK_FRMORM (1 << 9)
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#define OTG_HCINTMSK_BBERRM (1 << 8)
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#define OTG_HCINTMSK_TXERRM (1 << 7)
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// Note: OTG_HCINTMSK_NYET: Only in OTG_HS
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/* Note: OTG_HCINTMSK_NYET: Only in OTG_HS */
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#define OTG_HCINTMSK_NYET (1 << 6)
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#define OTG_HCINTMSK_ACKM (1 << 5)
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#define OTG_HCINTMSK_NAKM (1 << 4)
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#define OTG_HCINTMSK_STALLM (1 << 3)
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// Note: OTG_HCINTMSK_AHBERR: Only in OTG_HS
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/* Note: OTG_HCINTMSK_AHBERR: Only in OTG_HS */
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#define OTG_HCINTMSK_AHBERR (1 << 2)
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#define OTG_HCINTMSK_CHHM (1 << 1)
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#define OTG_HCINTMSK_XFRCM (1 << 0)
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/* OTG Host channel-x transfer size register (OTG_HCTSIZx) */
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// Note: OTG_HCTSIZ_DOPING: Only in OTG_HS
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/* Note: OTG_HCTSIZ_DOPING: Only in OTG_HS */
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#define OTG_HCTSIZ_DOPING (1 << 31)
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#define OTG_HCTSIZ_DPID_DATA0 (0x0 << 29)
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#define OTG_HCTSIZ_DPID_DATA1 (0x2 << 29)
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@@ -32,67 +32,67 @@
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/***********************************************************************/
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/* Core Global Control and Status Registers */
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#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + OTG_GOTGCTL)
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#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + OTG_GOTGINT)
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#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + OTG_GAHBCFG)
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#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + OTG_GUSBCFG)
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#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + OTG_GRSTCTL)
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#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + OTG_GINTSTS)
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#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + OTG_GINTMSK)
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#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSR)
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#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSP)
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#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GRXFSIZ)
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#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GNPTXFSIZ)
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#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_GNPTXSTS)
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#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + OTG_GCCFG)
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#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + OTG_CID)
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#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_HPTXFSIZ)
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#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTXF(x))
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#define OTG_FS_GOTGCTL MMIO32(USB_OTG_FS_BASE + OTG_GOTGCTL)
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#define OTG_FS_GOTGINT MMIO32(USB_OTG_FS_BASE + OTG_GOTGINT)
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#define OTG_FS_GAHBCFG MMIO32(USB_OTG_FS_BASE + OTG_GAHBCFG)
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#define OTG_FS_GUSBCFG MMIO32(USB_OTG_FS_BASE + OTG_GUSBCFG)
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#define OTG_FS_GRSTCTL MMIO32(USB_OTG_FS_BASE + OTG_GRSTCTL)
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#define OTG_FS_GINTSTS MMIO32(USB_OTG_FS_BASE + OTG_GINTSTS)
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#define OTG_FS_GINTMSK MMIO32(USB_OTG_FS_BASE + OTG_GINTMSK)
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#define OTG_FS_GRXSTSR MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSR)
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#define OTG_FS_GRXSTSP MMIO32(USB_OTG_FS_BASE + OTG_GRXSTSP)
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#define OTG_FS_GRXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GRXFSIZ)
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#define OTG_FS_GNPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_GNPTXFSIZ)
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#define OTG_FS_GNPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_GNPTXSTS)
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#define OTG_FS_GCCFG MMIO32(USB_OTG_FS_BASE + OTG_GCCFG)
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#define OTG_FS_CID MMIO32(USB_OTG_FS_BASE + OTG_CID)
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#define OTG_FS_HPTXFSIZ MMIO32(USB_OTG_FS_BASE + OTG_HPTXFSIZ)
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#define OTG_FS_DIEPTXF(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTXF(x))
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/* Host-mode Control and Status Registers */
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#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + OTG_HCFG)
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#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + OTG_HFIR)
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#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + OTG_HFNUM)
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#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_HPTXSTS)
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#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + OTG_HAINT)
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#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_HAINTMSK)
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#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + OTG_HPRT)
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#define OTG_FS_HCCHAR(x) MMIO32(USB_OTG_FS_BASE + OTG_HCCHAR(x))
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#define OTG_FS_HCINT(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINT(x))
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#define OTG_FS_HCINTMSK(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINTMSK(x))
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#define OTG_FS_HCTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_HCTSIZ(x))
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#define OTG_FS_HCFG MMIO32(USB_OTG_FS_BASE + OTG_HCFG)
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#define OTG_FS_HFIR MMIO32(USB_OTG_FS_BASE + OTG_HFIR)
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#define OTG_FS_HFNUM MMIO32(USB_OTG_FS_BASE + OTG_HFNUM)
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#define OTG_FS_HPTXSTS MMIO32(USB_OTG_FS_BASE + OTG_HPTXSTS)
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#define OTG_FS_HAINT MMIO32(USB_OTG_FS_BASE + OTG_HAINT)
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#define OTG_FS_HAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_HAINTMSK)
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#define OTG_FS_HPRT MMIO32(USB_OTG_FS_BASE + OTG_HPRT)
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#define OTG_FS_HCCHAR(x) MMIO32(USB_OTG_FS_BASE + OTG_HCCHAR(x))
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#define OTG_FS_HCINT(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINT(x))
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#define OTG_FS_HCINTMSK(x) MMIO32(USB_OTG_FS_BASE + OTG_HCINTMSK(x))
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#define OTG_FS_HCTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_HCTSIZ(x))
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/* Device-mode Control and Status Registers */
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#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + OTG_DCFG)
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#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + OTG_DCTL)
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#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + OTG_DSTS)
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#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPMSK)
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#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DOEPMSK)
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#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + OTG_DAINT)
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#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_DAINTMSK)
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#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + OTG_DVBUSDIS)
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#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + OTG_DVBUSPULSE)
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#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPEMPMSK)
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#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL0)
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#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL(x))
|
||||
#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL0)
|
||||
#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL(x))
|
||||
#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPINT(x))
|
||||
#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPINT(x))
|
||||
#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ0)
|
||||
#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ0)
|
||||
#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ(x))
|
||||
#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + OTG_DTXFSTS(x))
|
||||
#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ(x))
|
||||
#define OTG_FS_DCFG MMIO32(USB_OTG_FS_BASE + OTG_DCFG)
|
||||
#define OTG_FS_DCTL MMIO32(USB_OTG_FS_BASE + OTG_DCTL)
|
||||
#define OTG_FS_DSTS MMIO32(USB_OTG_FS_BASE + OTG_DSTS)
|
||||
#define OTG_FS_DIEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPMSK)
|
||||
#define OTG_FS_DOEPMSK MMIO32(USB_OTG_FS_BASE + OTG_DOEPMSK)
|
||||
#define OTG_FS_DAINT MMIO32(USB_OTG_FS_BASE + OTG_DAINT)
|
||||
#define OTG_FS_DAINTMSK MMIO32(USB_OTG_FS_BASE + OTG_DAINTMSK)
|
||||
#define OTG_FS_DVBUSDIS MMIO32(USB_OTG_FS_BASE + OTG_DVBUSDIS)
|
||||
#define OTG_FS_DVBUSPULSE MMIO32(USB_OTG_FS_BASE + OTG_DVBUSPULSE)
|
||||
#define OTG_FS_DIEPEMPMSK MMIO32(USB_OTG_FS_BASE + OTG_DIEPEMPMSK)
|
||||
#define OTG_FS_DIEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL0)
|
||||
#define OTG_FS_DIEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPCTL(x))
|
||||
#define OTG_FS_DOEPCTL0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL0)
|
||||
#define OTG_FS_DOEPCTL(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPCTL(x))
|
||||
#define OTG_FS_DIEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPINT(x))
|
||||
#define OTG_FS_DOEPINT(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPINT(x))
|
||||
#define OTG_FS_DIEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ0)
|
||||
#define OTG_FS_DOEPTSIZ0 MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ0)
|
||||
#define OTG_FS_DIEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DIEPTSIZ(x))
|
||||
#define OTG_FS_DTXFSTS(x) MMIO32(USB_OTG_FS_BASE + OTG_DTXFSTS(x))
|
||||
#define OTG_FS_DOEPTSIZ(x) MMIO32(USB_OTG_FS_BASE + OTG_DOEPTSIZ(x))
|
||||
|
||||
/* Power and clock gating control and status register */
|
||||
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + OTG_PCGCCTL)
|
||||
#define OTG_FS_PCGCCTL MMIO32(USB_OTG_FS_BASE + OTG_PCGCCTL)
|
||||
|
||||
/* Data FIFO */
|
||||
#define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \
|
||||
+ (((x) + 1) \
|
||||
<< 12)))
|
||||
#define OTG_FS_FIFO(x) (&MMIO32(USB_OTG_FS_BASE \
|
||||
+ (((x) + 1) \
|
||||
<< 12)))
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
@@ -27,84 +27,84 @@
|
||||
/* OTG_HS specific registers */
|
||||
|
||||
/* Host-mode Control and Status Registers */
|
||||
#define OTG_HCSPLT(x) (0x504 + 0x20*(x))
|
||||
#define OTG_HCDMA(x) (0x514 + 0x20*(x))
|
||||
#define OTG_HCSPLT(x) (0x504 + 0x20*(x))
|
||||
#define OTG_HCDMA(x) (0x514 + 0x20*(x))
|
||||
|
||||
/* Device-mode Control and Status Registers */
|
||||
#define OTG_DEACHHINT 0x838
|
||||
#define OTG_DEACHHINTMSK 0x83C
|
||||
#define OTG_DIEPEACHMSK1 0x844
|
||||
#define OTG_DOEPEACHMSK1 0x884
|
||||
#define OTG_DIEPDMA(x) (0x914 + 0x20*(x))
|
||||
#define OTG_DOEPDMA(x) (0xB14 + 0x20*(x))
|
||||
#define OTG_DEACHHINT 0x838
|
||||
#define OTG_DEACHHINTMSK 0x83C
|
||||
#define OTG_DIEPEACHMSK1 0x844
|
||||
#define OTG_DOEPEACHMSK1 0x884
|
||||
#define OTG_DIEPDMA(x) (0x914 + 0x20*(x))
|
||||
#define OTG_DOEPDMA(x) (0xB14 + 0x20*(x))
|
||||
|
||||
|
||||
|
||||
/***********************************************************************/
|
||||
|
||||
/* Core Global Control and Status Registers */
|
||||
#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
|
||||
#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
|
||||
#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
|
||||
#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
|
||||
#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
|
||||
#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
|
||||
#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
|
||||
#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
|
||||
#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
|
||||
#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
|
||||
#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
|
||||
#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
|
||||
#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
|
||||
#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID)
|
||||
#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
|
||||
#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))
|
||||
#define OTG_HS_GOTGCTL MMIO32(USB_OTG_HS_BASE + OTG_GOTGCTL)
|
||||
#define OTG_HS_GOTGINT MMIO32(USB_OTG_HS_BASE + OTG_GOTGINT)
|
||||
#define OTG_HS_GAHBCFG MMIO32(USB_OTG_HS_BASE + OTG_GAHBCFG)
|
||||
#define OTG_HS_GUSBCFG MMIO32(USB_OTG_HS_BASE + OTG_GUSBCFG)
|
||||
#define OTG_HS_GRSTCTL MMIO32(USB_OTG_HS_BASE + OTG_GRSTCTL)
|
||||
#define OTG_HS_GINTSTS MMIO32(USB_OTG_HS_BASE + OTG_GINTSTS)
|
||||
#define OTG_HS_GINTMSK MMIO32(USB_OTG_HS_BASE + OTG_GINTMSK)
|
||||
#define OTG_HS_GRXSTSR MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSR)
|
||||
#define OTG_HS_GRXSTSP MMIO32(USB_OTG_HS_BASE + OTG_GRXSTSP)
|
||||
#define OTG_HS_GRXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GRXFSIZ)
|
||||
#define OTG_HS_GNPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_GNPTXFSIZ)
|
||||
#define OTG_HS_GNPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_GNPTXSTS)
|
||||
#define OTG_HS_GCCFG MMIO32(USB_OTG_HS_BASE + OTG_GCCFG)
|
||||
#define OTG_HS_CID MMIO32(USB_OTG_HS_BASE + OTG_CID)
|
||||
#define OTG_HS_HPTXFSIZ MMIO32(USB_OTG_HS_BASE + OTG_HPTXFSIZ)
|
||||
#define OTG_HS_DIEPTXF(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPTXF(x))
|
||||
|
||||
/* Host-mode Control and Status Registers */
|
||||
#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
|
||||
#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
|
||||
#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
|
||||
#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
|
||||
#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
|
||||
#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
|
||||
#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
|
||||
#define OTG_HS_HCCHAR(x) MMIO32(USB_OTG_HS_BASE + OTG_HCCHAR(x))
|
||||
#define OTG_HS_HCSPLT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCSPLT(x))
|
||||
#define OTG_HS_HCINT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINT(x))
|
||||
#define OTG_HS_HCINTMSK(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSK(x))
|
||||
#define OTG_HS_HCTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZ(x))
|
||||
#define OTG_HS_HCDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_HCDMA(x))
|
||||
#define OTG_HS_HCFG MMIO32(USB_OTG_HS_BASE + OTG_HCFG)
|
||||
#define OTG_HS_HFIR MMIO32(USB_OTG_HS_BASE + OTG_HFIR)
|
||||
#define OTG_HS_HFNUM MMIO32(USB_OTG_HS_BASE + OTG_HFNUM)
|
||||
#define OTG_HS_HPTXSTS MMIO32(USB_OTG_HS_BASE + OTG_HPTXSTS)
|
||||
#define OTG_HS_HAINT MMIO32(USB_OTG_HS_BASE + OTG_HAINT)
|
||||
#define OTG_HS_HAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_HAINTMSK)
|
||||
#define OTG_HS_HPRT MMIO32(USB_OTG_HS_BASE + OTG_HPRT)
|
||||
#define OTG_HS_HCCHAR(x) MMIO32(USB_OTG_HS_BASE + OTG_HCCHAR(x))
|
||||
#define OTG_HS_HCSPLT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCSPLT(x))
|
||||
#define OTG_HS_HCINT(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINT(x))
|
||||
#define OTG_HS_HCINTMSK(x) MMIO32(USB_OTG_HS_BASE + OTG_HCINTMSK(x))
|
||||
#define OTG_HS_HCTSIZ(x) MMIO32(USB_OTG_HS_BASE + OTG_HCTSIZ(x))
|
||||
#define OTG_HS_HCDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_HCDMA(x))
|
||||
|
||||
/* Device-mode Control and Status Registers */
|
||||
#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
|
||||
#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
|
||||
#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
|
||||
#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
|
||||
#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
|
||||
#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
|
||||
#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
|
||||
#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
|
||||
#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
|
||||
#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
|
||||
#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
|
||||
#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
|
||||
#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
|
||||
#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
|
||||
#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
|
||||
#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
|
||||
#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
|
||||
#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
|
||||
#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
|
||||
OTG_DIEPTSIZ(x))
|
||||
#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
|
||||
#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
|
||||
OTG_DOEPTSIZ(x))
|
||||
#define OTG_HS_DEACHHINT MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINT)
|
||||
#define OTG_HS_DEACHHINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINTMSK)
|
||||
#define OTG_HS_DIEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEACHMSK1)
|
||||
#define OTG_HS_DOEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPEACHMSK1)
|
||||
#define OTG_HS_DIEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPDMA(x))
|
||||
#define OTG_HS_DOEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPDMA(x))
|
||||
#define OTG_HS_DCFG MMIO32(USB_OTG_HS_BASE + OTG_DCFG)
|
||||
#define OTG_HS_DCTL MMIO32(USB_OTG_HS_BASE + OTG_DCTL)
|
||||
#define OTG_HS_DSTS MMIO32(USB_OTG_HS_BASE + OTG_DSTS)
|
||||
#define OTG_HS_DIEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPMSK)
|
||||
#define OTG_HS_DOEPMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPMSK)
|
||||
#define OTG_HS_DAINT MMIO32(USB_OTG_HS_BASE + OTG_DAINT)
|
||||
#define OTG_HS_DAINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DAINTMSK)
|
||||
#define OTG_HS_DVBUSDIS MMIO32(USB_OTG_HS_BASE + OTG_DVBUSDIS)
|
||||
#define OTG_HS_DVBUSPULSE MMIO32(USB_OTG_HS_BASE + OTG_DVBUSPULSE)
|
||||
#define OTG_HS_DIEPEMPMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEMPMSK)
|
||||
#define OTG_HS_DIEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL0)
|
||||
#define OTG_HS_DIEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPCTL(x))
|
||||
#define OTG_HS_DOEPCTL0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL0)
|
||||
#define OTG_HS_DOEPCTL(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPCTL(x))
|
||||
#define OTG_HS_DIEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPINT(x))
|
||||
#define OTG_HS_DOEPINT(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPINT(x))
|
||||
#define OTG_HS_DIEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DIEPTSIZ0)
|
||||
#define OTG_HS_DOEPTSIZ0 MMIO32(USB_OTG_HS_BASE + OTG_DOEPTSIZ0)
|
||||
#define OTG_HS_DIEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
|
||||
OTG_DIEPTSIZ(x))
|
||||
#define OTG_HS_DTXFSTS(x) MMIO32(USB_OTG_HS_BASE + OTG_DTXFSTS(x))
|
||||
#define OTG_HS_DOEPTSIZ(x) MMIO32(USB_OTG_HS_BASE + \
|
||||
OTG_DOEPTSIZ(x))
|
||||
#define OTG_HS_DEACHHINT MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINT)
|
||||
#define OTG_HS_DEACHHINTMSK MMIO32(USB_OTG_HS_BASE + OTG_DEACHHINTMSK)
|
||||
#define OTG_HS_DIEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DIEPEACHMSK1)
|
||||
#define OTG_HS_DOEPEACHMSK MMIO32(USB_OTG_HS_BASE + OTG_DOEPEACHMSK1)
|
||||
#define OTG_HS_DIEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DIEPDMA(x))
|
||||
#define OTG_HS_DOEPDMA(x) MMIO32(USB_OTG_HS_BASE + OTG_DOEPDMA(x))
|
||||
|
||||
/* Power and clock gating control and status register */
|
||||
#define OTG_HS_PCGCCTL MMIO32(USB_OTG_HS_BASE + OTG_PCGCCTL)
|
||||
@@ -115,22 +115,22 @@
|
||||
/* Device-mode CSRs*/
|
||||
/* OTG device each endpoint interrupt register (OTG_DEACHINT) */
|
||||
/* Bits 31:18 - Reserved */
|
||||
#define OTG_DEACHHINT_OEP1INT (1 << 17)
|
||||
#define OTG_DEACHHINT_OEP1INT (1 << 17)
|
||||
/* Bits 16:2 - Reserved */
|
||||
#define OTG_DEACHHINT_IEP1INT (1 << 1)
|
||||
#define OTG_DEACHHINT_IEP1INT (1 << 1)
|
||||
/* Bit 0 - Reserved */
|
||||
|
||||
/* OTG device each in endpoint-1 interrupt register (OTG_DIEPEACHMSK1) */
|
||||
/* Bits 31:14 - Reserved */
|
||||
#define OTG_DIEPEACHMSK1_NAKM (1 << 13)
|
||||
#define OTG_DIEPEACHMSK1_NAKM (1 << 13)
|
||||
/* Bits 12:10 - Reserved */
|
||||
#define OTG_DIEPEACHMSK1_BIM (1 << 9)
|
||||
#define OTG_DIEPEACHMSK1_BIM (1 << 9)
|
||||
#define OTG_DIEPEACHMSK1_TXFURM (1 << 8)
|
||||
/* Bit 7 - Reserved */
|
||||
#define OTG_DIEPEACHMSK1_INEPNEM (1 << 6)
|
||||
#define OTG_DIEPEACHMSK1_INEPNMM (1 << 5)
|
||||
#define OTG_DIEPEACHMSK1_INEPNEM (1 << 6)
|
||||
#define OTG_DIEPEACHMSK1_INEPNMM (1 << 5)
|
||||
#define OTG_DIEPEACHMSK1_ITTXFEMSK (1 << 4)
|
||||
#define OTG_DIEPEACHMSK1_TOM (1 << 3)
|
||||
#define OTG_DIEPEACHMSK1_TOM (1 << 3)
|
||||
/* Bit 2 - Reserved */
|
||||
#define OTG_DIEPEACHMSK1_EPDM (1 << 1)
|
||||
#define OTG_DIEPEACHMSK1_XFRCM (1 << 0)
|
||||
@@ -141,10 +141,10 @@
|
||||
#define OTG_DOEPEACHMSK1_NAKM (1 << 13)
|
||||
#define OTG_DOEPEACHMSK1_BERRM (1 << 12)
|
||||
/* Bits 11:10 - Reserved */
|
||||
#define OTG_DOEPEACHMSK1_BIM (1 << 9)
|
||||
#define OTG_DOEPEACHMSK1_BIM (1 << 9)
|
||||
#define OTG_DOEPEACHMSK1_OPEM (1 << 8)
|
||||
/* Bits 7:3 - Reserved */
|
||||
#define OTG_DOEPEACHMSK1_AHBERRM (1 << 2)
|
||||
#define OTG_DOEPEACHMSK1_AHBERRM (1 << 2)
|
||||
#define OTG_DOEPEACHMSK1_EPDM (1 << 1)
|
||||
#define OTG_DOEPEACHMSK1_XFRCM (1 << 0)
|
||||
|
||||
@@ -153,11 +153,11 @@
|
||||
#define OTG_HCSPLT_SPLITEN (1 << 31)
|
||||
/* Bits 30:17 - Reserved */
|
||||
#define OTG_HCSPLT_COMPLSPLT (1 << 16)
|
||||
#define OTG_HCSPLT_XACTPOS_ALL (0x3 << 14)
|
||||
#define OTG_HCSPLT_XACTPOS_ALL (0x3 << 14)
|
||||
#define OTG_HCSPLT_XACTPOS_BEGIN (0x2 << 14)
|
||||
#define OTG_HCSPLT_XACTPOS_MID (0x0 << 14)
|
||||
#define OTG_HCSPLT_XACTPOS_END (0x1 << 14)
|
||||
#define OTG_HCSPLT_HUBADDR_MASK (0x7f << 7)
|
||||
#define OTG_HCSPLT_XACTPOS_MID (0x0 << 14)
|
||||
#define OTG_HCSPLT_XACTPOS_END (0x1 << 14)
|
||||
#define OTG_HCSPLT_HUBADDR_MASK (0x7f << 7)
|
||||
#define OTG_HCSPLT_PORTADDR_MASK (0x7f << 0)
|
||||
|
||||
#endif
|
||||
|
||||
@@ -35,7 +35,7 @@
|
||||
|
||||
/* Clear register bit masking out some bits that must not be touched. */
|
||||
#define CLR_REG_BIT_MSK_AND_SET(REG, MSK, BIT, EXTRA_BITS) \
|
||||
SET_REG((REG), (GET_REG((REG)) & (MSK) & (~(BIT))) | (EXTRA_BITS))
|
||||
SET_REG((REG), (GET_REG((REG)) & (MSK) & (~(BIT))) | (EXTRA_BITS))
|
||||
|
||||
#define CLR_REG_BIT_MSK(REG, MSK, BIT) \
|
||||
CLR_REG_BIT_MSK_AND_SET((REG), (MSK), (BIT), 0)
|
||||
|
||||
@@ -144,9 +144,9 @@ struct usb_midi_element_descriptor_tail {
|
||||
uint8_t bInTerminalLink;
|
||||
uint8_t bOutTerminalLink;
|
||||
uint8_t bElCapsSize;
|
||||
uint16_t bmElementCaps; /* host cannot assume this is 16-bit but
|
||||
device can (since highest defined bitmap
|
||||
value in v1.0 is bit 11) */
|
||||
uint16_t bmElementCaps; /* host cannot assume this is 16-bit but device
|
||||
can (since highest defined bitmap value in
|
||||
v1.0 is bit 11) */
|
||||
uint8_t iElement;
|
||||
} __attribute__((packed));
|
||||
|
||||
|
||||
@@ -110,17 +110,19 @@ typedef int (*usbd_control_callback)(usbd_device *usbd_dev,
|
||||
struct usb_setup_data *req, uint8_t **buf, uint16_t *len,
|
||||
usbd_control_complete_callback *complete);
|
||||
|
||||
typedef void (*usbd_set_config_callback)(usbd_device *usbd_dev, uint16_t wValue);
|
||||
typedef void (*usbd_set_config_callback)(usbd_device *usbd_dev,
|
||||
uint16_t wValue);
|
||||
|
||||
typedef void (*usbd_set_altsetting_callback)(usbd_device *usbd_dev,
|
||||
uint16_t wIndex, uint16_t wValue);
|
||||
uint16_t wIndex, uint16_t wValue);
|
||||
|
||||
typedef void (*usbd_endpoint_callback)(usbd_device *usbd_dev, uint8_t ep);
|
||||
|
||||
/* <usb_control.c> */
|
||||
/** Registers a control callback.
|
||||
*
|
||||
* The specified callback will be called if (type == (bmRequestType & type_mask))
|
||||
* The specified callback will be called if (type == (bmRequestType
|
||||
* & type_mask))
|
||||
* @param type Handled request type
|
||||
* @param type_mask Mask to apply before matching request type
|
||||
* @return 0 if successful
|
||||
@@ -137,7 +139,7 @@ extern int usbd_register_set_config_callback(usbd_device *usbd_dev,
|
||||
usbd_set_config_callback callback);
|
||||
/** Registers a "Set Interface" (alternate setting) callback */
|
||||
extern void usbd_register_set_altsetting_callback(usbd_device *usbd_dev,
|
||||
usbd_set_altsetting_callback callback);
|
||||
usbd_set_altsetting_callback callback);
|
||||
|
||||
/* Functions to be provided by the hardware abstraction layer */
|
||||
extern void usbd_poll(usbd_device *usbd_dev);
|
||||
|
||||
Reference in New Issue
Block a user