Moving stm32 f2/f4 flash code into the common area.
This commit is contained in:
Fergus Noble
committed by
Piotr Esden-Tempski
Piotr Esden-Tempski
parent
4d15da995e
commit
b039504494
@@ -33,12 +33,13 @@ CFLAGS = -Os -g \
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# ARFLAGS = rcsv
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ARFLAGS = rcs
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OBJS = gpio.o exti2.o flash.o rcc.o
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OBJS = gpio.o exti2.o rcc.o
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OBJS += crc_common_all.o dac_common_all.o dma_common_f24.o \
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gpio_common_all.o gpio_common_f24.o i2c_common_all.o \
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iwdg_common_all.o rtc_common_bcd.o spi_common_all.o \
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timer_common_all.o timer_common_f24.o usart_common_all.o
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timer_common_all.o timer_common_f24.o usart_common_all.o \
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flash_common_f24.o
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VPATH += ../../usb:../:../../cm3:../common
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@@ -1,257 +0,0 @@
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
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* Copyright (C) 2010 Mark Butler <mbutler@physics.otago.ac.nz>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <libopencm3/stm32/f2/flash.h>
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static inline void flash_set_program_size(u32 psize)
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{
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FLASH_CR &= ~(((1 << 0) | (1 << 1)) << 8);
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FLASH_CR |= psize;
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}
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void flash_dcache_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_DCE;
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}
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void flash_dcache_disable(void)
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{
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FLASH_ACR &= ~FLASH_ACR_DCE;
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}
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void flash_icache_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_ICE;
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}
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void flash_icache_disable(void)
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{
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FLASH_ACR &= ~FLASH_ACR_ICE;
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}
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void flash_prefetch_enable(void)
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{
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FLASH_ACR |= FLASH_ACR_PRFTEN;
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}
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void flash_prefetch_disable(void)
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{
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FLASH_ACR &= ~FLASH_ACR_PRFTEN;
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}
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void flash_dcache_reset(void)
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{
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FLASH_ACR |= FLASH_ACR_DCRST;
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}
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void flash_icache_reset(void)
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{
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FLASH_ACR |= FLASH_ACR_ICRST;
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}
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void flash_set_ws(u32 ws)
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{
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u32 reg32;
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reg32 = FLASH_ACR;
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reg32 &= ~((1 << 0) | (1 << 1) | (1 << 2));
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reg32 |= ws;
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FLASH_ACR = reg32;
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}
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void flash_unlock(void)
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{
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/* Clear the unlock state. */
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FLASH_CR |= FLASH_CR_LOCK;
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/* Authorize the FPEC access. */
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FLASH_KEYR = FLASH_KEYR_KEY1;
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FLASH_KEYR = FLASH_KEYR_KEY2;
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}
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void flash_lock(void)
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{
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FLASH_CR |= FLASH_CR_LOCK;
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}
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void flash_clear_pgserr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGSERR;
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}
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void flash_clear_pgperr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGPERR;
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}
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void flash_clear_pgaerr_flag(void)
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{
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FLASH_SR |= FLASH_SR_PGAERR;
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}
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void flash_clear_eop_flag(void)
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{
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FLASH_SR |= FLASH_SR_EOP;
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}
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void flash_clear_wrperr_flag(void)
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{
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FLASH_SR |= FLASH_SR_WRPERR;
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}
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void flash_clear_bsy_flag(void)
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{
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FLASH_SR &= ~FLASH_SR_BSY;
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}
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void flash_clear_status_flags(void)
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{
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flash_clear_pgserr_flag();
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flash_clear_pgperr_flag();
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flash_clear_pgaerr_flag();
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flash_clear_eop_flag();
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flash_clear_wrperr_flag();
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flash_clear_bsy_flag();
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}
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void flash_unlock_option_bytes(void)
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{
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/* Clear the unlock state. */
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FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
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/* Unlock the option bytes. */
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FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
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FLASH_OPTKEYR = FLASH_OPTKEYR_KEY2;
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}
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void flash_lock_option_bytes(void)
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{
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FLASH_OPTCR |= FLASH_OPTCR_OPTLOCK;
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}
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void flash_wait_for_last_operation(void)
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{
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while ((FLASH_SR & FLASH_SR_BSY) == FLASH_SR_BSY)
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;
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}
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void flash_program_double_word(u32 address, u64 data, u32 program_size)
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{
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/* Ensure that all flash operations are complete. */
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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/* Enable writes to flash. */
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FLASH_CR |= FLASH_CR_PG;
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/* Program the first half of the word. */
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MMIO64(address) = data;
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/* Wait for the write to complete. */
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flash_wait_for_last_operation();
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/* Disable writes to flash. */
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FLASH_CR &= ~FLASH_CR_PG;
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}
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void flash_program_word(u32 address, u32 data, u32 program_size)
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{
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/* Ensure that all flash operations are complete. */
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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/* Enable writes to flash. */
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FLASH_CR |= FLASH_CR_PG;
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/* Program the first half of the word. */
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MMIO32(address) = data;
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/* Wait for the write to complete. */
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flash_wait_for_last_operation();
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/* Disable writes to flash. */
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FLASH_CR &= ~FLASH_CR_PG;
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}
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void flash_program_half_word(u32 address, u16 data, u32 program_size)
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{
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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FLASH_CR |= FLASH_CR_PG;
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MMIO16(address) = data;
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
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}
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void flash_program_byte(u32 address, u8 data, u32 program_size)
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{
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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FLASH_CR |= FLASH_CR_PG;
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MMIO8(address) = data;
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_CR_PG; /* Disable the PG bit. */
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}
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void flash_erase_sector(u32 sector, u32 program_size)
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{
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
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FLASH_CR |= sector;
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FLASH_CR |= FLASH_CR_STRT;
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_CR_SER;
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FLASH_CR &= ~(((1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)) << 3);
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}
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void flash_erase_all_sectors(u32 program_size)
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{
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flash_wait_for_last_operation();
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flash_set_program_size(program_size);
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FLASH_CR |= FLASH_CR_MER; /* Enable mass erase. */
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FLASH_CR |= FLASH_CR_STRT; /* Trigger the erase. */
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flash_wait_for_last_operation();
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FLASH_CR &= ~FLASH_CR_MER; /* Disable mass erase. */
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}
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void flash_program_option_bytes(u32 data)
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{
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flash_wait_for_last_operation();
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if (FLASH_OPTCR & FLASH_OPTCR_OPTLOCK)
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flash_unlock_option_bytes();
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FLASH_OPTCR = data & ~0x3;
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FLASH_OPTCR |= FLASH_OPTCR_OPTSTRT; /* Enable option byte programming. */
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flash_wait_for_last_operation();
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}
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