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started csv files for generation of register field stuff

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This commit is contained in:
Michael Ossmann
2012-09-26 19:24:32 -06:00
committed by Piotr Esden-Tempski
parent a0624ecd21
commit ae9a6ae4af
4 changed files with 471 additions and 0 deletions
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scripts/data/lpc43xx/usb.csv Normal file
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USB0_CAPLENGTH,0,8,CAPLENGTH,Indicates offset to add to the register base address at the beginning of the Operational Register,0x40,r
USB0_CAPLENGTH,8,16,HCIVERSION,BCD encoding of the EHCI revision number supported by this host controller,0x100,r
USB0_HCSPARAMS,0,4,N_PORTS,Number of downstream ports,0x1,r
USB0_HCSPARAMS,4,1,PPC,Port Power Control,0x1,r
USB0_HCSPARAMS,8,4,N_PCC,Number of Ports per Companion Controller,0x0,r
USB0_HCSPARAMS,12,4,N_CC,Number of Companion Controller,0x0,r
USB0_HCSPARAMS,16,1,PI,Port indicators,0x1,r
USB0_HCSPARAMS,20,4,N_PTT,Number of Ports per Transaction Translator,0x0,r
USB0_HCSPARAMS,24,4,N_TT,Number of Transaction Translators,0x0,r
USB0_HCCPARAMS,0,1,ADC,64-bit Addressing Capability,0,r
USB0_HCCPARAMS,1,1,PFL,Programmable Frame List Flag,1,r
USB0_HCCPARAMS,2,1,ASP,Asynchronous Schedule Park Capability,1,r
USB0_HCCPARAMS,4,4,IST,Isochronous Scheduling Threshold,0,r
USB0_HCCPARAMS,8,4,EECP,EHCI Extended Capabilities Pointer,0,r
USB0_DCCPARAMS,0,5,DEN,Device Endpoint Number,0x4,r
USB0_DCCPARAMS,7,1,DC,Device Capable,0x1,r
USB0_DCCPARAMS,8,1,HC,Host Capable,0x1,r
USB0_USBCMD_D,0,1,RS,Run/Stop,0,rw
USB0_USBCMD_D,1,1,RST,Controller reset,0,rw
USB0_USBCMD_D,13,1,SUTW,Setup trip wire,0,rw
USB0_USBCMD_D,14,1,ATDTW,Add dTD trip wire,0,rw
USB0_USBCMD_D,16,8,ITC,Interrupt threshold control,0x8,rw
USB0_USBCMD_H,0,1,RS,Run/Stop,0,rw
USB0_USBCMD_H,1,1,RST,Controller reset,0,rw
USB0_USBCMD_H,2,1,FS0,Bit 0 of the Frame List Size bits,0,
USB0_USBCMD_H,3,1,FS1,Bit 1 of the Frame List Size bits,0,
USB0_USBCMD_H,4,1,PSE,This bit controls whether the host controller skips processing the periodic schedule,0,rw
USB0_USBCMD_H,5,1,ASE,This bit controls whether the host controller skips processing the asynchronous schedule,0,rw
USB0_USBCMD_H,6,1,IAA,This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule,0,rw
USB0_USBCMD_H,8,2,ASP1_0,Asynchronous schedule park mode,0x3,rw
USB0_USBCMD_H,11,1,ASPE,Asynchronous Schedule Park Mode Enable,1,rw
USB0_USBCMD_H,15,1,FS2,Bit 2 of the Frame List Size bits,0,
USB0_USBCMD_H,16,8,ITC,Interrupt threshold control,0x8,rw
USB0_USBSTS_D,0,1,UI,USB interrupt,0,rwc
USB0_USBSTS_D,1,1,UEI,USB error interrupt,0,rwc
USB0_USBSTS_D,2,1,PCI,Port change detect,0,rwc
USB0_USBSTS_D,6,1,URI,USB reset received,0,rwc
USB0_USBSTS_D,7,1,SRI,SOF received,0,rwc
USB0_USBSTS_D,8,1,SLI,DCSuspend,0,rwc
USB0_USBSTS_D,16,1,NAKI,NAK interrupt bit,0,r
USB0_USBSTS_H,0,1,UI,USB interrupt,0,rwc
USB0_USBSTS_H,1,1,UEI,USB error interrupt,0,rwc
USB0_USBSTS_H,2,1,PCI,Port change detect,0,rwc
USB0_USBSTS_H,3,1,FRI,Frame list roll-over,0,rwc
USB0_USBSTS_H,5,1,AAI,Interrupt on async advance,0,rwc
USB0_USBSTS_H,7,1,SRI,SOF received,0,rwc
USB0_USBSTS_H,12,1,HCH,HCHalted,1,r
USB0_USBSTS_H,13,1,RCL,Reclamation,0,r
USB0_USBSTS_H,14,1,PS,Periodic schedule status,0,r
USB0_USBSTS_H,15,1,AS,Asynchronous schedule status,0,
USB0_USBSTS_H,18,1,UAI,USB host asynchronous interrupt (USBHSTASYNCINT),0,rwc
USB0_USBSTS_H,19,1,UPI,USB host periodic interrupt (USBHSTPERINT),0,rwc
USB0_USBINTR_D,0,1,UE,USB interrupt enable,0,rw
USB0_USBINTR_D,1,1,UEE,USB error interrupt enable,0,rw
USB0_USBINTR_D,2,1,PCE,Port change detect enable,0,rw
USB0_USBINTR_D,6,1,URE,USB reset enable,0,rw
USB0_USBINTR_D,7,1,SRE,SOF received enable,0,rw
USB0_USBINTR_D,8,1,SLE,Sleep enable,0,rw
USB0_USBINTR_D,16,1,NAKE,NAK interrupt enable,0,rw
USB0_USBINTR_H,0,1,UE,USB interrupt enable,0,rw
USB0_USBINTR_H,1,1,UEE,USB error interrupt enable,0,rw
USB0_USBINTR_H,2,1,PCE,Port change detect enable,0,rw
USB0_USBINTR_H,3,1,FRE,Frame list rollover enable,0,rw
USB0_USBINTR_H,5,1,AAE,Interrupt on asynchronous advance enable,0,rw
USB0_USBINTR_H,7,1,SRE,SOF received enable,0,
USB0_USBINTR_H,18,1,UAIE,USB host asynchronous interrupt enable,0,rw
USB0_USBINTR_H,19,1,UPIA,USB host periodic interrupt enable,0,rw
USB0_FRINDEX_D,0,3,FRINDEX2_0,Current micro frame number,,r
USB0_FRINDEX_D,3,11,FRINDEX13_3,Current frame number of the last frame transmitted,,r
USB0_FRINDEX_H,0,3,FRINDEX2_0,Current micro frame number,,rw
USB0_FRINDEX_H,3,10,FRINDEX12_3,Frame list current index,,rw
USB0_DEVICEADDR,24,1,USBADRA,Device address advance,0,
USB0_DEVICEADDR,25,7,USBADR,USB device address,0,rw
USB0_PERIODICLISTBASE,12,20,PERBASE31_12,Base Address (Low),,rw
USB0_ENDPOINTLISTADDR,11,21,EPBASE31_11,Endpoint list pointer (low),,rw
USB0_ASYNCLISTADDR,5,27,ASYBASE31_5,Link pointer (Low) LPL,,rw
USB0_TTCTRL,24,7,TTHA,Hub address when FS or LS device are connected directly,,rw
USB0_BURSTSIZE,0,8,RXPBURST,Programmable RX burst length,0x10,rw
USB0_BURSTSIZE,8,8,TXPBURST,Programmable TX burst length,0x10,rw
USB0_TXFILLTUNING,0,8,TXSCHOH,FIFO burst threshold,0x2,rw
USB0_TXFILLTUNING,8,5,TXSCHEATLTH,Scheduler health counter,0x0,rw
USB0_TXFILLTUNING,16,6,TXFIFOTHRES,Scheduler overhead,0x0,rw
USB0_BINTERVAL,0,4,BINT,bInterval value,0x00,rw
USB0_ENDPTNAK,0,6,EPRN,Rx endpoint NAK,0x00,rwc
USB0_ENDPTNAK,16,6,EPTN,Tx endpoint NAK,0x00,rwc
USB0_ENDPTNAKEN,0,6,EPRNE,Rx endpoint NAK enable,0x00,rw
USB0_ENDPTNAKEN,16,6,EPTNE,Tx endpoint NAK,0x00,rw
USB0_PORTSC1_D,0,1,CCS,Current connect status,0,r
USB0_PORTSC1_D,2,1,PE,Port enable,1,r
USB0_PORTSC1_D,3,1,PEC,Port enable/disable change,0,r
USB0_PORTSC1_D,6,1,FPR,Force port resume,0,rw
USB0_PORTSC1_D,7,1,SUSP,Suspend,0,r
USB0_PORTSC1_D,8,1,PR,Port reset,0,r
USB0_PORTSC1_D,9,1,HSP,High-speed status,0,r
USB0_PORTSC1_D,14,2,PIC1_0,Port indicator control,0,rw
USB0_PORTSC1_D,16,4,PTC3_0,Port test control,0,rw
USB0_PORTSC1_D,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw
USB0_PORTSC1_D,24,1,PFSC,Port force full speed connect,0,rw
USB0_PORTSC1_D,26,2,PSPD,Port speed,0,r
USB0_PORTSC1_H,0,1,CCS,Current connect status,0,rwc
USB0_PORTSC1_H,1,1,CSC,Connect status change,0,rwc
USB0_PORTSC1_H,2,1,PE,Port enable,0,rw
USB0_PORTSC1_H,3,1,PEC,Port disable/enable change,0,rwc
USB0_PORTSC1_H,4,1,OCA,Over-current active,0,r
USB0_PORTSC1_H,5,1,OCC,Over-current change,0,rwc
USB0_PORTSC1_H,6,1,FPR,Force port resume,0,rw
USB0_PORTSC1_H,7,1,SUSP,Suspend,0,rw
USB0_PORTSC1_H,8,1,PR,Port reset,0,rw
USB0_PORTSC1_H,9,1,HSP,High-speed status,0,r
USB0_PORTSC1_H,10,2,LS,Line status,0x3,r
USB0_PORTSC1_H,12,1,PP,Port power control,0,rw
USB0_PORTSC1_H,14,2,PIC1_0,Port indicator control,0,rw
USB0_PORTSC1_H,16,4,PTC3_0,Port test control,0,rw
USB0_PORTSC1_H,20,1,WKCN,Wake on connect enable (WKCNNT_E),0,rw
USB0_PORTSC1_H,21,1,WKDC,Wake on disconnect enable (WKDSCNNT_E),0,rw
USB0_PORTSC1_H,22,1,WKOC,Wake on over-current enable (WKOC_E),0,rw
USB0_PORTSC1_H,23,1,PHCD,PHY low power suspend - clock disable (PLPSCD),0,rw
USB0_PORTSC1_H,24,1,PFSC,Port force full speed connect,0,rw
USB0_PORTSC1_H,26,2,PSPD,Port speed,0,r
USB0_OTGSC,0,1,VD,VBUS_Discharge,0,rw
USB0_OTGSC,1,1,VC,VBUS_Charge,0,rw
USB0_OTGSC,2,1,HAAR,Hardware assist auto_reset,0,rw
USB0_OTGSC,3,1,OT,OTG termination,0,rw
USB0_OTGSC,4,1,DP,Data pulsing,0,rw
USB0_OTGSC,5,1,IDPU,ID pull-up,1,rw
USB0_OTGSC,6,1,HADP,Hardware assist data pulse,0,rw
USB0_OTGSC,7,1,HABA,Hardware assist B-disconnect to A-connect,0,rw
USB0_OTGSC,8,1,ID,USB ID,0,r
USB0_OTGSC,9,1,AVV,A-VBUS valid,0,r
USB0_OTGSC,10,1,ASV,A-session valid,0,r
USB0_OTGSC,11,1,BSV,B-session valid,0,r
USB0_OTGSC,12,1,BSE,B-session end,0,r
USB0_OTGSC,13,1,MS1T,1 millisecond timer toggle,0,r
USB0_OTGSC,14,1,DPS,Data bus pulsing status,0,r
USB0_OTGSC,16,1,IDIS,USB ID interrupt status,0,rwc
USB0_OTGSC,17,1,AVVIS,A-VBUS valid interrupt status,0,rwc
USB0_OTGSC,18,1,ASVIS,A-Session valid interrupt status,0,rwc
USB0_OTGSC,19,1,BSVIS,B-Session valid interrupt status,0,rwc
USB0_OTGSC,20,1,BSEIS,B-Session end interrupt status,0,rwc
USB0_OTGSC,21,1,MS1S,1 millisecond timer interrupt status,0,rwc
USB0_OTGSC,22,1,DPIS,Data pulse interrupt status,0,rwc
USB0_OTGSC,24,1,IDIE,USB ID interrupt enable,0,rw
USB0_OTGSC,25,1,AVVIE,A-VBUS valid interrupt enable,0,rw
USB0_OTGSC,26,1,ASVIE,A-session valid interrupt enable,0,rw
USB0_OTGSC,27,1,BSVIE,B-session valid interrupt enable,0,rw
USB0_OTGSC,28,1,BSEIE,B-session end interrupt enable,0,rw
USB0_OTGSC,29,1,MS1E,1 millisecond timer interrupt enable,0,rw
USB0_OTGSC,30,1,DPIE,Data pulse interrupt enable,0,rw
USB0_USBMODE_D,0,2,CM1_0,Controller mode,0,rwo
USB0_USBMODE_D,2,1,ES,Endian select,0,rw
USB0_USBMODE_D,3,1,SLOM,Setup Lockout mode,0,rw
USB0_USBMODE_D,4,1,SDIS,Setup Lockout mode,0,rw
USB0_USBMODE_H,0,2,CM,Controller mode,0,rwo
USB0_USBMODE_H,2,1,ES,Endian select,0,rw
USB0_USBMODE_H,4,1,SDIS,Stream disable mode,0,rw
USB0_USBMODE_H,5,1,VBPS,VBUS power select,0,rwo
USB0_ENDPTSETUPSTAT,0,6,ENDPSETUPSTAT,Setup endpoint status for logical endpoints 0 to 5,0,rwc
USB0_ENDPTPRIME,0,6,PERB,Prime endpoint receive buffer for physical OUT endpoints 5 to 0,0,rws
USB0_ENDPTPRIME,16,6,PETB,Prime endpoint transmit buffer for physical IN endpoints 5 to 0,0,rws
USB0_ENDPTFLUSH,0,6,FERB,Flush endpoint receive buffer for physical OUT endpoints 5 to 0,0,rwc
USB0_ENDPTFLUSH,16,6,FETB,Flush endpoint transmit buffer for physical IN endpoints 5 to 0,0,rwc
USB0_ENDPTSTAT,0,6,ERBR,Endpoint receive buffer ready for physical OUT endpoints 5 to 0,0,r
USB0_ENDPTSTAT,16,6,ETBR,Endpoint transmit buffer ready for physical IN endpoints 3 to 0,0,r
USB0_ENDPTCOMPLETE,0,6,ERCE,Endpoint receive complete event for physical OUT endpoints 5 to 0,0,rwc
USB0_ENDPTCOMPLETE,16,6,ETCE,Endpoint transmit complete event for physical IN endpoints 5 to 0,0,rwc
USB0_ENDPTCTRL0,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL0,2,2,RXT1_0,Endpoint type,0,rw
USB0_ENDPTCTRL0,7,1,RXE,Rx endpoint enable,1,r
USB0_ENDPTCTRL0,16,1,TXS,Tx endpoint stall,,rw
USB0_ENDPTCTRL0,18,2,TXT1_0,Endpoint type,0,r
USB0_ENDPTCTRL0,23,1,TXE,Tx endpoint enable,1,r
USB0_ENDPTCTRL1,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL1,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL1,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL1,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL1,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL1,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL1,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL1,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL1,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL1,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL2,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL2,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL2,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL2,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL2,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL2,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL2,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL2,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL2,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL2,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL3,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL3,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL3,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL3,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL3,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL3,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL3,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL3,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL3,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL3,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL4,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL4,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL4,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL4,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL4,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL4,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL4,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL4,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL4,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL4,23,1,TXE,Tx endpoint enable,0,r
USB0_ENDPTCTRL5,0,1,RXS,Rx endpoint stall,0,rw
USB0_ENDPTCTRL5,2,2,RXT,Endpoint type,0,rw
USB0_ENDPTCTRL5,5,1,RXI,Rx data toggle inhibit,0,rw
USB0_ENDPTCTRL5,6,1,RXR,Rx data toggle reset,0,ws
USB0_ENDPTCTRL5,7,1,RXE,Rx endpoint enable,0,rw
USB0_ENDPTCTRL5,16,1,TXS,Tx endpoint stall,0,rw
USB0_ENDPTCTRL5,18,2,TXT1_0,Tx Endpoint type,0,r
USB0_ENDPTCTRL5,21,1,TXI,Tx data toggle inhibit,0,rw
USB0_ENDPTCTRL5,22,1,TXR,Tx data toggle reset,1,ws
USB0_ENDPTCTRL5,23,1,TXE,Tx endpoint enable,0,r
1 USB0_CAPLENGTH 0 8 CAPLENGTH Indicates offset to add to the register base address at the beginning of the Operational Register 0x40 r
2 USB0_CAPLENGTH 8 16 HCIVERSION BCD encoding of the EHCI revision number supported by this host controller 0x100 r
3 USB0_HCSPARAMS 0 4 N_PORTS Number of downstream ports 0x1 r
4 USB0_HCSPARAMS 4 1 PPC Port Power Control 0x1 r
5 USB0_HCSPARAMS 8 4 N_PCC Number of Ports per Companion Controller 0x0 r
6 USB0_HCSPARAMS 12 4 N_CC Number of Companion Controller 0x0 r
7 USB0_HCSPARAMS 16 1 PI Port indicators 0x1 r
8 USB0_HCSPARAMS 20 4 N_PTT Number of Ports per Transaction Translator 0x0 r
9 USB0_HCSPARAMS 24 4 N_TT Number of Transaction Translators 0x0 r
10 USB0_HCCPARAMS 0 1 ADC 64-bit Addressing Capability 0 r
11 USB0_HCCPARAMS 1 1 PFL Programmable Frame List Flag 1 r
12 USB0_HCCPARAMS 2 1 ASP Asynchronous Schedule Park Capability 1 r
13 USB0_HCCPARAMS 4 4 IST Isochronous Scheduling Threshold 0 r
14 USB0_HCCPARAMS 8 4 EECP EHCI Extended Capabilities Pointer 0 r
15 USB0_DCCPARAMS 0 5 DEN Device Endpoint Number 0x4 r
16 USB0_DCCPARAMS 7 1 DC Device Capable 0x1 r
17 USB0_DCCPARAMS 8 1 HC Host Capable 0x1 r
18 USB0_USBCMD_D 0 1 RS Run/Stop 0 rw
19 USB0_USBCMD_D 1 1 RST Controller reset 0 rw
20 USB0_USBCMD_D 13 1 SUTW Setup trip wire 0 rw
21 USB0_USBCMD_D 14 1 ATDTW Add dTD trip wire 0 rw
22 USB0_USBCMD_D 16 8 ITC Interrupt threshold control 0x8 rw
23 USB0_USBCMD_H 0 1 RS Run/Stop 0 rw
24 USB0_USBCMD_H 1 1 RST Controller reset 0 rw
25 USB0_USBCMD_H 2 1 FS0 Bit 0 of the Frame List Size bits 0
26 USB0_USBCMD_H 3 1 FS1 Bit 1 of the Frame List Size bits 0
27 USB0_USBCMD_H 4 1 PSE This bit controls whether the host controller skips processing the periodic schedule 0 rw
28 USB0_USBCMD_H 5 1 ASE This bit controls whether the host controller skips processing the asynchronous schedule 0 rw
29 USB0_USBCMD_H 6 1 IAA This bit is used as a doorbell by software to tell the host controller to issue an interrupt the next time it advances asynchronous schedule 0 rw
30 USB0_USBCMD_H 8 2 ASP1_0 Asynchronous schedule park mode 0x3 rw
31 USB0_USBCMD_H 11 1 ASPE Asynchronous Schedule Park Mode Enable 1 rw
32 USB0_USBCMD_H 15 1 FS2 Bit 2 of the Frame List Size bits 0
33 USB0_USBCMD_H 16 8 ITC Interrupt threshold control 0x8 rw
34 USB0_USBSTS_D 0 1 UI USB interrupt 0 rwc
35 USB0_USBSTS_D 1 1 UEI USB error interrupt 0 rwc
36 USB0_USBSTS_D 2 1 PCI Port change detect 0 rwc
37 USB0_USBSTS_D 6 1 URI USB reset received 0 rwc
38 USB0_USBSTS_D 7 1 SRI SOF received 0 rwc
39 USB0_USBSTS_D 8 1 SLI DCSuspend 0 rwc
40 USB0_USBSTS_D 16 1 NAKI NAK interrupt bit 0 r
41 USB0_USBSTS_H 0 1 UI USB interrupt 0 rwc
42 USB0_USBSTS_H 1 1 UEI USB error interrupt 0 rwc
43 USB0_USBSTS_H 2 1 PCI Port change detect 0 rwc
44 USB0_USBSTS_H 3 1 FRI Frame list roll-over 0 rwc
45 USB0_USBSTS_H 5 1 AAI Interrupt on async advance 0 rwc
46 USB0_USBSTS_H 7 1 SRI SOF received 0 rwc
47 USB0_USBSTS_H 12 1 HCH HCHalted 1 r
48 USB0_USBSTS_H 13 1 RCL Reclamation 0 r
49 USB0_USBSTS_H 14 1 PS Periodic schedule status 0 r
50 USB0_USBSTS_H 15 1 AS Asynchronous schedule status 0
51 USB0_USBSTS_H 18 1 UAI USB host asynchronous interrupt (USBHSTASYNCINT) 0 rwc
52 USB0_USBSTS_H 19 1 UPI USB host periodic interrupt (USBHSTPERINT) 0 rwc
53 USB0_USBINTR_D 0 1 UE USB interrupt enable 0 rw
54 USB0_USBINTR_D 1 1 UEE USB error interrupt enable 0 rw
55 USB0_USBINTR_D 2 1 PCE Port change detect enable 0 rw
56 USB0_USBINTR_D 6 1 URE USB reset enable 0 rw
57 USB0_USBINTR_D 7 1 SRE SOF received enable 0 rw
58 USB0_USBINTR_D 8 1 SLE Sleep enable 0 rw
59 USB0_USBINTR_D 16 1 NAKE NAK interrupt enable 0 rw
60 USB0_USBINTR_H 0 1 UE USB interrupt enable 0 rw
61 USB0_USBINTR_H 1 1 UEE USB error interrupt enable 0 rw
62 USB0_USBINTR_H 2 1 PCE Port change detect enable 0 rw
63 USB0_USBINTR_H 3 1 FRE Frame list rollover enable 0 rw
64 USB0_USBINTR_H 5 1 AAE Interrupt on asynchronous advance enable 0 rw
65 USB0_USBINTR_H 7 1 SRE SOF received enable 0
66 USB0_USBINTR_H 18 1 UAIE USB host asynchronous interrupt enable 0 rw
67 USB0_USBINTR_H 19 1 UPIA USB host periodic interrupt enable 0 rw
68 USB0_FRINDEX_D 0 3 FRINDEX2_0 Current micro frame number r
69 USB0_FRINDEX_D 3 11 FRINDEX13_3 Current frame number of the last frame transmitted r
70 USB0_FRINDEX_H 0 3 FRINDEX2_0 Current micro frame number rw
71 USB0_FRINDEX_H 3 10 FRINDEX12_3 Frame list current index rw
72 USB0_DEVICEADDR 24 1 USBADRA Device address advance 0
73 USB0_DEVICEADDR 25 7 USBADR USB device address 0 rw
74 USB0_PERIODICLISTBASE 12 20 PERBASE31_12 Base Address (Low) rw
75 USB0_ENDPOINTLISTADDR 11 21 EPBASE31_11 Endpoint list pointer (low) rw
76 USB0_ASYNCLISTADDR 5 27 ASYBASE31_5 Link pointer (Low) LPL rw
77 USB0_TTCTRL 24 7 TTHA Hub address when FS or LS device are connected directly rw
78 USB0_BURSTSIZE 0 8 RXPBURST Programmable RX burst length 0x10 rw
79 USB0_BURSTSIZE 8 8 TXPBURST Programmable TX burst length 0x10 rw
80 USB0_TXFILLTUNING 0 8 TXSCHOH FIFO burst threshold 0x2 rw
81 USB0_TXFILLTUNING 8 5 TXSCHEATLTH Scheduler health counter 0x0 rw
82 USB0_TXFILLTUNING 16 6 TXFIFOTHRES Scheduler overhead 0x0 rw
83 USB0_BINTERVAL 0 4 BINT bInterval value 0x00 rw
84 USB0_ENDPTNAK 0 6 EPRN Rx endpoint NAK 0x00 rwc
85 USB0_ENDPTNAK 16 6 EPTN Tx endpoint NAK 0x00 rwc
86 USB0_ENDPTNAKEN 0 6 EPRNE Rx endpoint NAK enable 0x00 rw
87 USB0_ENDPTNAKEN 16 6 EPTNE Tx endpoint NAK 0x00 rw
88 USB0_PORTSC1_D 0 1 CCS Current connect status 0 r
89 USB0_PORTSC1_D 2 1 PE Port enable 1 r
90 USB0_PORTSC1_D 3 1 PEC Port enable/disable change 0 r
91 USB0_PORTSC1_D 6 1 FPR Force port resume 0 rw
92 USB0_PORTSC1_D 7 1 SUSP Suspend 0 r
93 USB0_PORTSC1_D 8 1 PR Port reset 0 r
94 USB0_PORTSC1_D 9 1 HSP High-speed status 0 r
95 USB0_PORTSC1_D 14 2 PIC1_0 Port indicator control 0 rw
96 USB0_PORTSC1_D 16 4 PTC3_0 Port test control 0 rw
97 USB0_PORTSC1_D 23 1 PHCD PHY low power suspend - clock disable (PLPSCD) 0 rw
98 USB0_PORTSC1_D 24 1 PFSC Port force full speed connect 0 rw
99 USB0_PORTSC1_D 26 2 PSPD Port speed 0 r
100 USB0_PORTSC1_H 0 1 CCS Current connect status 0 rwc
101 USB0_PORTSC1_H 1 1 CSC Connect status change 0 rwc
102 USB0_PORTSC1_H 2 1 PE Port enable 0 rw
103 USB0_PORTSC1_H 3 1 PEC Port disable/enable change 0 rwc
104 USB0_PORTSC1_H 4 1 OCA Over-current active 0 r
105 USB0_PORTSC1_H 5 1 OCC Over-current change 0 rwc
106 USB0_PORTSC1_H 6 1 FPR Force port resume 0 rw
107 USB0_PORTSC1_H 7 1 SUSP Suspend 0 rw
108 USB0_PORTSC1_H 8 1 PR Port reset 0 rw
109 USB0_PORTSC1_H 9 1 HSP High-speed status 0 r
110 USB0_PORTSC1_H 10 2 LS Line status 0x3 r
111 USB0_PORTSC1_H 12 1 PP Port power control 0 rw
112 USB0_PORTSC1_H 14 2 PIC1_0 Port indicator control 0 rw
113 USB0_PORTSC1_H 16 4 PTC3_0 Port test control 0 rw
114 USB0_PORTSC1_H 20 1 WKCN Wake on connect enable (WKCNNT_E) 0 rw
115 USB0_PORTSC1_H 21 1 WKDC Wake on disconnect enable (WKDSCNNT_E) 0 rw
116 USB0_PORTSC1_H 22 1 WKOC Wake on over-current enable (WKOC_E) 0 rw
117 USB0_PORTSC1_H 23 1 PHCD PHY low power suspend - clock disable (PLPSCD) 0 rw
118 USB0_PORTSC1_H 24 1 PFSC Port force full speed connect 0 rw
119 USB0_PORTSC1_H 26 2 PSPD Port speed 0 r
120 USB0_OTGSC 0 1 VD VBUS_Discharge 0 rw
121 USB0_OTGSC 1 1 VC VBUS_Charge 0 rw
122 USB0_OTGSC 2 1 HAAR Hardware assist auto_reset 0 rw
123 USB0_OTGSC 3 1 OT OTG termination 0 rw
124 USB0_OTGSC 4 1 DP Data pulsing 0 rw
125 USB0_OTGSC 5 1 IDPU ID pull-up 1 rw
126 USB0_OTGSC 6 1 HADP Hardware assist data pulse 0 rw
127 USB0_OTGSC 7 1 HABA Hardware assist B-disconnect to A-connect 0 rw
128 USB0_OTGSC 8 1 ID USB ID 0 r
129 USB0_OTGSC 9 1 AVV A-VBUS valid 0 r
130 USB0_OTGSC 10 1 ASV A-session valid 0 r
131 USB0_OTGSC 11 1 BSV B-session valid 0 r
132 USB0_OTGSC 12 1 BSE B-session end 0 r
133 USB0_OTGSC 13 1 MS1T 1 millisecond timer toggle 0 r
134 USB0_OTGSC 14 1 DPS Data bus pulsing status 0 r
135 USB0_OTGSC 16 1 IDIS USB ID interrupt status 0 rwc
136 USB0_OTGSC 17 1 AVVIS A-VBUS valid interrupt status 0 rwc
137 USB0_OTGSC 18 1 ASVIS A-Session valid interrupt status 0 rwc
138 USB0_OTGSC 19 1 BSVIS B-Session valid interrupt status 0 rwc
139 USB0_OTGSC 20 1 BSEIS B-Session end interrupt status 0 rwc
140 USB0_OTGSC 21 1 MS1S 1 millisecond timer interrupt status 0 rwc
141 USB0_OTGSC 22 1 DPIS Data pulse interrupt status 0 rwc
142 USB0_OTGSC 24 1 IDIE USB ID interrupt enable 0 rw
143 USB0_OTGSC 25 1 AVVIE A-VBUS valid interrupt enable 0 rw
144 USB0_OTGSC 26 1 ASVIE A-session valid interrupt enable 0 rw
145 USB0_OTGSC 27 1 BSVIE B-session valid interrupt enable 0 rw
146 USB0_OTGSC 28 1 BSEIE B-session end interrupt enable 0 rw
147 USB0_OTGSC 29 1 MS1E 1 millisecond timer interrupt enable 0 rw
148 USB0_OTGSC 30 1 DPIE Data pulse interrupt enable 0 rw
149 USB0_USBMODE_D 0 2 CM1_0 Controller mode 0 rwo
150 USB0_USBMODE_D 2 1 ES Endian select 0 rw
151 USB0_USBMODE_D 3 1 SLOM Setup Lockout mode 0 rw
152 USB0_USBMODE_D 4 1 SDIS Setup Lockout mode 0 rw
153 USB0_USBMODE_H 0 2 CM Controller mode 0 rwo
154 USB0_USBMODE_H 2 1 ES Endian select 0 rw
155 USB0_USBMODE_H 4 1 SDIS Stream disable mode 0 rw
156 USB0_USBMODE_H 5 1 VBPS VBUS power select 0 rwo
157 USB0_ENDPTSETUPSTAT 0 6 ENDPSETUPSTAT Setup endpoint status for logical endpoints 0 to 5 0 rwc
158 USB0_ENDPTPRIME 0 6 PERB Prime endpoint receive buffer for physical OUT endpoints 5 to 0 0 rws
159 USB0_ENDPTPRIME 16 6 PETB Prime endpoint transmit buffer for physical IN endpoints 5 to 0 0 rws
160 USB0_ENDPTFLUSH 0 6 FERB Flush endpoint receive buffer for physical OUT endpoints 5 to 0 0 rwc
161 USB0_ENDPTFLUSH 16 6 FETB Flush endpoint transmit buffer for physical IN endpoints 5 to 0 0 rwc
162 USB0_ENDPTSTAT 0 6 ERBR Endpoint receive buffer ready for physical OUT endpoints 5 to 0 0 r
163 USB0_ENDPTSTAT 16 6 ETBR Endpoint transmit buffer ready for physical IN endpoints 3 to 0 0 r
164 USB0_ENDPTCOMPLETE 0 6 ERCE Endpoint receive complete event for physical OUT endpoints 5 to 0 0 rwc
165 USB0_ENDPTCOMPLETE 16 6 ETCE Endpoint transmit complete event for physical IN endpoints 5 to 0 0 rwc
166 USB0_ENDPTCTRL0 0 1 RXS Rx endpoint stall 0 rw
167 USB0_ENDPTCTRL0 2 2 RXT1_0 Endpoint type 0 rw
168 USB0_ENDPTCTRL0 7 1 RXE Rx endpoint enable 1 r
169 USB0_ENDPTCTRL0 16 1 TXS Tx endpoint stall rw
170 USB0_ENDPTCTRL0 18 2 TXT1_0 Endpoint type 0 r
171 USB0_ENDPTCTRL0 23 1 TXE Tx endpoint enable 1 r
172 USB0_ENDPTCTRL1 0 1 RXS Rx endpoint stall 0 rw
173 USB0_ENDPTCTRL1 2 2 RXT Endpoint type 0 rw
174 USB0_ENDPTCTRL1 5 1 RXI Rx data toggle inhibit 0 rw
175 USB0_ENDPTCTRL1 6 1 RXR Rx data toggle reset 0 ws
176 USB0_ENDPTCTRL1 7 1 RXE Rx endpoint enable 0 rw
177 USB0_ENDPTCTRL1 16 1 TXS Tx endpoint stall 0 rw
178 USB0_ENDPTCTRL1 18 2 TXT1_0 Tx Endpoint type 0 r
179 USB0_ENDPTCTRL1 21 1 TXI Tx data toggle inhibit 0 rw
180 USB0_ENDPTCTRL1 22 1 TXR Tx data toggle reset 1 ws
181 USB0_ENDPTCTRL1 23 1 TXE Tx endpoint enable 0 r
182 USB0_ENDPTCTRL2 0 1 RXS Rx endpoint stall 0 rw
183 USB0_ENDPTCTRL2 2 2 RXT Endpoint type 0 rw
184 USB0_ENDPTCTRL2 5 1 RXI Rx data toggle inhibit 0 rw
185 USB0_ENDPTCTRL2 6 1 RXR Rx data toggle reset 0 ws
186 USB0_ENDPTCTRL2 7 1 RXE Rx endpoint enable 0 rw
187 USB0_ENDPTCTRL2 16 1 TXS Tx endpoint stall 0 rw
188 USB0_ENDPTCTRL2 18 2 TXT1_0 Tx Endpoint type 0 r
189 USB0_ENDPTCTRL2 21 1 TXI Tx data toggle inhibit 0 rw
190 USB0_ENDPTCTRL2 22 1 TXR Tx data toggle reset 1 ws
191 USB0_ENDPTCTRL2 23 1 TXE Tx endpoint enable 0 r
192 USB0_ENDPTCTRL3 0 1 RXS Rx endpoint stall 0 rw
193 USB0_ENDPTCTRL3 2 2 RXT Endpoint type 0 rw
194 USB0_ENDPTCTRL3 5 1 RXI Rx data toggle inhibit 0 rw
195 USB0_ENDPTCTRL3 6 1 RXR Rx data toggle reset 0 ws
196 USB0_ENDPTCTRL3 7 1 RXE Rx endpoint enable 0 rw
197 USB0_ENDPTCTRL3 16 1 TXS Tx endpoint stall 0 rw
198 USB0_ENDPTCTRL3 18 2 TXT1_0 Tx Endpoint type 0 r
199 USB0_ENDPTCTRL3 21 1 TXI Tx data toggle inhibit 0 rw
200 USB0_ENDPTCTRL3 22 1 TXR Tx data toggle reset 1 ws
201 USB0_ENDPTCTRL3 23 1 TXE Tx endpoint enable 0 r
202 USB0_ENDPTCTRL4 0 1 RXS Rx endpoint stall 0 rw
203 USB0_ENDPTCTRL4 2 2 RXT Endpoint type 0 rw
204 USB0_ENDPTCTRL4 5 1 RXI Rx data toggle inhibit 0 rw
205 USB0_ENDPTCTRL4 6 1 RXR Rx data toggle reset 0 ws
206 USB0_ENDPTCTRL4 7 1 RXE Rx endpoint enable 0 rw
207 USB0_ENDPTCTRL4 16 1 TXS Tx endpoint stall 0 rw
208 USB0_ENDPTCTRL4 18 2 TXT1_0 Tx Endpoint type 0 r
209 USB0_ENDPTCTRL4 21 1 TXI Tx data toggle inhibit 0 rw
210 USB0_ENDPTCTRL4 22 1 TXR Tx data toggle reset 1 ws
211 USB0_ENDPTCTRL4 23 1 TXE Tx endpoint enable 0 r
212 USB0_ENDPTCTRL5 0 1 RXS Rx endpoint stall 0 rw
213 USB0_ENDPTCTRL5 2 2 RXT Endpoint type 0 rw
214 USB0_ENDPTCTRL5 5 1 RXI Rx data toggle inhibit 0 rw
215 USB0_ENDPTCTRL5 6 1 RXR Rx data toggle reset 0 ws
216 USB0_ENDPTCTRL5 7 1 RXE Rx endpoint enable 0 rw
217 USB0_ENDPTCTRL5 16 1 TXS Tx endpoint stall 0 rw
218 USB0_ENDPTCTRL5 18 2 TXT1_0 Tx Endpoint type 0 r
219 USB0_ENDPTCTRL5 21 1 TXI Tx data toggle inhibit 0 rw
220 USB0_ENDPTCTRL5 22 1 TXR Tx data toggle reset 1 ws
221 USB0_ENDPTCTRL5 23 1 TXE Tx endpoint enable 0 r