diff --git a/include/libopencm3/stm32/f4/rcc.h b/include/libopencm3/stm32/f4/rcc.h
index e6d660f1..2c6ac630 100644
--- a/include/libopencm3/stm32/f4/rcc.h
+++ b/include/libopencm3/stm32/f4/rcc.h
@@ -770,9 +770,7 @@ extern uint32_t rcc_apb2_frequency;
 /* --- Function prototypes ------------------------------------------------- */
 
 enum rcc_clock_3v3 {
-	RCC_CLOCK_3V3_48MHZ,
 	RCC_CLOCK_3V3_84MHZ,
-	RCC_CLOCK_3V3_120MHZ,
 	RCC_CLOCK_3V3_168MHZ,
 	RCC_CLOCK_3V3_180MHZ,
 	RCC_CLOCK_3V3_END
diff --git a/lib/stm32/f4/rcc.c b/lib/stm32/f4/rcc.c
index 515693e4..d86421ec 100644
--- a/lib/stm32/f4/rcc.c
+++ b/lib/stm32/f4/rcc.c
@@ -50,23 +50,6 @@ uint32_t rcc_apb1_frequency = 16000000;
 uint32_t rcc_apb2_frequency = 16000000;
 
 const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
-	{ /* 48MHz */
-		.pllm = 16,
-		.plln = 96,
-		.pllp = 2,
-		.pllq = 2,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_1WS,
-		.ahb_frequency  = 48000000,
-		.apb1_frequency = 12000000,
-		.apb2_frequency = 24000000,
-	},
 	{ /* 84MHz */
 		.pllm = 16,
 		.plln = 336,
@@ -84,23 +67,6 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-	{ /* 120MHz */
-		.pllm = 16,
-		.plln = 240,
-		.pllp = 2,
-		.pllq = 5,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSI_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_3WS,
-		.ahb_frequency  = 120000000,
-		.apb1_frequency = 30000000,
-		.apb2_frequency = 60000000,
-	},
 	{ /* 168MHz */
 		.pllm = 16,
 		.plln = 336,
@@ -138,23 +104,6 @@ const struct rcc_clock_scale rcc_hsi_configs[RCC_CLOCK_3V3_END] = {
 };
 
 const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
-	{ /* 48MHz */
-		.pllm = 8,
-		.plln = 96,
-		.pllp = 2,
-		.pllq = 2,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_1WS,
-		.ahb_frequency  = 48000000,
-		.apb1_frequency = 12000000,
-		.apb2_frequency = 24000000,
-	},
 	{ /* 84MHz */
 		.pllm = 8,
 		.plln = 336,
@@ -172,23 +121,6 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-	{ /* 120MHz */
-		.pllm = 8,
-		.plln = 240,
-		.pllp = 2,
-		.pllq = 5,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_3WS,
-		.ahb_frequency  = 120000000,
-		.apb1_frequency = 30000000,
-		.apb2_frequency = 60000000,
-	},
 	{ /* 168MHz */
 		.pllm = 8,
 		.plln = 336,
@@ -226,23 +158,6 @@ const struct rcc_clock_scale rcc_hse_8mhz_3v3[RCC_CLOCK_3V3_END] = {
 };
 
 const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
-	{ /* 48MHz */
-		.pllm = 12,
-		.plln = 96,
-		.pllp = 2,
-		.pllq = 2,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_1WS,
-		.ahb_frequency  = 48000000,
-		.apb1_frequency = 12000000,
-		.apb2_frequency = 24000000,
-	},
 	{ /* 84MHz */
 		.pllm = 12,
 		.plln = 336,
@@ -260,23 +175,6 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-	{ /* 120MHz */
-		.pllm = 12,
-		.plln = 240,
-		.pllp = 2,
-		.pllq = 5,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_3WS,
-		.ahb_frequency  = 120000000,
-		.apb1_frequency = 30000000,
-		.apb2_frequency = 60000000,
-	},
 	{ /* 168MHz */
 		.pllm = 12,
 		.plln = 336,
@@ -314,23 +212,6 @@ const struct rcc_clock_scale rcc_hse_12mhz_3v3[RCC_CLOCK_3V3_END] = {
 };
 
 const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
-	{ /* 48MHz */
-		.pllm = 16,
-		.plln = 96,
-		.pllp = 2,
-		.pllq = 2,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_1WS,
-		.ahb_frequency  = 48000000,
-		.apb1_frequency = 12000000,
-		.apb2_frequency = 24000000,
-	},
 	{ /* 84MHz */
 		.pllm = 16,
 		.plln = 336,
@@ -348,23 +229,6 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-	{ /* 120MHz */
-		.pllm = 16,
-		.plln = 240,
-		.pllp = 2,
-		.pllq = 5,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_3WS,
-		.ahb_frequency  = 120000000,
-		.apb1_frequency = 30000000,
-		.apb2_frequency = 60000000,
-	},
 	{ /* 168MHz */
 		.pllm = 16,
 		.plln = 336,
@@ -402,23 +266,6 @@ const struct rcc_clock_scale rcc_hse_16mhz_3v3[RCC_CLOCK_3V3_END] = {
 };
 
 const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
-	{ /* 48MHz */
-		.pllm = 25,
-		.plln = 96,
-		.pllp = 2,
-		.pllq = 2,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_1WS,
-		.ahb_frequency  = 48000000,
-		.apb1_frequency = 12000000,
-		.apb2_frequency = 24000000,
-	},
 	{ /* 84MHz */
 		.pllm = 25,
 		.plln = 336,
@@ -436,23 +283,6 @@ const struct rcc_clock_scale rcc_hse_25mhz_3v3[RCC_CLOCK_3V3_END] = {
 		.apb1_frequency = 42000000,
 		.apb2_frequency = 84000000,
 	},
-	{ /* 120MHz */
-		.pllm = 25,
-		.plln = 240,
-		.pllp = 2,
-		.pllq = 5,
-		.pllr = 0,
-		.pll_source = RCC_CFGR_PLLSRC_HSE_CLK,
-		.hpre = RCC_CFGR_HPRE_DIV_NONE,
-		.ppre1 = RCC_CFGR_PPRE_DIV_4,
-		.ppre2 = RCC_CFGR_PPRE_DIV_2,
-		.voltage_scale = PWR_SCALE1,
-		.flash_config = FLASH_ACR_DCEN | FLASH_ACR_ICEN |
-				FLASH_ACR_LATENCY_3WS,
-		.ahb_frequency  = 120000000,
-		.apb1_frequency = 30000000,
-		.apb2_frequency = 60000000,
-	},
 	{ /* 168MHz */
 		.pllm = 25,
 		.plln = 336,