[stm32] Use correct offsets for UniqueID bits

STM32L1 has a different set of offsets, not just a different base
address, so we can't have common registers definitions.  Also, out of
F0,F1,F2,F3,F4,L1, only the F1 has the odd note about 2x16bit registers
and 2x32bit registers with one 16bit register marked as "This field
value is also reserved for a future feature."  Therefore, replace the
awkward reading out as multiple words and just copy them in.

F0,F2,F3,F4 were missing definitions altogether.

This does _not_ attempt to address the problem of the mismatched base
addresses for Medium+ and High Density L1 parts.

include/libopencm3/stm32/f2/memorymap.h

@@ -130,4 +130,12 @@
 /* PPIB */
 #define DBGMCU_BASE			(PPBI_BASE + 0x00042000)
 
+/* Device Electronic Signature */
+#define DESIG_FLASH_SIZE_BASE		(0x1FFF7A22)
+#define DESIG_UNIQUE_ID_BASE		(0x1FFF7A10)
+#define DESIG_UNIQUE_ID0		MMIO32(DESIG_UNIQUE_ID_BASE)
+#define DESIG_UNIQUE_ID1		MMIO32(DESIG_UNIQUE_ID_BASE + 4)
+#define DESIG_UNIQUE_ID2		MMIO32(DESIG_UNIQUE_ID_BASE + 8)
+
+
 #endif