EMTime/libopencm3
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[Style] Global style fix run.

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This commit is contained in:
Piotr Esden-Tempski
2014-01-03 01:07:30 +01:00
parent 67efedec54
commit a909b5ca9e
25 changed files with 920 additions and 915 deletions
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2
lib/stm32/common/exti_common_all.c
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@@ -110,7 +110,7 @@ void exti_select_source(uint32_t exti, uint32_t gpioport)
case GPIOD:
bits = 3;
break;
#if defined(GPIOE) && defined(GPIO_PORT_E_BASE)
#if defined(GPIOE) && defined(GPIO_PORT_E_BASE)
case GPIOE:
bits = 4;
break;

23
lib/stm32/common/rcc_common_all.c
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@@ -17,15 +17,15 @@
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#include <libopencm3/stm32/rcc.h>
/*---------------------------------------------------------------------------*/
/** @brief RCC Enable Peripheral Clocks.
*
* Enable the clock on particular peripherals. There are three registers
* involved, each one controlling the enabling of clocks associated with the
* AHB, APB1 and APB2 respectively. Several peripherals could be enabled
* Enable the clock on particular peripherals. There are three registers
* involved, each one controlling the enabling of clocks associated with the
* AHB, APB1 and APB2 respectively. Several peripherals could be enabled
* simultaneously <em>only if they are controlled by the same register</em>.
*
* @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
@@ -45,9 +45,9 @@ void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en)
/*---------------------------------------------------------------------------*/
/** @brief RCC Disable Peripheral Clocks.
*
* Enable the clock on particular peripherals. There are three registers
* involved, each one controlling the enabling of clocks associated with
* the AHB, APB1 and APB2 respectively. Several peripherals could be disabled
* Enable the clock on particular peripherals. There are three registers
* involved, each one controlling the enabling of clocks associated with
* the AHB, APB1 and APB2 respectively. Several peripherals could be disabled
* simultaneously <em>only if they are controlled by the same register</em>.
*
* @param[in] *reg Unsigned int32. Pointer to a Clock Enable Register
@@ -70,7 +70,7 @@ void rcc_peripheral_disable_clock(volatile uint32_t *reg, uint32_t en)
* controlling reset of peripherals associated with the AHB, APB1 and APB2
* respectively. Several peripherals could be reset simultaneously <em>only if
* they are controlled by the same register</em>.
*
*
* @param[in] *reg Unsigned int32. Pointer to a Reset Register
* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
* @param[in] reset Unsigned int32. Logical OR of all resets.
@@ -93,7 +93,8 @@ void rcc_peripheral_reset(volatile uint32_t *reg, uint32_t reset)
*
* @param[in] *reg Unsigned int32. Pointer to a Reset Register
* (either RCC_AHBENR, RCC_APB1ENR or RCC_APB2ENR)
* @param[in] clear_reset Unsigned int32. Logical OR of all resets to be removed:
* @param[in] clear_reset Unsigned int32. Logical OR of all resets to be
* removed:
* @li If register is RCC_AHBRSTR, from @ref rcc_ahbrstr_rst
* @li If register is RCC_APB1RSTR, from @ref rcc_apb1rstr_rst
* @li If register is RCC_APB2RSTR, from @ref rcc_apb2rstr_rst
@@ -115,7 +116,7 @@ void rcc_peripheral_clear_reset(volatile uint32_t *reg, uint32_t clear_reset)
*
* For available constants, see #periph_t (RCC_UART1 for example)
*/
void rcc_periph_clock_enable(enum rcc_periph_clken clken)
{
_RCC_REG(clken) |= _RCC_BIT(clken);
@@ -182,4 +183,4 @@ void rcc_periph_reset_release(enum rcc_periph_rst rst)
}
#undef _RCC_REG
#undef _RCC_BIT
#undef _RCC_BIT

2
lib/stm32/f0/adc.c
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@@ -788,7 +788,7 @@ void adc_enable_analog_watchdog_on_all_channels(uint32_t adc)
void adc_enable_analog_watchdog_on_selected_channel(uint32_t adc, uint8_t chan)
{
ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) | \
ADC_CFGR1(adc) = (ADC_CFGR1(adc) & ~ADC_CFGR1_AWDCH) |
ADC_CFGR1_AWDCH_VAL(chan);
ADC_CFGR1(adc) |= ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL;

2
lib/stm32/f0/rcc.c
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@@ -250,7 +250,7 @@ void rcc_osc_on(enum rcc_osc osc)
RCC_CSR |= RCC_CSR_LSION;
break;
case PLL:
RCC_CR|=RCC_CR_PLLON;
RCC_CR |= RCC_CR_PLLON;
break;
}
}