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[Style] Global style fix run.

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This commit is contained in:
Piotr Esden-Tempski
2014-01-03 01:07:30 +01:00
parent 67efedec54
commit a909b5ca9e
25 changed files with 920 additions and 915 deletions
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559
include/libopencm3/cm3/cortex.h
View File

@@ -1,277 +1,282 @@
/** @defgroup CM3_cortex_defines Cortex Core Defines
*
* @brief <b>libopencm3 Defined Constants and Types for the Cortex Core </b>
*
* @ingroup CM3_defines
*
* @version 1.0.0
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Ben Gamari <bgamari@gmail.com>
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CORTEX_H
#define LIBOPENCM3_CORTEX_H
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable interrupts
*
* Disable the interrupt mask and enable interrupts globally
*/
static inline void cm_enable_interrupts(void)
{
__asm__("CPSIE I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable interrupts
*
* Mask all interrupts globally
*/
static inline void cm_disable_interrupts(void)
{
__asm__("CPSID I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable faults
*
* Disable the HardFault mask and enable fault interrupt globally
*/
static inline void cm_enable_faults(void)
{
__asm__("CPSIE F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable faults
*
* Mask the HardFault interrupt globally
*/
static inline void cm_disable_faults(void)
{
__asm__("CPSID F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if interrupts are masked
*
* Checks, if interrupts are masked (disabled).
*
* @returns true, if interrupts are disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_interrupts(void)
{
register uint32_t result;
__asm__ ("MRS %0, PRIMASK" : "=r" (result));
return result;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if Fault interrupt is masked
*
* Checks, if HardFault interrupt is masked (disabled).
*
* @returns bool true, if HardFault interrupt is disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_faults(void)
{
register uint32_t result;
__asm__ ("MRS %0, FAULTMASK" : "=r" (result));
return result;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask interrupts
*
* This function switches the mask of the interrupts. If mask is true, the
* interrupts will be disabled. The result of this function can be used for
* restoring previous state of the mask.
*
* @param[in] mask bool New state of the interrupt mask
* @returns bool old state of the interrupt mask
*/
__attribute__((always_inline))
static inline bool cm_mask_interrupts(bool mask)
{
register bool old;
__asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old));
__asm__ __volatile__("" : : : "memory");
__asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
return old;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask HardFault interrupt
*
* This function switches the mask of the HardFault interrupt. If mask is true,
* the HardFault interrupt will be disabled. The result of this function can be
* used for restoring previous state of the mask.
*
* @param[in] mask bool New state of the HardFault interrupt mask
* @returns bool old state of the HardFault interrupt mask
*/
__attribute__((always_inline))
static inline bool cm_mask_faults(bool mask)
{
register bool old;
__asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old));
__asm__ __volatile__ ("" : : : "memory");
__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
return old;
}
/**@}*/
/*===========================================================================*/
/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
*
* @brief Atomic operation support
*
* @ingroup CM3_cortex_defines
*/
/**@{*/
#if !defined(__DOXYGEN__)
/* Do not populate this definition outside */
static inline bool __cm_atomic_set(bool* val)
{
return cm_mask_interrupts(*val);
}
#define __CM_SAVER(state) __val = state, \
__save __attribute__((__cleanup__(__cm_atomic_set))) = \
__cm_atomic_set(&__val)
#endif /* !defined(__DOXYGEN) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare block
*
* This macro disables interrupts for the next command or block of code. The
* interrupt mask is automatically restored after exit of the boundary of the
* code block. Therefore restore of interrupt is done automatically after call
* of return or goto control sentence jumping outside of the block.
*
* @warning The usage of sentences break or continue is prohibited in the block
* due to implementation of this macro!
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* @example 1: Basic usage of atomic block
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // access value as atomic
* } // interrupts is restored automatically
* @endcode
*
* @example 2: Use of return inside block:
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t allocval(void)
* {
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_BLOCK()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_BLOCK() \
for (bool ___CM_SAVER(true), __my = true; __my; __my = false)
#endif /* defined(__DOXYGEN__) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare context
*
* This macro disables interrupts in the current block of code from the place
* where it is defined to the end of the block. The interrupt mask is
* automatically restored after exit of the boundary of the code block.
* Therefore restore of interrupt is done automatically after call of return,
* continue, break, or goto control sentence jumping outside of the block.
*
* @note This function is intended for use in for- cycles to enable the use of
* break and contine sentences inside the block, and for securing the atomic
* reader-like functions.
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* @example 1: Basic usage of atomic context
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* for (int i=0;i < 100; i++) {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value += 100; // access value as atomic
* if ((value % 16) == 0) {
* break; // restore interrupts and break cycle
* }
* } // interrupts is restored automatically
* @endcode
*
* @example 2: Usage of atomic context inside atomic reader fcn.
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t getnextval(void)
* {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value = value + 3; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_CONTEXT()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true)
#endif /* defined(__DOXYGEN__) */
/**@}*/
#endif
/** @defgroup CM3_cortex_defines Cortex Core Defines
*
* @brief <b>libopencm3 Defined Constants and Types for the Cortex Core </b>
*
* @ingroup CM3_defines
*
* @version 1.0.0
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Ben Gamari <bgamari@gmail.com>
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
#ifndef LIBOPENCM3_CORTEX_H
#define LIBOPENCM3_CORTEX_H
/**@{*/
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable interrupts
*
* Disable the interrupt mask and enable interrupts globally
*/
static inline void cm_enable_interrupts(void)
{
__asm__("CPSIE I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable interrupts
*
* Mask all interrupts globally
*/
static inline void cm_disable_interrupts(void)
{
__asm__("CPSID I\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Enable faults
*
* Disable the HardFault mask and enable fault interrupt globally
*/
static inline void cm_enable_faults(void)
{
__asm__("CPSIE F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Disable faults
*
* Mask the HardFault interrupt globally
*/
static inline void cm_disable_faults(void)
{
__asm__("CPSID F\n");
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if interrupts are masked
*
* Checks, if interrupts are masked (disabled).
*
* @returns true, if interrupts are disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_interrupts(void)
{
register uint32_t result;
__asm__ ("MRS %0, PRIMASK" : "=r" (result));
return result;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Check if Fault interrupt is masked
*
* Checks, if HardFault interrupt is masked (disabled).
*
* @returns bool true, if HardFault interrupt is disabled.
*/
__attribute__((always_inline))
static inline bool cm_is_masked_faults(void)
{
register uint32_t result;
__asm__ ("MRS %0, FAULTMASK" : "=r" (result));
return result;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask interrupts
*
* This function switches the mask of the interrupts. If mask is true, the
* interrupts will be disabled. The result of this function can be used for
* restoring previous state of the mask.
*
* @param[in] mask bool New state of the interrupt mask
* @returns bool old state of the interrupt mask
*/
__attribute__((always_inline))
static inline bool cm_mask_interrupts(bool mask)
{
register bool old;
__asm__ __volatile__("MRS %0, PRIMASK" : "=r" (old));
__asm__ __volatile__("" : : : "memory");
__asm__ __volatile__("MSR PRIMASK, %0" : : "r" (mask));
return old;
}
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Mask HardFault interrupt
*
* This function switches the mask of the HardFault interrupt. If mask is true,
* the HardFault interrupt will be disabled. The result of this function can be
* used for restoring previous state of the mask.
*
* @param[in] mask bool New state of the HardFault interrupt mask
* @returns bool old state of the HardFault interrupt mask
*/
__attribute__((always_inline))
static inline bool cm_mask_faults(bool mask)
{
register bool old;
__asm__ __volatile__ ("MRS %0, FAULTMASK" : "=r" (old));
__asm__ __volatile__ ("" : : : "memory");
__asm__ __volatile__ ("MSR FAULTMASK, %0" : : "r" (mask));
return old;
}
/**@}*/
/*===========================================================================*/
/** @defgroup CM3_cortex_atomic_defines Cortex Core Atomic support Defines
*
* @brief Atomic operation support
*
* @ingroup CM3_cortex_defines
*/
/**@{*/
#if !defined(__DOXYGEN__)
/* Do not populate this definition outside */
static inline bool __cm_atomic_set(bool *val)
{
return cm_mask_interrupts(*val);
}
#define __CM_SAVER(state) \
do { \
__val = state, \
__save __attribute__((__cleanup__(__cm_atomic_set))) = \
__cm_atomic_set(&__val); \
} while (0)
#endif /* !defined(__DOXYGEN) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare block
*
* This macro disables interrupts for the next command or block of code. The
* interrupt mask is automatically restored after exit of the boundary of the
* code block. Therefore restore of interrupt is done automatically after call
* of return or goto control sentence jumping outside of the block.
*
* @warning The usage of sentences break or continue is prohibited in the block
* due to implementation of this macro!
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* @example 1: Basic usage of atomic block
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // access value as atomic
* } // interrupts is restored automatically
* @endcode
*
* @example 2: Use of return inside block:
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t allocval(void)
* {
* CM_ATOMIC_BLOCK() { // interrupts are masked in this block
* value = value * 1024 + 651; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_BLOCK()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_BLOCK() \
do { \
for (bool ___CM_SAVER(true), __my = true; __my; __my = false); \
} while (0)
#endif /* defined(__DOXYGEN__) */
/*---------------------------------------------------------------------------*/
/** @brief Cortex M Atomic Declare context
*
* This macro disables interrupts in the current block of code from the place
* where it is defined to the end of the block. The interrupt mask is
* automatically restored after exit of the boundary of the code block.
* Therefore restore of interrupt is done automatically after call of return,
* continue, break, or goto control sentence jumping outside of the block.
*
* @note This function is intended for use in for- cycles to enable the use of
* break and contine sentences inside the block, and for securing the atomic
* reader-like functions.
*
* @note It is safe to use this block inside normal code and in interrupt
* routine.
*
* @example 1: Basic usage of atomic context
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* for (int i=0;i < 100; i++) {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value += 100; // access value as atomic
* if ((value % 16) == 0) {
* break; // restore interrupts and break cycle
* }
* } // interrupts is restored automatically
* @endcode
*
* @example 2: Usage of atomic context inside atomic reader fcn.
*
* @code
* uint64_t value; // This value is used somewhere in interrupt
*
* ...
*
* uint64_t getnextval(void)
* {
* CM_ATOMIC_CONTEXT(); // interrupts are masked in this block
* value = value + 3; // do long atomic operation
* return value; // interrupts is restored automatically
* }
* @endcode
*/
#if defined(__DOXYGEN__)
#define CM_ATOMIC_CONTEXT()
#else /* defined(__DOXYGEN__) */
#define CM_ATOMIC_CONTEXT() bool __CM_SAVER(true)
#endif /* defined(__DOXYGEN__) */
/**@}*/
#endif

2
include/libopencm3/cm3/sync.h
View File

@@ -32,7 +32,7 @@ void __dmb(void);
/* --- Exclusive load and store instructions ------------------------------- */
/* Those are defined only on CM3 or CM4 */
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__)
#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__)
uint32_t __ldrex(volatile uint32_t *addr);
uint32_t __strex(uint32_t val, volatile uint32_t *addr);

92
include/libopencm3/ethernet/mac.h
View File

@@ -1,46 +1,46 @@
/** @defgroup ethernet_mac_defines MAC Generic Defines
*
* @brief <b>Defined Constants and Types for the Ethernet MAC</b>
*
* @ingroup ETH
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#if defined(STM32F1)
# include <libopencm3/ethernet/mac_stm32fxx7.h>
#elif defined(STM32F4)
# include <libopencm3/ethernet/mac_stm32fxx7.h>
#else
# error "stm32 family not defined."
#endif
/**@}*/
/** @defgroup ethernet_mac_defines MAC Generic Defines
*
* @brief <b>Defined Constants and Types for the Ethernet MAC</b>
*
* @ingroup ETH
*
* @version 1.0.0
*
* @author @htmlonly &copy; @endhtmlonly 2013 Frantisek Burian <BuFran@seznam.cz>
*
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
/*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
* it under the terms of the GNU Lesser General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
/**@{*/
#if defined(STM32F1)
# include <libopencm3/ethernet/mac_stm32fxx7.h>
#elif defined(STM32F4)
# include <libopencm3/ethernet/mac_stm32fxx7.h>
#else
# error "stm32 family not defined."
#endif
/**@}*/

15
include/libopencm3/ethernet/mac_stm32fxx7.h
View File

@@ -1,6 +1,6 @@
/** @defgroup ethernet_mac_stm32fxx7_defines MAC STM32Fxx7 Defines
*
* @brief <b>Defined Constants and Types for the Ethernet MAC for STM32Fxx7
* @brief <b>Defined Constants and Types for the Ethernet MAC for STM32Fxx7
* chips</b>
*
* @ingroup ETH
@@ -12,10 +12,10 @@
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
*/
/*
* This file is part of the libopencm3 project.
*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
@@ -36,8 +36,8 @@
#define LIBOPENCM3_ETHERNET_H
#include <libopencm3/stm32/memorymap.h>
#include <libopencm3/cm3/common.h>
#include <libopencm3/cm3/common.h>
/**@{*/
/* Ethernet MAC registers */
@@ -746,8 +746,7 @@ END_DECLS
* for (;;)
* eth_tx(frame,sizeof(frame));
*/
/**@}*/
#endif

16
include/libopencm3/ethernet/phy.h
View File

@@ -11,10 +11,10 @@
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
*/
/*
* This file is part of the libopencm3 project.
*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
@@ -29,12 +29,12 @@
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
*/
#ifndef LIBOPENCM3_PHY_H
#define LIBOPENCM3_PHY_H
#include <stdbool.h>
#include <stdbool.h>
/**@{*/
/* Registers */
@@ -83,8 +83,8 @@ bool phy_link_isup(void);
enum phy_status phy_link_status(void);
void phy_autoneg_force(enum phy_status mode);
void phy_autoneg_enable(void);
void phy_autoneg_enable(void);
/**@}*/

18
include/libopencm3/ethernet/phy_ksz8051mll.h
View File

@@ -1,6 +1,6 @@
/** @defgroup ethernet_phy_ksz8051mll_defines PHY KSZ8051mll Defines
*
* @brief <b>Defined Constants and Types for the Ethernet PHY KSZ8051mll
* @brief <b>Defined Constants and Types for the Ethernet PHY KSZ8051mll
* chips</b>
*
* @ingroup ETH
@@ -12,10 +12,10 @@
* @date 1 September 2013
*
* LGPL License Terms @ref lgpl_license
*/
*/
/*
* This file is part of the libopencm3 project.
*
* This file is part of the libopencm3 project.
*
* Copyright (C) 2013 Frantisek Burian <BuFran@seznam.cz>
*
* This library is free software: you can redistribute it and/or modify
@@ -30,13 +30,13 @@
*
* You should have received a copy of the GNU Lesser General Public License
* along with this library. If not, see <http://www.gnu.org/licenses/>.
*/
*/
#ifndef LIBOPENCM3_PHY_KSZ8051MLL_H
#define LIBOPENCM3_PHY_KSZ8051MLL_H
#include <libopencm3/ethernet/phy.h>
/**@{*/
/* Registers */
@@ -52,8 +52,8 @@
#define PHY_REG_LINKMD 0x1D
#define PHY_REG_CR1 0x1E
#define PHY_REG_CR2 0x1E
#define PHY_REG_CR2 0x1E
/**@}*/

4
include/libopencm3/lpc43xx/sgpio.h
View File

@@ -483,7 +483,7 @@ LGPL License Terms @ref lgpl_license
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT (3)
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_MASK \
(0x3 << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT)
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x)
#define SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE(x)
((x) << SGPIO_MUX_CFGx_CLK_SOURCE_SLICE_MODE_SHIFT)
/* QUALIFIER_MODE: Select qualifier mode */
@@ -684,7 +684,7 @@ typedef struct {
} sgpio_t;
/* Global access to SGPIO structure */
#define SGPIO ((sgpio_t*)SGPIO_PORT_BASE)
#define SGPIO ((sgpio_t *)SGPIO_PORT_BASE)
/**@}*/

2
include/libopencm3/stm32/common/rcc_common_all.h
View File

@@ -29,7 +29,7 @@
#ifndef LIBOPENCM3_RCC_COMMON_ALL_H
#define LIBOPENCM3_RCC_COMMON_ALL_H
BEGIN_DECLS
void rcc_peripheral_enable_clock(volatile uint32_t *reg, uint32_t en);

2
include/libopencm3/stm32/f1/adc.h
View File

@@ -622,7 +622,7 @@ injected channels.
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */

6
include/libopencm3/stm32/f1/rcc.h
View File

@@ -519,7 +519,7 @@ enum rcc_periph_clken {
RCC_ETHMAC = _REG_BIT(0x14, 14),/*--C*/
RCC_ETHMACTX = _REG_BIT(0x14, 15),/*--C*/
RCC_ETHMACRX = _REG_BIT(0x14, 16),/*--C*/
/* APB2 peripherals */
RCC_AFIO = _REG_BIT(0x18, 0),/*VNC*/
RCC_GPIOA = _REG_BIT(0x18, 2),/*VNC*/
@@ -542,7 +542,7 @@ enum rcc_periph_clken {
RCC_TIM9 = _REG_BIT(0x18, 19),/*-N-*/
RCC_TIM10 = _REG_BIT(0x18, 20),/*-N-*/
RCC_TIM11 = _REG_BIT(0x18, 21),/*-N-*/
/* APB1 peripherals */
RCC_TIM2 = _REG_BIT(0x1C, 0),/*VNC*/
RCC_TIM3 = _REG_BIT(0x1C, 1),/*VNC*/
@@ -600,7 +600,7 @@ enum rcc_periph_rst {
RST_TIM9 = _REG_BIT(0x0c, 19),/*-N-*/
RST_TIM10 = _REG_BIT(0x0c, 20),/*-N-*/
RST_TIM11 = _REG_BIT(0x0c, 21),/*-N-*/
/* APB1 peripherals */
RST_TIM2 = _REG_BIT(0x10, 0),/*VNC*/
RST_TIM3 = _REG_BIT(0x10, 1),/*VNC*/

2
include/libopencm3/stm32/f3/adc.h
View File

@@ -628,7 +628,7 @@
#define ADC_JSQR_JSQ2_LSB 14
#define ADC_JSQR_JSQ1_LSB 8
#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 6 + 8))
#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 6 + 8))
#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
/* Bits 30:26 JSQ4[4:0]: 4th conversion in the injected sequence */

2
include/libopencm3/stm32/f4/adc.h
View File

@@ -587,7 +587,7 @@ injected channels.
#define ADC_JSQR_JSQ2_MSK (0x1f << ADC_JSQR_JSQ2_LSB)
#define ADC_JSQR_JSQ1_MSK (0x1f << ADC_JSQR_JSQ1_LSB)
#define ADC_JSQR_JSQ_VAL(n,val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JSQ_VAL(n, val) ((val) << (((n) - 1) * 5))
#define ADC_JSQR_JL_VAL(val) (((val) - 1) << ADC_JSQR_JL_SHIFT)
/* --- ADC_JDRx, ADC_DR values --------------------------------------------- */

6
include/libopencm3/stm32/f4/rcc.h
View File

@@ -530,7 +530,7 @@ enum rcc_periph_clken {
RCC_TIM12 = _REG_BIT(0x40, 6),
RCC_TIM13 = _REG_BIT(0x40, 7),
RCC_TIM14 = _REG_BIT(0x40, 8),
RCC_WWDG = _REG_BIT(0x40, 11),
RCC_WWDG = _REG_BIT(0x40, 11),
RCC_SPI2 = _REG_BIT(0x40, 14),
RCC_SPI3 = _REG_BIT(0x40, 15),
RCC_USART2 = _REG_BIT(0x40, 17),
@@ -613,7 +613,7 @@ enum rcc_periph_clken {
SCC_TIM12 = _REG_BIT(0x60, 6),
SCC_TIM13 = _REG_BIT(0x60, 7),
SCC_TIM14 = _REG_BIT(0x60, 8),
SCC_WWDG = _REG_BIT(0x60, 11),
SCC_WWDG = _REG_BIT(0x60, 11),
SCC_SPI2 = _REG_BIT(0x60, 14),
SCC_SPI3 = _REG_BIT(0x60, 15),
SCC_USART2 = _REG_BIT(0x60, 17),
@@ -686,7 +686,7 @@ enum rcc_periph_rst {
RST_TIM12 = _REG_BIT(0x20, 6),
RST_TIM13 = _REG_BIT(0x20, 7),
RST_TIM14 = _REG_BIT(0x20, 8),
RST_WWDG = _REG_BIT(0x20, 11),
RST_WWDG = _REG_BIT(0x20, 11),
RST_SPI2 = _REG_BIT(0x20, 14),
RST_SPI3 = _REG_BIT(0x20, 15),
RST_USART2 = _REG_BIT(0x20, 17),

6
include/libopencm3/stm32/l1/rcc.h
View File

@@ -439,7 +439,7 @@ enum rcc_periph_clken {
RCC_DMA2 = _REG_BIT(0x1c, 25),
RCC_AES = _REG_BIT(0x1c, 27),
RCC_FSMC = _REG_BIT(0x1c, 30),
/* APB2 peripherals */
RCC_SYSCFG = _REG_BIT(0x20, 0),
RCC_TIM9 = _REG_BIT(0x20, 2),
@@ -488,7 +488,7 @@ enum rcc_periph_clken {
SCC_DMA2 = _REG_BIT(0x28, 25),
SCC_AES = _REG_BIT(0x28, 27),
SCC_FSMC = _REG_BIT(0x28, 30),
/* APB2 peripherals */
SCC_SYSCFG = _REG_BIT(0x2c, 0),
SCC_TIM9 = _REG_BIT(0x2c, 2),
@@ -538,7 +538,7 @@ enum rcc_periph_rst {
RST_DMA2 = _REG_BIT(0x10, 25),
RST_AES = _REG_BIT(0x10, 27),
RST_FSMC = _REG_BIT(0x10, 30),
/* APB2 peripherals */
RST_SYSCFG = _REG_BIT(0x14, 0),
RST_TIM9 = _REG_BIT(0x14, 2),