diff --git a/include/libopencm3/vf6xx/uart.h b/include/libopencm3/vf6xx/uart.h
new file mode 100644
index 00000000..07caa1d0
--- /dev/null
+++ b/include/libopencm3/vf6xx/uart.h
@@ -0,0 +1,182 @@
+/** @defgroup VF6xx_uart_defines UART Defines
+ *
+ * @brief <b>Defined Constants and Types for the VF6xx UART Module</b>
+ *
+ * @ingroup VF6xx_defines
+ *
+ * @version 1.0.0
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2014
+ * Stefan Agner <stefan@agner.ch>
+ *
+ * @date 01 July 2014
+ *
+ * LGPL License Terms @ref lgpl_license
+ *  */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2014 Stefan Agner <stefan@agner.ch>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef LIBOPENCM3_VF6XX_UART_H
+#define LIBOPENCM3_VF6XX_UART_H
+
+#include <libopencm3/cm3/common.h>
+#include <libopencm3/vf6xx/memorymap.h>
+
+/* --- Convenience macros -------------------------------------------------- */
+
+/****************************************************************************/
+/** @defgroup uart_reg_base UART register base addresses
+@ingroup VF6xx_uart_defines
+
+@{*/
+#define UART0				UART0_BASE
+#define UART1				UART1_BASE
+#define UART2				UART2_BASE
+#define UART3				UART3_BASE
+#define UART4				UART4_BASE
+#define UART5				UART5_BASE
+
+/* --- UART registers ------------------------------------------------------ */
+
+#define UART_BDH(uart_base)		MMIO8(uart_base + 0x00)
+#define UART_BDL(uart_base)		MMIO8(uart_base + 0x01)
+#define UART_C1(uart_base)		MMIO8(uart_base + 0x02)
+#define UART_C2(uart_base)		MMIO8(uart_base + 0x03)
+#define UART_S1(uart_base)		MMIO8(uart_base + 0x04)
+#define UART_S2(uart_base)		MMIO8(uart_base + 0x05)
+#define UART_C3(uart_base)		MMIO8(uart_base + 0x06)
+#define UART_D(uart_base)		MMIO8(uart_base + 0x07)
+#define UART_MA1(uart_base)		MMIO8(uart_base + 0x08)
+#define UART_MA2(uart_base)		MMIO8(uart_base + 0x09)
+#define UART_C4(uart_base)		MMIO8(uart_base + 0x0A)
+#define UART_C5(uart_base)		MMIO8(uart_base + 0x0B)
+#define UART_ED(uart_base)		MMIO8(uart_base + 0x0C)
+#define UART_MODEM(uart_base)		MMIO8(uart_base + 0x0D)
+/* Incomplete */
+
+/* --- CCM values -....----------------------------------------------------- */
+
+/* BDH: Baud Rate Register High */
+#define UART_BDH_LBKDIE				(1 << 7)
+#define UART_BDH_RXEDGIE			(1 << 6)
+#define UART_BDH_SBR_MASK			0x1f
+
+/* BDL: Baud Rate Register Low */
+#define UART_BDL_SBR_MASK			0xff
+
+/* C1: Control register 1 */
+#define UART_C1_LOOPS				(1 << 7)
+#define UART_C1_RSRC				(1 << 5)
+#define UART_C1_M				(1 << 4)
+#define UART_C1_WAKE				(1 << 3)
+#define UART_C1_ILT				(1 << 2)
+#define UART_C1_PE				(1 << 1)
+#define UART_C1_PT				(1 << 0)
+
+/* C2: Control register 2 */
+#define UART_C2_TIE				(1 << 7)
+#define UART_C2_TCIE				(1 << 6)
+#define UART_C2_RIE				(1 << 5)
+#define UART_C2_ILIE				(1 << 4)
+#define UART_C2_TE				(1 << 3)
+#define UART_C2_RE				(1 << 2)
+#define UART_C2_RWU				(1 << 1)
+#define UART_C2_SBK				(1 << 0)
+
+/* S1: Status register 1 */
+#define UART_S1_TDRE				(1 << 7)
+#define UART_S1_TC				(1 << 6)
+#define UART_S1_RDRF				(1 << 5)
+#define UART_S1_IDLE				(1 << 4)
+#define UART_S1_OR				(1 << 3)
+#define UART_S1_NF				(1 << 2)
+#define UART_S1_FE				(1 << 1)
+#define UART_S1_PF				(1 << 0)
+
+/* S2: Status register 2 */
+#define UART_S2_LBKDIF				(1 << 7)
+#define UART_S2_RXEDGIF				(1 << 6)
+#define UART_S2_MSBF				(1 << 5)
+#define UART_S2_RXINV				(1 << 4)
+#define UART_S2_RWUID				(1 << 3)
+#define UART_S2_BRK13				(1 << 2)
+#define UART_S2_LBKDE				(1 << 1)
+#define UART_S2_RAF				(1 << 0)
+
+/* C3: Control register 3 */
+#define UART_C3_R8				(1 << 7)
+#define UART_C3_T8				(1 << 6)
+#define UART_C3_TXDIR				(1 << 5)
+#define UART_C3_TXINV				(1 << 4)
+#define UART_C3_ORIE				(1 << 3)
+#define UART_C3_NEIE				(1 << 2)
+#define UART_C3_FEIE				(1 << 1)
+#define UART_C3_PEIE				(1 << 0)
+
+/* MODEM: Modem configuration register */
+#define UART_MODEM_RXRTSE			(1 << 3)
+#define UART_MODEM_TXRTSPOL			(1 << 2)
+#define UART_MODEM_TXRTSE			(1 << 1)
+#define UART_MODEM_TXCTSE			(1 << 0)
+
+/****************************************************************************/
+/** @defgroup uart_parity UART Parity Selection
+@ingroup VF6xx_uart_defines
+
+@{*/
+#define UART_PARITY_NONE		0x00
+#define UART_PARITY_EVEN		UART_C1_PE
+#define UART_PARITY_ODD			(UART_C1_PE | UART_C1_PT)
+/**@}*/
+#define UART_PARITY_MASK		0x3
+
+/* CR3_CTSE/CR3_RTSE combined values */
+/****************************************************************************/
+/** @defgroup usart_cr3_flowcontrol USART Hardware Flow Control Selection
+@ingroup STM32F_usart_defines
+
+@{*/
+#define UART_FLOWCONTROL_NONE		0x00
+#define UART_FLOWCONTROL_RTS		UART_MODEM_RXRTSE
+#define UART_FLOWCONTROL_CTS		UART_MODEM_TXCTSE
+#define UART_FLOWCONTROL_RTS_CTS	(UART_MODEM_RXRTSE | UART_MODEM_TXCTSE)
+/**@}*/
+#define UART_FLOWCONTROL_MASK		(UART_MODEM_RXRTSE | UART_MODEM_TXCTSE)
+
+/* --- Function prototypes ------------------------------------------------- */
+
+#include <libopencm3/cm3/common.h>
+
+BEGIN_DECLS
+
+void uart_enable(uint32_t uart);
+void uart_disable(uint32_t uart);
+void uart_set_baudrate(uint32_t uart, uint32_t baud);
+void uart_set_parity(uint32_t uart, uint8_t parity);
+void uart_set_flow_control(uint32_t uart, uint8_t flowcontrol);
+void uart_send(uint32_t uart, uint8_t data);
+void uart_send_blocking(uint32_t usart, uint8_t data);
+void uart_wait_send_ready(uint32_t uart);
+uint8_t uart_recv(uint32_t uart);
+uint8_t uart_recv_blocking(uint32_t uart);
+void uart_wait_recv_ready(uint32_t uart);
+
+END_DECLS
+
+#endif
diff --git a/lib/vf6xx/Makefile b/lib/vf6xx/Makefile
index f1d66236..bf5392c8 100644
--- a/lib/vf6xx/Makefile
+++ b/lib/vf6xx/Makefile
@@ -34,7 +34,7 @@ CFLAGS		= -Os -g \
 		  -mcpu=cortex-m4 -mthumb $(FP_FLAGS) -Wstrict-prototypes \
 		  -ffunction-sections -fdata-sections -MD -DVF6XX
 ARFLAGS		= rcs
-OBJS		= ccm.o
+OBJS		= ccm.o uart.o
 
 VPATH += ../cm3
 
diff --git a/lib/vf6xx/uart.c b/lib/vf6xx/uart.c
new file mode 100644
index 00000000..0c5f16c2
--- /dev/null
+++ b/lib/vf6xx/uart.c
@@ -0,0 +1,225 @@
+/** @defgroup VF6xx_uart UART
+ *
+ * @ingroup VF6xx
+ *
+ * @section vf6xx_uart_api_ex UART API.
+ *
+ * @brief <b>VF6xx Universal Asynchronous Receiver/Transmitter (UART)</b>
+ *
+ * @author @htmlonly &copy; @endhtmlonly 2014 Stefan Agner <stefan@agner.ch>
+ *
+ * @date 03 July 2014
+ *
+ * This library supports the UART in the VF6xx SoC of Freescale.
+ * Devices can have up to 6 UARTs.
+ *
+ * LGPL License Terms @ref lgpl_license
+ */
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2014 Stefan Agner <stefan@agner.ch>
+ *
+ * This library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU Lesser General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public License
+ * along with this library.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/**@{*/
+
+#include <libopencm3/vf6xx/uart.h>
+#include <libopencm3/vf6xx/ccm.h>
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Set Baudrate.
+
+The baud rate is computed from the IPG bus clock. The bus clock must be
+calculated by using @ref ccm_calculate_clocks before calling this function.
+
+@param[in] uart unsigned 32 bit. UART block register address base @ref
+uart_reg_base
+@param[in] baud unsigned 32 bit. Baud rate specified in Hz.
+*/
+
+void uart_set_baudrate(uint32_t uart, uint32_t baud)
+{
+	uint32_t bd_clk = ccm_ipg_bus_clk / baud;
+	uint32_t sbr;
+
+	/* Round up if LSB is one... */
+	bd_clk /= 8;
+	sbr = bd_clk / 2 + (bd_clk & 0x1);
+
+	UART_BDL(uart) = sbr & UART_BDL_SBR_MASK;
+	UART_BDH(uart) = (sbr >> 8) & UART_BDH_SBR_MASK;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Set Parity.
+
+The parity bit can be selected as none, even or odd.
+
+@param[in] uart unsigned 32 bit. UART block register address base @ref
+uart_reg_base
+@param[in] parity unsigned 8 bit. Parity @ref uart_parity.
+*/
+
+void uart_set_parity(uint32_t uart, uint8_t parity)
+{
+	uint8_t reg8;
+
+	reg8 = UART_C1(uart);
+	reg8 = (reg8 & ~UART_PARITY_MASK) | parity;
+	UART_C1(uart) = reg8;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Set Hardware Flow Control.
+
+The flow control bit can be selected as none, RTS, CTS or RTS+CTS.
+
+@param[in] uart unsigned 32 bit. UART block register address base @ref
+uart_reg_base
+@param[in] flowcontrol unsigned 8 bit. Flowcontrol @ref uart_cr3_flowcontrol.
+*/
+
+void uart_set_flow_control(uint32_t uart, uint8_t flowcontrol)
+{
+	uint8_t reg8;
+
+	reg8 = UART_MODEM(uart);
+	reg8 = (reg8 & ~UART_FLOWCONTROL_MASK) | flowcontrol;
+	UART_MODEM(uart) = reg8;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Enable.
+
+Enable Tramitter and Receiver
+
+@param[in] uart unsigned 32 bit. UART block register address base @ref
+uart_reg_base
+*/
+
+void uart_enable(uint32_t uart)
+{
+	UART_C2(uart) |= (UART_C2_TE | UART_C2_RE);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Disable.
+
+At the end of the current frame, the UART is disabled to reduce power.
+
+@param[in] uart unsigned 32 bit. UART block register address base @ref
+uart_reg_base
+*/
+
+void uart_disable(uint32_t uart)
+{
+	UART_C2(uart) &= ~(UART_C2_TE | UART_C2_RE);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Send a Data Word.
+ *
+ * @param[in] uart unsigned 32 bit. UART block register address base @ref
+ * uart_reg_base
+ * @param[in] data unsigned 8 bit.
+ */
+
+void uart_send(uint32_t uart, uint8_t data)
+{
+	UART_D(uart) = data;
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Wait for Transmit Data Buffer Empty
+ *
+ * Blocks until the transmit data buffer becomes empty and is ready to accept
+ * the next data word.
+ *
+ * @param[in] uart unsigned 32 bit. UART block register address base @ref
+ * uart_reg_base
+ */
+
+void uart_wait_send_ready(uint32_t uart)
+{
+	/* Wait until the data has been transferred into the shift register. */
+	while ((UART_S1(uart) & UART_S1_TC) == 0);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Send Data byte blocking
+ *
+ * Blocks until the transmit data buffer becomes empty before sending the
+ * next (given) byte.
+ * @param[in] uart unsigned 32 bit. UART block register address base @ref
+ * uart_reg_base
+ * @param[in] data unsigned 8 bit.
+ */
+
+void uart_send_blocking(uint32_t uart, uint8_t data)
+{
+	uart_wait_send_ready(uart);
+	uart_send(uart, data);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Read a Received Data Word.
+ *
+ * @param[in] uart unsigned 32 bit. UART block register address base @ref
+ * uart_reg_base
+ * @returns unsigned 8 bit data word.
+ */
+
+uint8_t uart_recv(uint32_t uart)
+{
+	/* Receive data. */
+	return UART_D(uart);
+}
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Wait for Received Data Available
+ *
+ * Blocks until the receive data buffer holds a valid received data word.
+ *
+ * @param[in] uart unsigned 32 bit. UART block register address base @ref
+ * uart_reg_base
+ */
+
+void uart_wait_recv_ready(uint32_t uart)
+{
+	/* Wait until the data is ready to be received. */
+	while ((UART_S1(uart) & UART_S1_RDRF) == 0);
+}
+
+
+/*---------------------------------------------------------------------------*/
+/** @brief UART Read a Received Data Word with Blocking.
+
+Wait until a data word has been received then return the word.
+
+@param[in] uart unsigned 32 bit. UART block register address base @ref
+uart_reg_base
+@returns unsigned 16 bit data word.
+*/
+
+uint8_t uart_recv_blocking(uint32_t uart)
+{
+	uart_wait_recv_ready(uart);
+
+	return uart_recv(uart);
+}
+
+/**@}*/
+