stm32l4: rcc: Add core functions
Based on STM32L1, and rather a lot of duplication unfortunately.
This commit is contained in:
Karl Palsson
359
lib/stm32/l4/rcc.c
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359
lib/stm32/l4/rcc.c
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/** @defgroup rcc_file RCC
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*
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* @ingroup STM32L4xx
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*
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* @section rcc_l4_api_ex Reset and Clock Control API.
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*
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* @brief <b>libopencm3 STM32L4xx Reset and Clock Control</b>
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*
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* @author @htmlonly © @endhtmlonly 2016 Karl Palsson <karlp@tweak.net.au>
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*
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* @date 12 Feb 2016
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*
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* This library supports the Reset and Clock Control System in the STM32 series
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* of ARM Cortex Microcontrollers by ST Microelectronics.
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*
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* LGPL License Terms @ref lgpl_license
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*/
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/*
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* This file is part of the libopencm3 project.
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*
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* Copyright (C) 2016 Karl Palsson <karlp@tweak.net.au>
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*
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* This library is free software: you can redistribute it and/or modify
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* it under the terms of the GNU Lesser General Public License as published by
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* the Free Software Foundation, either version 3 of the License, or
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* (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public License
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* along with this library. If not, see <http://www.gnu.org/licenses/>.
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*/
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/**@{*/
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#include <libopencm3/stm32/rcc.h>
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/* Set the default clock frequencies after reset. */
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uint32_t rcc_ahb_frequency = 4000000;
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uint32_t rcc_apb1_frequency = 4000000;
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uint32_t rcc_apb2_frequency = 4000000;
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void rcc_osc_ready_int_clear(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CICR |= RCC_CICR_PLLRDYC;
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break;
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case RCC_HSE:
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RCC_CICR |= RCC_CICR_HSERDYC;
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break;
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case RCC_HSI16:
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RCC_CICR |= RCC_CICR_HSIRDYC;
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break;
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case RCC_MSI:
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RCC_CICR |= RCC_CICR_MSIRDYC;
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break;
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case RCC_LSE:
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RCC_CICR |= RCC_CICR_LSERDYC;
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break;
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case RCC_LSI:
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RCC_CICR |= RCC_CICR_LSIRDYC;
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break;
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}
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}
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void rcc_osc_ready_int_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIER |= RCC_CIER_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIER |= RCC_CIER_HSERDYIE;
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break;
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case RCC_HSI16:
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RCC_CIER |= RCC_CIER_HSIRDYIE;
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break;
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case RCC_MSI:
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RCC_CIER |= RCC_CIER_MSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIER |= RCC_CIER_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIER |= RCC_CIER_LSIRDYIE;
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break;
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}
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}
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void rcc_osc_ready_int_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CIER &= ~RCC_CIER_PLLRDYIE;
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break;
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case RCC_HSE:
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RCC_CIER &= ~RCC_CIER_HSERDYIE;
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break;
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case RCC_HSI16:
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RCC_CIER &= ~RCC_CIER_HSIRDYIE;
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break;
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case RCC_MSI:
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RCC_CIER &= ~RCC_CIER_MSIRDYIE;
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break;
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case RCC_LSE:
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RCC_CIER &= ~RCC_CIER_LSERDYIE;
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break;
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case RCC_LSI:
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RCC_CIER &= ~RCC_CIER_LSIRDYIE;
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break;
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}
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}
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int rcc_osc_ready_int_flag(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return ((RCC_CIFR & RCC_CIFR_PLLRDYF) != 0);
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break;
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case RCC_HSE:
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return ((RCC_CIFR & RCC_CIFR_HSERDYF) != 0);
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break;
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case RCC_HSI16:
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return ((RCC_CIFR & RCC_CIFR_HSIRDYF) != 0);
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break;
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case RCC_MSI:
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return ((RCC_CIFR & RCC_CIFR_MSIRDYF) != 0);
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break;
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case RCC_LSE:
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return ((RCC_CIFR & RCC_CIFR_LSERDYF) != 0);
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break;
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case RCC_LSI:
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return ((RCC_CIFR & RCC_CIFR_LSIRDYF) != 0);
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break;
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}
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return false;
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}
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void rcc_css_int_clear(void)
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{
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RCC_CICR |= RCC_CICR_CSSC;
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}
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int rcc_css_int_flag(void)
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{
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return ((RCC_CIFR & RCC_CIFR_CSSF) != 0);
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}
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bool rcc_is_osc_ready(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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return (RCC_CR & RCC_CR_PLLRDY);
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case RCC_HSE:
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return (RCC_CR & RCC_CR_HSERDY);
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case RCC_HSI16:
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return (RCC_CR & RCC_CR_HSIRDY);
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case RCC_MSI:
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return (RCC_CR & RCC_CR_MSIRDY);
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case RCC_LSE:
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return (RCC_BDCR & RCC_BDCR_LSERDY);
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case RCC_LSI:
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return (RCC_CSR & RCC_CSR_LSIRDY);
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}
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return false;
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}
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void rcc_wait_for_osc_ready(enum rcc_osc osc)
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{
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while (!rcc_is_osc_ready(osc));
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}
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void rcc_wait_for_sysclk_status(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
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!= RCC_CFGR_SWS_PLL);
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break;
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case RCC_HSE:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
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!= RCC_CFGR_SWS_HSE);
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break;
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case RCC_HSI16:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
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!= RCC_CFGR_SWS_HSI16);
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break;
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case RCC_MSI:
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while (((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK)
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!= RCC_CFGR_SWS_MSI);
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break;
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default:
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/* Shouldn't be reached. */
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break;
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}
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}
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void rcc_osc_on(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR |= RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEON;
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break;
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case RCC_HSI16:
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RCC_CR |= RCC_CR_HSION;
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break;
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case RCC_MSI:
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RCC_CR |= RCC_CR_MSION;
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break;
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case RCC_LSE:
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RCC_BDCR |= RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR |= RCC_CSR_LSION;
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break;
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}
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}
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void rcc_osc_off(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_PLL:
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RCC_CR &= ~RCC_CR_PLLON;
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break;
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEON;
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break;
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case RCC_HSI16:
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RCC_CR &= ~RCC_CR_HSION;
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break;
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case RCC_MSI:
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RCC_CR &= ~RCC_CR_MSION;
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break;
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case RCC_LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEON;
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break;
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case RCC_LSI:
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RCC_CSR &= ~RCC_CSR_LSION;
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break;
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}
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}
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void rcc_css_enable(void)
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{
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RCC_CR |= RCC_CR_CSSON;
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}
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void rcc_css_disable(void)
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{
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RCC_CR &= ~RCC_CR_CSSON;
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}
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void rcc_osc_bypass_enable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR |= RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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RCC_BDCR |= RCC_BDCR_LSEBYP;
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break;
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case RCC_PLL:
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case RCC_HSI16:
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case RCC_MSI:
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case RCC_LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_osc_bypass_disable(enum rcc_osc osc)
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{
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switch (osc) {
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case RCC_HSE:
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RCC_CR &= ~RCC_CR_HSEBYP;
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break;
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case RCC_LSE:
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RCC_BDCR &= ~RCC_BDCR_LSEBYP;
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break;
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case RCC_PLL:
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case RCC_HSI16:
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case RCC_MSI:
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case RCC_LSI:
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/* Do nothing, only HSE/LSE allowed here. */
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break;
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}
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}
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void rcc_set_sysclk_source(uint32_t clk)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_SW_MASK << RCC_CFGR_SW_SHIFT);
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RCC_CFGR = (reg32 | (clk << RCC_CFGR_SW_SHIFT));
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}
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void rcc_set_pll_source(uint32_t pllsrc)
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{
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uint32_t reg32;
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reg32 = RCC_PLLCFGR;
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reg32 &= ~(RCC_PLLCFGR_PLLSRC_MASK << RCC_PLLCFGR_PLLSRC_SHIFT);
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RCC_PLLCFGR = (reg32 | (pllsrc << RCC_PLLCFGR_PLLSRC_SHIFT));
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}
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void rcc_set_ppre2(uint32_t ppre2)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE2_MASK << RCC_CFGR_PPRE2_SHIFT);
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RCC_CFGR = (reg32 | (ppre2 << RCC_CFGR_PPRE2_SHIFT));
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}
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void rcc_set_ppre1(uint32_t ppre1)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_PPRE1_MASK << RCC_CFGR_PPRE1_SHIFT);
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RCC_CFGR = (reg32 | (ppre1 << RCC_CFGR_PPRE1_SHIFT));
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}
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void rcc_set_hpre(uint32_t hpre)
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{
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uint32_t reg32;
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reg32 = RCC_CFGR;
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reg32 &= ~(RCC_CFGR_HPRE_MASK << RCC_CFGR_HPRE_SHIFT);
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RCC_CFGR = (reg32 | (hpre << RCC_CFGR_HPRE_SHIFT));
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}
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void rcc_set_main_pll(uint32_t source, uint32_t pllm, uint32_t plln, uint32_t pllp,
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uint32_t pllq, uint32_t pllr)
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{
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RCC_PLLCFGR = (pllm << RCC_PLLCFGR_PLLM_SHIFT) |
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(plln << RCC_PLLCFGR_PLLN_SHIFT) |
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(pllp) |
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(source << RCC_PLLCFGR_PLLSRC_SHIFT) |
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(pllq << RCC_PLLCFGR_PLLQ_SHIFT) |
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(pllr << RCC_PLLCFGR_PLLR_SHIFT) | RCC_PLLCFGR_PLLREN;
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}
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uint32_t rcc_system_clock_source(void)
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{
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/* Return the clock source which is used as system clock. */
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return ((RCC_CFGR >> RCC_CFGR_SWS_SHIFT) & RCC_CFGR_SWS_MASK);
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}
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/**@}*/
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