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doxygen: fix more broken groupings

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This commit is contained in:
Karl Palsson
2020-12-10 22:25:51 +00:00
parent 992a4d3753
commit 97d5e9a403
10 changed files with 27 additions and 35 deletions
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4
include/libopencm3/stm32/common/flash_common_f24.h
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@@ -59,7 +59,7 @@
#define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14) #define FLASH_OPTCR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
/** Flash Option Control register 1 (bank 2) */ /** Flash Option Control register 1 (bank 2) */
#define FLASH_OPTCR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18) #define FLASH_OPTCR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
/*@}*/ /**@}*/
/** @defgroup flash_latency FLASH Wait States /** @defgroup flash_latency FLASH Wait States
@ingroup flash_defines @ingroup flash_defines
@@ -73,7 +73,7 @@
#define FLASH_ACR_LATENCY_5WS 0x05 #define FLASH_ACR_LATENCY_5WS 0x05
#define FLASH_ACR_LATENCY_6WS 0x06 #define FLASH_ACR_LATENCY_6WS 0x06
#define FLASH_ACR_LATENCY_7WS 0x07 #define FLASH_ACR_LATENCY_7WS 0x07
/*@}*/ /**@}*/
#define FLASH_ACR_LATENCY_SHIFT 0 #define FLASH_ACR_LATENCY_SHIFT 0
#define FLASH_ACR_LATENCY_MASK 0x0f #define FLASH_ACR_LATENCY_MASK 0x0f

2
include/libopencm3/stm32/f0/crs.h
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@@ -1,6 +1,6 @@
/** @defgroup crs_defines CRS Defines /** @defgroup crs_defines CRS Defines
* *
* @brief <b>Defined Constants and Types for the Clock Recovery System.</b> * @brief <b>Defined Constants and Types for the Clock Recovery System</b>
* *
* @ingroup STM32F0xx_defines * @ingroup STM32F0xx_defines
* *

8
include/libopencm3/stm32/f1/bkp.h
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@@ -161,7 +161,7 @@
/* Backup data register 42 (BKP_DR42) */ /* Backup data register 42 (BKP_DR42) */
#define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC) #define BKP_DR42 MMIO32(BACKUP_REGS_BASE + 0xBC)
/*@}*/ /**@}*/
/** @defgroup BKP_RTCCR_Values BKP_RTCCR Values /** @defgroup BKP_RTCCR_Values BKP_RTCCR Values
* @ingroup bkp_defines * @ingroup bkp_defines
@@ -177,7 +177,7 @@
/** CAL[6:0]: Calibration value */ /** CAL[6:0]: Calibration value */
#define BKP_RTCCR_CAL_LSB 0 #define BKP_RTCCR_CAL_LSB 0
/*@}*/ /**@}*/
/** @defgroup BKP_CR_Values BKP_CR Values /** @defgroup BKP_CR_Values BKP_CR Values
* @ingroup bkp_defines * @ingroup bkp_defines
@@ -187,7 +187,7 @@
/** TPE: TAMPER pin enable */ /** TPE: TAMPER pin enable */
#define BKP_CR_TPE (1 << 0) #define BKP_CR_TPE (1 << 0)
/*@}*/ /**@}*/
/** @defgroup BKP_CSR_Values BKP_CSR Values /** @defgroup BKP_CSR_Values BKP_CSR Values
* @ingroup bkp_defines * @ingroup bkp_defines
@@ -206,6 +206,6 @@
/** CTE: Clear tamper event */ /** CTE: Clear tamper event */
#define BKP_CSR_CTE (1 << 0) #define BKP_CSR_CTE (1 << 0)
/*@}*/ /**@}*/
#endif #endif

2
include/libopencm3/stm32/f7/flash.h
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@@ -59,7 +59,7 @@
#define FLASH_ACR_ARTRST (1 << 11) #define FLASH_ACR_ARTRST (1 << 11)
#define FLASH_ACR_ARTEN (1 << 9) #define FLASH_ACR_ARTEN (1 << 9)
#define FLASH_ACR_PRFTEN (1 << 8) #define FLASH_ACR_PRFTEN (1 << 8)
/*@}*/ /**@}*/
#define FLASH_SR_ERSERR (1 << 7) #define FLASH_SR_ERSERR (1 << 7)

10
include/libopencm3/stm32/f7/pwr.h
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@@ -50,7 +50,7 @@ LGPL License Terms @ref lgpl_license
/** Power control/status register 2 (PWR_CSR2) */ /** Power control/status register 2 (PWR_CSR2) */
#define PWR_CSR2 MMIO32(POWER_CONTROL_BASE + 0x0c) #define PWR_CSR2 MMIO32(POWER_CONTROL_BASE + 0x0c)
/*@}*/ /**@}*/
/** @defgroup pwr_cr1_defines PWR_CR1 values /** @defgroup pwr_cr1_defines PWR_CR1 values
* @ingroup STM32F_pwr_defines * @ingroup STM32F_pwr_defines
@@ -134,7 +134,7 @@ LGPL License Terms @ref lgpl_license
/** LPDS: Low-power deepsleep */ /** LPDS: Low-power deepsleep */
#define PWR_CR1_LPDS (1 << 0) #define PWR_CR1_LPDS (1 << 0)
/*@}*/ /**@}*/
/** @defgroup pwr_csr1_defines PWR_CSR1 values /** @defgroup pwr_csr1_defines PWR_CSR1 values
* @ingroup STM32F_pwr_defines * @ingroup STM32F_pwr_defines
@@ -185,7 +185,7 @@ LGPL License Terms @ref lgpl_license
/** WUIF: Wakeup internal flag */ /** WUIF: Wakeup internal flag */
#define PWR_CSR1_WUIF (1 << 0) #define PWR_CSR1_WUIF (1 << 0)
/*@}*/ /**@}*/
/** @defgroup pwr_cr2_defines PWR_CR2 values /** @defgroup pwr_cr2_defines PWR_CR2 values
* @ingroup STM32F_pwr_defines * @ingroup STM32F_pwr_defines
@@ -230,7 +230,7 @@ LGPL License Terms @ref lgpl_license
/** CWUPF1: Clear Wakeup Pin flag for PA0 */ /** CWUPF1: Clear Wakeup Pin flag for PA0 */
#define PWR_CR2_CWUPF1 (1 << 0) #define PWR_CR2_CWUPF1 (1 << 0)
/*@}*/ /**@}*/
/** @defgroup pwr_csr2_defines PWR_CSR2 values /** @defgroup pwr_csr2_defines PWR_CSR2 values
* @ingroup STM32F_pwr_defines * @ingroup STM32F_pwr_defines
@@ -275,7 +275,7 @@ LGPL License Terms @ref lgpl_license
/** WUPF1: Wakeup Pin flag for PA0 */ /** WUPF1: Wakeup Pin flag for PA0 */
#define PWR_CSR2_WUPF1 (1 << 0) #define PWR_CSR2_WUPF1 (1 << 0)
/*@}*/ /**@}*/
/* --- Function prototypes ------------------------------------------------- */ /* --- Function prototypes ------------------------------------------------- */
enum pwr_vos_scale { enum pwr_vos_scale {

2
include/libopencm3/stm32/l0/crs.h
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@@ -1,6 +1,6 @@
/** @defgroup crs_defines CRS Defines /** @defgroup crs_defines CRS Defines
* *
* @brief <b>Defined Constants and Types for the Clock Recovery System.</b> * @brief <b>Defined Constants and Types for the Clock Recovery System</b>
* *
* @ingroup STM32L0xx_defines * @ingroup STM32L0xx_defines
* *

6
include/libopencm3/stm32/l0/timer.h
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@@ -32,8 +32,7 @@ LGPL License Terms @ref lgpl_license
* along with this library. If not, see <http://www.gnu.org/licenses/>. * along with this library. If not, see <http://www.gnu.org/licenses/>.
*/ */
#ifndef LIBOPENCM3_TIMER_H #pragma once
#define LIBOPENCM3_TIMER_H
#include <libopencm3/stm32/common/timer_common_all.h> #include <libopencm3/stm32/common/timer_common_all.h>
@@ -98,6 +97,3 @@ LGPL License Terms @ref lgpl_license
/**@}*/ /**@}*/
#endif
/**@}*/

2
include/libopencm3/stm32/l4/crs.h
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@@ -1,6 +1,6 @@
/** @defgroup crs_defines CRS Defines /** @defgroup crs_defines CRS Defines
* *
* @brief <b>Defined Constants and Types for the Clock Recovery System.</b> * @brief <b>Defined Constants and Types for the Clock Recovery System</b>
* *
* @ingroup STM32L4xx_defines * @ingroup STM32L4xx_defines
* *

22
include/libopencm3/stm32/l4/rcc.h
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@@ -128,7 +128,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_CR_MSIRANGE_24MHZ 9 #define RCC_CR_MSIRANGE_24MHZ 9
#define RCC_CR_MSIRANGE_32MHZ 10 #define RCC_CR_MSIRANGE_32MHZ 10
#define RCC_CR_MSIRANGE_48MHZ 11 #define RCC_CR_MSIRANGE_48MHZ 11
/*@}*/ /**@}*/
#define RCC_CR_MSIRGSEL (1 << 3) #define RCC_CR_MSIRGSEL (1 << 3)
#define RCC_CR_MSIPLLEN (1 << 2) #define RCC_CR_MSIPLLEN (1 << 2)
#define RCC_CR_MSIRDY (1 << 1) #define RCC_CR_MSIRDY (1 << 1)
@@ -255,7 +255,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
@{*/ @{*/
#define RCC_PLLCFGR_PLLN_SHIFT 0x8 #define RCC_PLLCFGR_PLLN_SHIFT 0x8
#define RCC_PLLCFGR_PLLN_MASK 0x7f #define RCC_PLLCFGR_PLLN_MASK 0x7f
/*@}*/ /**@}*/
/** @defgroup rcc_pllcfgr_pllm RCC_PLLCFGR PLLM values /** @defgroup rcc_pllcfgr_pllm RCC_PLLCFGR PLLM values
@ingroup STM32L4xx_rcc_defines @ingroup STM32L4xx_rcc_defines
@@ -264,7 +264,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_PLLCFGR_PLLM_SHIFT 0x4 #define RCC_PLLCFGR_PLLM_SHIFT 0x4
#define RCC_PLLCFGR_PLLM_MASK 0x7 #define RCC_PLLCFGR_PLLM_MASK 0x7
#define RCC_PLLCFGR_PLLM(x) ((x)-1) #define RCC_PLLCFGR_PLLM(x) ((x)-1)
/*@}*/ /**@}*/
#define RCC_PLLCFGR_PLLSRC_SHIFT 0 #define RCC_PLLCFGR_PLLSRC_SHIFT 0
#define RCC_PLLCFGR_PLLSRC_MASK 0x3 #define RCC_PLLCFGR_PLLSRC_MASK 0x3
@@ -420,7 +420,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_AHB1ENR_FLASHEN (1 << 8) #define RCC_AHB1ENR_FLASHEN (1 << 8)
#define RCC_AHB1ENR_DMA2EN (1 << 1) #define RCC_AHB1ENR_DMA2EN (1 << 1)
#define RCC_AHB1ENR_DMA1EN (1 << 0) #define RCC_AHB1ENR_DMA1EN (1 << 0)
/*@}*/ /**@}*/
/* --- RCC_AHB2ENR values --------------------------------------------------- */ /* --- RCC_AHB2ENR values --------------------------------------------------- */
@@ -440,7 +440,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_AHB2ENR_GPIOCEN (1 << 2) #define RCC_AHB2ENR_GPIOCEN (1 << 2)
#define RCC_AHB2ENR_GPIOBEN (1 << 1) #define RCC_AHB2ENR_GPIOBEN (1 << 1)
#define RCC_AHB2ENR_GPIOAEN (1 << 0) #define RCC_AHB2ENR_GPIOAEN (1 << 0)
/*@}*/ /**@}*/
/* --- RCC_AHB3ENR values --------------------------------------------------- */ /* --- RCC_AHB3ENR values --------------------------------------------------- */
@@ -450,7 +450,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
@{*/ @{*/
#define RCC_AHB3ENR_QSPIEN (1 << 8) #define RCC_AHB3ENR_QSPIEN (1 << 8)
#define RCC_AHB3ENR_FMCEN (1 << 0) #define RCC_AHB3ENR_FMCEN (1 << 0)
/*@}*/ /**@}*/
/**@}*/ /**@}*/
@@ -483,7 +483,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_APB1ENR1_TIM4EN (1 << 2) #define RCC_APB1ENR1_TIM4EN (1 << 2)
#define RCC_APB1ENR1_TIM3EN (1 << 1) #define RCC_APB1ENR1_TIM3EN (1 << 1)
#define RCC_APB1ENR1_TIM2EN (1 << 0) #define RCC_APB1ENR1_TIM2EN (1 << 0)
/*@}*/ /**@}*/
/* --- RCC_APB1ENR2 values -------------------------------------------------- */ /* --- RCC_APB1ENR2 values -------------------------------------------------- */
@@ -494,8 +494,8 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_APB1ENR2_LPTIM2EN (1 << 5) #define RCC_APB1ENR2_LPTIM2EN (1 << 5)
#define RCC_APB1ENR2_SWPMI1EN (1 << 2) #define RCC_APB1ENR2_SWPMI1EN (1 << 2)
#define RCC_APB1ENR2_LPUART1EN (1 << 0) #define RCC_APB1ENR2_LPUART1EN (1 << 0)
/*@}*/ /**@}*/
/*@}*/ /**@}*/
/* --- RCC_APB2ENR values -------------------------------------------------- */ /* --- RCC_APB2ENR values -------------------------------------------------- */
@@ -516,7 +516,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_APB2ENR_SDMMC1EN (1 << 10) #define RCC_APB2ENR_SDMMC1EN (1 << 10)
#define RCC_APB2ENR_FWEN (1 << 7) #define RCC_APB2ENR_FWEN (1 << 7)
#define RCC_APB2ENR_SYSCFGEN (1 << 0) #define RCC_APB2ENR_SYSCFGEN (1 << 0)
/*@}*/ /**@}*/
/* --- RCC_AHB1SMENR - AHB1 periph clock in sleep mode --------------------- */ /* --- RCC_AHB1SMENR - AHB1 periph clock in sleep mode --------------------- */
@@ -722,7 +722,7 @@ Twelve frequency ranges are available: 100 kHz, 200 kHz, 400 kHz, 800 kHz,
#define RCC_CSR_MSIRANGE_2MHZ 5 #define RCC_CSR_MSIRANGE_2MHZ 5
#define RCC_CSR_MSIRANGE_4MHZ 6 #define RCC_CSR_MSIRANGE_4MHZ 6
#define RCC_CSR_MSIRANGE_8MHZ 7 #define RCC_CSR_MSIRANGE_8MHZ 7
/*@}*/ /**@}*/
#define RCC_CSR_LSIRDY (1 << 1) #define RCC_CSR_LSIRDY (1 << 1)
#define RCC_CSR_LSION (1 << 0) #define RCC_CSR_LSION (1 << 0)

4
lib/stm32/common/flash_common_l01.c
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@@ -97,10 +97,6 @@ void flash_unlock_acr(void)
FLASH_PDKEYR = FLASH_PDKEYR_PDKEY2; FLASH_PDKEYR = FLASH_PDKEYR_PDKEY2;
} }
/**
* Erase a page in ram.
* @param page_address must be first word in page for L1, any address in page for L0
*/
void flash_erase_page(uint32_t page_address) void flash_erase_page(uint32_t page_address)
{ {
FLASH_PECR |= FLASH_PECR_ERASE | FLASH_PECR_PROG; FLASH_PECR |= FLASH_PECR_ERASE | FLASH_PECR_PROG;