Merge pull request #79 "More L1 support (and f2/f4 rtc)"
Merge remote-tracking branch 'karlp/pr_more_l1_rtc'
This commit is contained in:
Piotr Esden-Tempski
119
include/libopencm3/stm32/common/pwr_common_all.h
Normal file
119
include/libopencm3/stm32/common/pwr_common_all.h
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@@ -0,0 +1,119 @@
|
||||
/** @addtogroup pwr_defines */
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA PWR.H */
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||||
|
||||
#ifndef LIBOPENCM3_PWR_COMMON_ALL_H
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#define LIBOPENCM3_PWR_COMMON_ALL_H
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/**@{*/
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|
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#include <libopencm3/cm3/common.h>
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|
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/* --- PWR registers ------------------------------------------------------- */
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/* Power control register (PWR_CR) */
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#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
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/* Power control/status register (PWR_CSR) */
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#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
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||||
|
||||
/* --- PWR_CR values ------------------------------------------------------- */
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||||
|
||||
/* Bits [31:9]: Reserved, must be kept at reset value. */
|
||||
|
||||
/* DBP: Disable backup domain write protection */
|
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#define PWR_CR_DBP (1 << 8)
|
||||
|
||||
/* PLS[7:5]: PVD level selection */
|
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#define PWR_CR_PLS_LSB 5
|
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/** @defgroup pwr_pls PVD level selection
|
||||
@ingroup STM32F_pwr_defines
|
||||
|
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@{*/
|
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#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
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#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
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/**@}*/
|
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#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
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||||
|
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/* PVDE: Power voltage detector enable */
|
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#define PWR_CR_PVDE (1 << 4)
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|
||||
/* CSBF: Clear standby flag */
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#define PWR_CR_CSBF (1 << 3)
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|
||||
/* CWUF: Clear wakeup flag */
|
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#define PWR_CR_CWUF (1 << 2)
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|
||||
/* PDDS: Power down deepsleep */
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#define PWR_CR_PDDS (1 << 1)
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|
||||
/* LPDS: Low-power deepsleep */
|
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#define PWR_CR_LPDS (1 << 0)
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|
||||
/* --- PWR_CSR values ------------------------------------------------------ */
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|
||||
/* Bits [31:9]: Reserved, must be kept at reset value. */
|
||||
|
||||
/* EWUP: Enable WKUP pin */
|
||||
#define PWR_CSR_EWUP (1 << 8)
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|
||||
/* Bits [7:3]: Reserved, must be kept at reset value. */
|
||||
|
||||
/* PVDO: PVD output */
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#define PWR_CSR_PVDO (1 << 2)
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|
||||
/* SBF: Standby flag */
|
||||
#define PWR_CSR_SBF (1 << 1)
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|
||||
/* WUF: Wakeup flag */
|
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#define PWR_CSR_WUF (1 << 0)
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||||
|
||||
/* --- PWR function prototypes ------------------------------------------- */
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void pwr_disable_backup_domain_write_protect(void);
|
||||
void pwr_enable_backup_domain_write_protect(void);
|
||||
void pwr_enable_power_voltage_detect(u32 pvd_level);
|
||||
void pwr_disable_power_voltage_detect(void);
|
||||
void pwr_clear_standby_flag(void);
|
||||
void pwr_clear_wakeup_flag(void);
|
||||
void pwr_set_standby_mode(void);
|
||||
void pwr_set_stop_mode(void);
|
||||
void pwr_voltage_regulator_on_in_stop(void);
|
||||
void pwr_voltage_regulator_low_power_in_stop(void);
|
||||
void pwr_enable_wakeup_pin(void);
|
||||
void pwr_disable_wakeup_pin(void);
|
||||
bool pwr_voltage_high(void);
|
||||
bool pwr_get_standby_flag(void);
|
||||
bool pwr_get_wakeup_flag(void);
|
||||
|
||||
END_DECLS
|
||||
|
||||
/**@}*/
|
||||
#endif
|
||||
302
include/libopencm3/stm32/common/rtc_common_bcd.h
Normal file
302
include/libopencm3/stm32/common/rtc_common_bcd.h
Normal file
@@ -0,0 +1,302 @@
|
||||
/** @addtogroup rtc_defines */
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2012 Karl Palsson <karlp@tweak.net.au>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/* THIS FILE SHOULD NOT BE INCLUDED DIRECTLY, BUT ONLY VIA RTC.H */
|
||||
|
||||
/*
|
||||
* This covers the "version 2" RTC peripheral. This is completely different
|
||||
* to the v1 RTC periph on the F1 series devices. It has BCD counters, with
|
||||
* automatic leapyear corrections and daylight savings support.
|
||||
* This peripheral is used on the F0, F2, F3, F4 and L1 devices, though some
|
||||
* only support a subset.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_RTC2_H
|
||||
#define LIBOPENCM3_RTC2_H
|
||||
|
||||
/**@{*/
|
||||
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
|
||||
/* RTC time register (RTC_TR) */
|
||||
#define RTC_TR MMIO32(RTC_BASE + 0x00)
|
||||
|
||||
/* RTC date register (RTC_DR) */
|
||||
#define RTC_DR MMIO32(RTC_BASE + 0x04)
|
||||
|
||||
/* RTC control register (RTC_CR) */
|
||||
#define RTC_CR MMIO32(RTC_BASE + 0x08)
|
||||
|
||||
/* RTC initialization and status register (RTC_ISR) */
|
||||
#define RTC_ISR MMIO32(RTC_BASE + 0x0c)
|
||||
|
||||
/* RTC prescaler register (RTC_PRER) */
|
||||
#define RTC_PRER MMIO32(RTC_BASE + 0x10)
|
||||
|
||||
/* RTC wakeup timer register (RTC_WUTR) */
|
||||
#define RTC_WUTR MMIO32(RTC_BASE + 0x14)
|
||||
|
||||
/* RTC calibration register (RTC_CALIBR) NB: see also RTC_CALR */
|
||||
#define RTC_CALIBR MMIO32(RTC_BASE + 0x18)
|
||||
|
||||
/* RTC alarm X register (RTC_ALRMxR) */
|
||||
#define RTC_ALRMAR MMIO32(RTC_BASE + 0x1c)
|
||||
#define RTC_ALRMBR MMIO32(RTC_BASE + 0x20)
|
||||
|
||||
/* RTC write protection register (RTC_WPR)*/
|
||||
#define RTC_WPR MMIO32(RTC_BASE + 0x24)
|
||||
|
||||
/* RTC sub second register (RTC_SSR) (high and med+ only) */
|
||||
#define RTC_SSR MMIO32(RTC_BASE + 0x28)
|
||||
|
||||
/* RTC shift control register (RTC_SHIFTR) (high and med+ only) */
|
||||
#define RTC_SHIFTR MMIO32(RTC_BASE + 0x2c)
|
||||
|
||||
/* RTC time stamp time register (RTC_TSTR) */
|
||||
#define RTC_TSTR MMIO32(RTC_BASE + 0x30)
|
||||
/* RTC time stamp date register (RTC_TSDR) */
|
||||
#define RTC_TSDR MMIO32(RTC_BASE + 0x34)
|
||||
/* RTC timestamp sub second register (RTC_TSSSR) (high and med+ only) */
|
||||
#define RTC_TSSSR MMIO32(RTC_BASE + 0x38)
|
||||
|
||||
/* RTC calibration register (RTC_CALR) (high and med+ only) */
|
||||
#define RTC_CALR MMIO32(RTC_BASE + 0x3c)
|
||||
|
||||
/* RTC tamper and alternate function configuration register (RTC_TAFCR) */
|
||||
#define RTC_TAFCR MMIO32(RTC_BASE + 0x40)
|
||||
|
||||
/* RTC alarm X sub second register (RTC_ALRMxSSR) (high and med+ only) */
|
||||
#define RTC_ALRMASSR MMIO32(RTC_BASE + 0x44)
|
||||
#define RTC_ALRMBSSR MMIO32(RTC_BASE + 0x48)
|
||||
|
||||
/* RTC backup registers (RTC_BKPxR) */
|
||||
#define RTC_BKP_BASE (RTC_BASE + 0x50)
|
||||
#define RTC_BKPXR(reg) MMIO32(RTC_BKP_BASE + (4*reg))
|
||||
|
||||
|
||||
/* RTC time register (RTC_TR) bits */
|
||||
#define RTC_TR_TR_PM (1 << 22)
|
||||
#define RTC_TR_HT_SHIFT (20)
|
||||
#define RTC_TR_HT_MASK (0x3)
|
||||
#define RTC_TR_HU_SHIFT (16)
|
||||
#define RTC_TR_HU_MASK (0xf)
|
||||
#define RTC_TR_MNT_SHIFT (12)
|
||||
#define RTC_TR_MNT_MASK (0x7)
|
||||
#define RTC_TR_MNU_SHIFT (8)
|
||||
#define RTC_TR_MNU_MASK (0xf)
|
||||
#define RTC_TR_ST_SHIFT (4)
|
||||
#define RTC_TR_ST_MASK (0x3)
|
||||
#define RTC_TR_SU_SHIFT (0)
|
||||
#define RTC_TR_SU_MASK (0xf)
|
||||
|
||||
/* RTC date register (RTC_DR) bits */
|
||||
#define RTC_DR_YT_SHIFT (20)
|
||||
#define RTC_DR_YT_MASK (0xf)
|
||||
#define RTC_DR_YU_SHIFT (16)
|
||||
#define RTC_DR_YU_MASK (0xf)
|
||||
#define RTC_DR_WDU_SHIFT (13)
|
||||
#define RTC_DR_WDU_MASK (0x7)
|
||||
#define RTC_DR_MT (1<<12)
|
||||
#define RTC_DR_MU_SHIFT (8)
|
||||
#define RTC_DR_MU_MASK (0xf)
|
||||
#define RTC_DR_DT_SHIFT (4)
|
||||
#define RTC_DR_DT_MASK (0x3)
|
||||
#define RTC_DR_DU_SHIFT (0)
|
||||
#define RTC_DR_DU_MASK (0xf)
|
||||
|
||||
/* RTC control register (RTC_CR) bits */
|
||||
#define RTC_CR_COE (1<<23)
|
||||
|
||||
/* These bits are used to select the flag to be routed to AFO_ALARM RTC output */
|
||||
#define RTC_CR_OSEL_SHIFT 21
|
||||
#define RTC_CR_OSEL_MASK (0x3)
|
||||
#define RTC_CR_OSEL_DISABLED (0x0)
|
||||
#define RTC_CR_OSEL_ALARMA (0x1)
|
||||
#define RTC_CR_OSEL_ALARMB (0x2)
|
||||
#define RTC_CR_OSEL_WAKEUP (0x3)
|
||||
|
||||
#define RTC_CR_POL (1<<20)
|
||||
#define RTC_CR_COSEL (1<<19)
|
||||
#define RTC_CR_BKP (1<<18)
|
||||
#define RTC_CR_SUB1H (1<<17)
|
||||
#define RTC_CR_ADD1H (1<<16)
|
||||
#define RTC_CR_TSIE (1<<15)
|
||||
#define RTC_CR_WUTIE (1<<14)
|
||||
#define RTC_CR_ALRBIE (1<<13)
|
||||
#define RTC_CR_ALRAIE (1<<12)
|
||||
#define RTC_CR_TSE (1<<11)
|
||||
#define RTC_CR_WUTE (1<<10)
|
||||
#define RTC_CR_ALRBE (1<<9)
|
||||
#define RTC_CR_ALRAE (1<<8)
|
||||
#define RTC_CR_DCE (1<<7)
|
||||
#define RTC_CR_FMT (1<<6)
|
||||
#define RTC_CR_BYPSHAD (1<<5)
|
||||
#define RTC_CR_REFCKON (1<<4)
|
||||
#define RTC_CR_TSEDGE (1<<3)
|
||||
#define RTC_CR_TSEDGE (1<<3)
|
||||
#define RTC_CR_WUCLKSEL_SHIFT (0)
|
||||
#define RTC_CR_WUCLKSEL_MASK (0x7)
|
||||
#define RTC_CR_WUCLKSEL_RTC_DIV16 (0x0)
|
||||
#define RTC_CR_WUCLKSEL_RTC_DIV8 (0x1)
|
||||
#define RTC_CR_WUCLKSEL_RTC_DIV4 (0x2)
|
||||
#define RTC_CR_WUCLKSEL_RTC_DIV2 (0x3)
|
||||
#define RTC_CR_WUCLKSEL_SPRE (0x4)
|
||||
#define RTC_CR_WUCLKSEL_SPRE_216 (0x6)
|
||||
|
||||
/* RTC initialization and status register (RTC_ISR) bits */
|
||||
#define RTC_ISR_RECALPF (1<<16)
|
||||
#define RTC_ISR_TAMP3F (1<<15)
|
||||
#define RTC_ISR_TAMP2F (1<<14)
|
||||
#define RTC_ISR_TAMP1F (1<<13)
|
||||
#define RTC_ISR_TSOVF (1<<12)
|
||||
#define RTC_ISR_TSF (1<<11)
|
||||
#define RTC_ISR_WUTF (1<<10)
|
||||
#define RTC_ISR_ALRBF (1<<9)
|
||||
#define RTC_ISR_ALRAF (1<<8)
|
||||
#define RTC_ISR_INIT (1<<7)
|
||||
#define RTC_ISR_INITF (1<<6)
|
||||
#define RTC_ISR_RSF (1<<5)
|
||||
#define RTC_ISR_INITS (1<<4)
|
||||
#define RTC_ISR_SHPF (1<<3)
|
||||
#define RTC_ISR_WUTWF (1<<2)
|
||||
#define RTC_ISR_ALRBWF (1<<1)
|
||||
#define RTC_ISR_ALRAWF (1<<0)
|
||||
|
||||
/* RTC prescaler register (RTC_PRER) bits */
|
||||
#define RTC_PRER_PREDIV_A_SHIFT (16)
|
||||
#define RTC_PRER_PREDIV_A_MASK (0x7f)
|
||||
#define RTC_PRER_PREDIV_S_SHIFT (0)
|
||||
#define RTC_PRER_PREDIV_S_MASK (0x7fff)
|
||||
|
||||
/* RTC calibration register (RTC_CALIBR) bits */
|
||||
// FIXME - TODO
|
||||
|
||||
/* RTC Alarm register bits Applies to RTC_ALRMAR and RTC_ALRMBR */
|
||||
#define RTC_ALRMXR_MSK4 (1<<31)
|
||||
#define RTC_ALRMXR_WDSEL (1<<30)
|
||||
#define RTC_ALRMXR_DT_SHIFT (28)
|
||||
#define RTC_ALRMXR_DT_MASK (0x3)
|
||||
#define RTC_ALRMXR_DU_SHIFT (24)
|
||||
#define RTC_ALRMXR_DU_MASK (0xf)
|
||||
#define RTC_ALRMXR_MSK3 (1<<23)
|
||||
#define RTC_ALRMXR_PM (1<<22)
|
||||
#define RTC_ALRMXR_HT_SHIFT (20)
|
||||
#define RTC_ALRMXR_HT_MASK (0x3)
|
||||
#define RTC_ALRMXR_HU_SHIFT (16)
|
||||
#define RTC_ALRMXR_HU_MASK (0xf)
|
||||
#define RTC_ALRMXR_MSK2 (1<<15)
|
||||
#define RTC_ALRMXR_MNT_SHIFT (12)
|
||||
#define RTC_ALRMXR_MNT_MASK (0x7)
|
||||
#define RTC_ALRMXR_MNU_SHIFT (8)
|
||||
#define RTC_ALRMXR_MNU_MASK (0xf)
|
||||
#define RTC_ALRMXR_MSK1 (1<<7)
|
||||
#define RTC_ALRMXR_ST_SHIFT (4)
|
||||
#define RTC_ALRMXR_ST_MASK (0x7)
|
||||
#define RTC_ALRMXR_SU_SHIFT (0)
|
||||
#define RTC_ALRMXR_SU_MASK (0xf)
|
||||
|
||||
/* RTC shift control register (RTC_SHIFTR) */
|
||||
// FIXME - TODO
|
||||
|
||||
/* RTC time stamp time register (RTC_TSTR) bits */
|
||||
#define RTC_TSTR_PM (1<<22)
|
||||
#define RTC_TSTR_HT_SHIFT (20)
|
||||
#define RTC_TSTR_HT_MASK (0x3)
|
||||
#define RTC_TSTR_HU_SHIFT (16)
|
||||
#define RTC_TSTR_HU_MASK (0xf)
|
||||
#define RTC_TSTR_MNT_SHIFT (12)
|
||||
#define RTC_TSTR_MNT_MASK (0x7)
|
||||
#define RTC_TSTR_MNU_SHIFT (8)
|
||||
#define RTC_TSTR_MNU_MASK (0xf)
|
||||
#define RTC_TSTR_ST_SHIFT (4)
|
||||
#define RTC_TSTR_ST_MASK (0x7)
|
||||
#define RTC_TSTR_SU_SHIFT (0)
|
||||
#define RTC_TSTR_SU_MASK (0xf)
|
||||
|
||||
/* RTC time stamp date register (RTC_TSDR) bits */
|
||||
#define RTC_TSDR_WDU_SHIFT (13)
|
||||
#define RTC_TSDR_WDU_MASK (0x7)
|
||||
#define RTC_TSDR_MT (1<<12)
|
||||
#define RTC_TSDR_MU_SHIFT (8)
|
||||
#define RTC_TSDR_MU_MASK (0xf)
|
||||
#define RTC_TSDR_DT_SHIFT (4)
|
||||
#define RTC_TSDR_DT_MASK (0x3)
|
||||
#define RTC_TSDR_DU_SHIFT (0)
|
||||
#define RTC_TSDR_DU_MASK (0xf)
|
||||
|
||||
/* RTC calibration register (RTC_CALR) bits */
|
||||
// FIXME - TODO
|
||||
|
||||
/* RTC tamper and alternate function configuration register (RTC_TAFCR) bits */
|
||||
#define RTC_TAFCR_ALARMOUTTYPE (1<<18)
|
||||
#define RTC_TAFCR_TAMPPUDIS (1<<15)
|
||||
|
||||
#define RTC_TAFCR_TAMPPRCH_SHIFT (13)
|
||||
#define RTC_TAFCR_TAMPPRCH_MASK (0x3)
|
||||
#define RTC_TAFCR_TAMPPRCH_1RTC (0x0)
|
||||
#define RTC_TAFCR_TAMPPRCH_2RTC (0x1)
|
||||
#define RTC_TAFCR_TAMPPRCH_4RTC (0x2)
|
||||
#define RTC_TAFCR_TAMPPRCH_8RTC (0x3)
|
||||
|
||||
#define RTC_TAFCR_TAMPFLT_SHIFT (11)
|
||||
#define RTC_TAFCR_TAMPFLT_MASK (0x3)
|
||||
#define RTC_TAFCR_TAMPFLT_EDGE1 (0x0)
|
||||
#define RTC_TAFCR_TAMPFLT_EDGE2 (0x1)
|
||||
#define RTC_TAFCR_TAMPFLT_EDGE4 (0x2)
|
||||
#define RTC_TAFCR_TAMPFLT_EDGE8 (0x3)
|
||||
|
||||
#define RTC_TAFCR_TAMPFREQ_SHIFT (8)
|
||||
#define RTC_TAFCR_TAMPFREQ_MASK (0x7)
|
||||
#define RTC_TAFCR_TAMPFREQ_RTCDIV32K (0x0)
|
||||
#define RTC_TAFCR_TAMPFREQ_RTCDIV16K (0x1)
|
||||
#define RTC_TAFCR_TAMPFREQ_RTCDIV8K (0x2)
|
||||
#define RTC_TAFCR_TAMPFREQ_RTCDIV4K (0x3)
|
||||
#define RTC_TAFCR_TAMPFREQ_RTCDIV2K (0x4)
|
||||
#define RTC_TAFCR_TAMPFREQ_RTCDIV1K (0x5)
|
||||
#define RTC_TAFCR_TAMPFREQ_RTCDIV512 (0x6)
|
||||
#define RTC_TAFCR_TAMPFREQ_RTCDIV256 (0x7)
|
||||
|
||||
#define RTC_TAFCR_TAMPTS (1<<7)
|
||||
#define RTC_TAFCR_TAMP3TRG (1<<6)
|
||||
#define RTC_TAFCR_TAMP3E (1<<5)
|
||||
#define RTC_TAFCR_TAMP2TRG (1<<4)
|
||||
#define RTC_TAFCR_TAMP2E (1<<3)
|
||||
#define RTC_TAFCR_TAMPIE (1<<2)
|
||||
#define RTC_TAFCR_TAMP1TRG (1<<1)
|
||||
#define RTC_TAFCR_TAMP1E (1<<0)
|
||||
|
||||
/* RTC alarm X sub second register */
|
||||
// FIXME - TODO
|
||||
|
||||
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void rtc_set_prescaler(u32 sync, u32 async);
|
||||
void rtc_wait_for_synchro(void);
|
||||
void rtc_lock(void);
|
||||
void rtc_unlock(void);
|
||||
|
||||
END_DECLS
|
||||
/**@}*/
|
||||
|
||||
#endif /* RTC2_H */
|
||||
|
||||
40
include/libopencm3/stm32/f1/pwr.h
Normal file
40
include/libopencm3/stm32/f1/pwr.h
Normal file
@@ -0,0 +1,40 @@
|
||||
/** @defgroup pwr_defines PWR Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32F1xx PWR Control</b>
|
||||
|
||||
@ingroup STM32F1xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 5 December 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_PWR_H
|
||||
#define LIBOPENCM3_PWR_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/pwr_common_all.h>
|
||||
|
||||
#endif
|
||||
|
||||
@@ -17,6 +17,11 @@
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/*
|
||||
* The F1 RTC is a straight timestamp, a completely different peripheral to
|
||||
* that found in the F2, F3, F4, L1 and F0.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_RTC_H
|
||||
#define LIBOPENCM3_RTC_H
|
||||
|
||||
|
||||
39
include/libopencm3/stm32/f2/rtc.h
Normal file
39
include/libopencm3/stm32/f2/rtc.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/** @defgroup rtc_defines RTC Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32F2xx RTC</b>
|
||||
|
||||
@ingroup STM32F2xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 5 December 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_RTC_H
|
||||
#define LIBOPENCM3_RTC_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/rtc_common_bcd.h>
|
||||
|
||||
#endif
|
||||
@@ -1,3 +1,15 @@
|
||||
/** @defgroup pwr_defines PWR Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32F4xx Power Control</b>
|
||||
|
||||
@ingroup STM32F4xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
@@ -17,10 +29,11 @@
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_PWR_F4_H
|
||||
#define LIBOPENCM3_PWR_F4_H
|
||||
#ifndef LIBOPENCM3_PWR_H
|
||||
#define LIBOPENCM3_PWR_H
|
||||
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/pwr_common_all.h>
|
||||
|
||||
/*
|
||||
* This file extends the common STM32 version with definitions only
|
||||
|
||||
39
include/libopencm3/stm32/f4/rtc.h
Normal file
39
include/libopencm3/stm32/f4/rtc.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/** @defgroup rtc_defines RTC Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32F4xx RTC</b>
|
||||
|
||||
@ingroup STM32F4xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 5 December 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_RTC_H
|
||||
#define LIBOPENCM3_RTC_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/rtc_common_bcd.h>
|
||||
|
||||
#endif
|
||||
@@ -33,10 +33,10 @@
|
||||
|
||||
#define FLASH_ACR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x00)
|
||||
#define FLASH_PECR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x04)
|
||||
#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
|
||||
#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
|
||||
#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
|
||||
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
|
||||
#define FLASH_PDKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x08)
|
||||
#define FLASH_PEKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x0C)
|
||||
#define FLASH_PRGKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x10)
|
||||
#define FLASH_OPTKEYR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x14)
|
||||
#define FLASH_SR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x18)
|
||||
#define FLASH_OBR MMIO32(FLASH_MEM_INTERFACE_BASE + 0x1c)
|
||||
#define FLASH_WRPR1 MMIO32(FLASH_MEM_INTERFACE_BASE + 0x20)
|
||||
@@ -46,9 +46,9 @@
|
||||
/* --- FLASH_ACR values ---------------------------------------------------- */
|
||||
|
||||
#define FLASH_RUNPD (1 << 4)
|
||||
#define FLASH_SLEEPPD (1 << 3)
|
||||
#define FLASH_SLEEPPD (1 << 3)
|
||||
#define FLASH_ACC64 (1 << 2)
|
||||
#define FLASH_PRFTEN (1 << 1)
|
||||
#define FLASH_PRFTEN (1 << 1)
|
||||
#define FLASH_LATENCY_0WS 0x00
|
||||
#define FLASH_LATENCY_1WS 0x01
|
||||
|
||||
@@ -85,30 +85,30 @@
|
||||
|
||||
|
||||
/* --- FLASH_SR values ----------------------------------------------------- */
|
||||
#define FLASH_OPTVERRUSR (1 << 12)
|
||||
#define FLASH_OPTVERR (1 << 11)
|
||||
#define FLASH_SIZEERR (1 << 10)
|
||||
#define FLASH_PGAERR (1 << 9)
|
||||
#define FLASH_WRPERR (1 << 8)
|
||||
#define FLASH_READY (1 << 3)
|
||||
#define FLASH_ENDHV (1 << 2)
|
||||
#define FLASH_EOP (1 << 1)
|
||||
#define FLASH_BSY (1 << 0)
|
||||
#define FLASH_OPTVERRUSR (1 << 12)
|
||||
#define FLASH_OPTVERR (1 << 11)
|
||||
#define FLASH_SIZEERR (1 << 10)
|
||||
#define FLASH_PGAERR (1 << 9)
|
||||
#define FLASH_WRPERR (1 << 8)
|
||||
#define FLASH_READY (1 << 3)
|
||||
#define FLASH_ENDHV (1 << 2)
|
||||
#define FLASH_EOP (1 << 1)
|
||||
#define FLASH_BSY (1 << 0)
|
||||
|
||||
/* --- FLASH_OBR values ----------------------------------------------------- */
|
||||
#define FLASH_BFB2 (1 << 23)
|
||||
#define FLASH_BFB2 (1 << 23)
|
||||
#define FLASH_NRST_STDBY (1 << 22)
|
||||
#define FLASH_NRST_STOP (1 << 21)
|
||||
#define FLASH_IWDG_SW (1 << 20)
|
||||
#define FLASH_BOR_OFF (0x0 << 16)
|
||||
#define FLASH_BOR_LEVEL_1 (0x8 << 16)
|
||||
#define FLASH_BOR_LEVEL_2 (0x9 << 16)
|
||||
#define FLASH_BOR_LEVEL_3 (0xa << 16)
|
||||
#define FLASH_BOR_LEVEL_4 (0xb << 16)
|
||||
#define FLASH_BOR_LEVEL_5 (0xc << 16)
|
||||
#define FLASH_RDPRT_LEVEL_0 (0xaa)
|
||||
#define FLASH_RDPRT_LEVEL_1 (0x00)
|
||||
#define FLASH_RDPRT_LEVEL_2 (0xcc)
|
||||
#define FLASH_NRST_STOP (1 << 21)
|
||||
#define FLASH_IWDG_SW (1 << 20)
|
||||
#define FLASH_BOR_OFF (0x0 << 16)
|
||||
#define FLASH_BOR_LEVEL_1 (0x8 << 16)
|
||||
#define FLASH_BOR_LEVEL_2 (0x9 << 16)
|
||||
#define FLASH_BOR_LEVEL_3 (0xa << 16)
|
||||
#define FLASH_BOR_LEVEL_4 (0xb << 16)
|
||||
#define FLASH_BOR_LEVEL_5 (0xc << 16)
|
||||
#define FLASH_RDPRT_LEVEL_0 (0xaa)
|
||||
#define FLASH_RDPRT_LEVEL_1 (0x00)
|
||||
#define FLASH_RDPRT_LEVEL_2 (0xcc)
|
||||
|
||||
/* --- Function prototypes ------------------------------------------------- */
|
||||
|
||||
|
||||
@@ -4,8 +4,8 @@ partname_doxygen: STM32L1
|
||||
irqs:
|
||||
- wwdg
|
||||
- pvd
|
||||
- tamper
|
||||
- rtc
|
||||
- tamper_stamp
|
||||
- rtc_wkup
|
||||
- flash
|
||||
- rcc
|
||||
- exti0
|
||||
@@ -44,6 +44,19 @@ irqs:
|
||||
- usart3
|
||||
- exti15_10
|
||||
- rtc_alarm
|
||||
- usb_wakeup
|
||||
- usb_fs_wakeup
|
||||
- tim6
|
||||
- tim7
|
||||
# below here is medium+/high density
|
||||
- sdio
|
||||
- tim5
|
||||
- spi3
|
||||
- uart4
|
||||
- uart5
|
||||
- dma2_ch1
|
||||
- dma2_ch2
|
||||
- dma2_ch3
|
||||
- dma2_ch4
|
||||
- dma2_ch5
|
||||
- aes
|
||||
- comp_acq
|
||||
@@ -47,7 +47,6 @@
|
||||
#define IWDG_BASE (PERIPH_BASE_APB1 + 0x3000)
|
||||
/* PERIPH_BASE_APB1 + 0x3400 (0x4000 3400 - 0x4000 37FF): Reserved */
|
||||
#define SPI2_BASE (PERIPH_BASE_APB1 + 0x3800)
|
||||
// datasheet has an error? here
|
||||
#define SPI3_BASE (PERIPH_BASE_APB1 + 0x3c00)
|
||||
/* PERIPH_BASE_APB1 + 0x4000 (0x4000 4000 - 0x4000 3FFF): Reserved */
|
||||
#define USART2_BASE (PERIPH_BASE_APB1 + 0x4400)
|
||||
@@ -61,6 +60,7 @@
|
||||
/* gap */
|
||||
#define POWER_CONTROL_BASE (PERIPH_BASE_APB1 + 0x7000)
|
||||
#define DAC_BASE (PERIPH_BASE_APB1 + 0x7400)
|
||||
#define OPAMP_BASE (PERIPH_BASE_APB1 + 0x7c5c)
|
||||
#define COMP_BASE (PERIPH_BASE_APB1 + 0x7c00)
|
||||
#define ROUTING_BASE (PERIPH_BASE_APB1 + 0x7c04)
|
||||
|
||||
@@ -85,13 +85,16 @@
|
||||
#define GPIO_PORT_D_BASE (PERIPH_BASE_AHB + 0x00c00)
|
||||
#define GPIO_PORT_E_BASE (PERIPH_BASE_AHB + 0x01000)
|
||||
#define GPIO_PORT_H_BASE (PERIPH_BASE_AHB + 0x01400)
|
||||
#define GPIO_PORT_F_BASE (PERIPH_BASE_AHB + 0x01800)
|
||||
#define GPIO_PORT_G_BASE (PERIPH_BASE_AHB + 0x01c00)
|
||||
/* gap */
|
||||
#define CRC_BASE (PERIPH_BASE_AHB + 0x03000)
|
||||
/* gap */
|
||||
#define RCC_BASE (PERIPH_BASE_AHB + 0x03800)
|
||||
#define FLASH_MEM_INTERFACE_BASE (PERIPH_BASE_AHB + 0x03c00)
|
||||
/* gap */
|
||||
#define DMA_BASE (PERIPH_BASE_AHB + 0x06000)
|
||||
#define DMA1_BASE (PERIPH_BASE_AHB + 0x06000)
|
||||
#define DMA2_BASE (PERIPH_BASE_AHB + 0x04000)
|
||||
|
||||
/* PPIB */
|
||||
#define DBGMCU_BASE (PPBI_BASE + 0x00042000)
|
||||
|
||||
@@ -1,3 +1,18 @@
|
||||
/** @defgroup pwr_defines PWR Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32L1xx Power Control</b>
|
||||
|
||||
@ingroup STM32L1xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2011 Stephen Caudle <scaudle@doceme.com>
|
||||
@author @htmlonly © @endhtmlonly 2012 Karl Palsson <karlp@tweak.net.au>
|
||||
|
||||
@date 1 July 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
@@ -18,10 +33,11 @@
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_PWR_L1_H
|
||||
#define LIBOPENCM3_PWR_L1_H
|
||||
#ifndef LIBOPENCM3_PWR_H
|
||||
#define LIBOPENCM3_PWR_H
|
||||
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/pwr_common_all.h>
|
||||
|
||||
/*
|
||||
* This file extends the common STM32 version with definitions only
|
||||
@@ -53,6 +69,9 @@
|
||||
/* ULP: Ultralow power mode */
|
||||
#define PWR_CR_ULP (1 << 9)
|
||||
|
||||
/* LPSDSR: Low-power deepsleep/sleep/low power run */
|
||||
#define PWR_CR_LPSDSR (1 << 0) /* masks common PWR_CR_LPDS */
|
||||
|
||||
/* --- PWR_CSR values ------------------------------------------------------- */
|
||||
|
||||
/* Bits [31:11]: Reserved */
|
||||
|
||||
@@ -46,7 +46,7 @@ LGPL License Terms @ref lgpl_license
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/cm3/common.h>
|
||||
#include <libopencm3/stm32/l1/pwr.h>
|
||||
#include <libopencm3/stm32/pwr.h>
|
||||
|
||||
/* --- RCC registers ------------------------------------------------------- */
|
||||
|
||||
@@ -82,11 +82,31 @@ LGPL License Terms @ref lgpl_license
|
||||
#define RCC_CR_RTCPRE_DIV2 0
|
||||
#define RCC_CR_RTCPRE_DIV4 1
|
||||
#define RCC_CR_RTCPRE_DIV8 2
|
||||
#define RCC_CR_RTCPRE_DIV18 3
|
||||
#define RCC_CR_RTCPRE_DIV16 3
|
||||
#define RCC_CR_RTCPRE_SHIFT 29
|
||||
#define RCC_CR_RTCPRE_MASK 0x3
|
||||
|
||||
/* --- RCC_ICSCR values ---------------------------------------------------- */
|
||||
|
||||
// TODO
|
||||
#define RCC_ICSCR_MSITRIM_SHIFT 24
|
||||
#define RCC_ICSCR_MSITRIM_MASK 0xff
|
||||
#define RCC_ICSCR_MSICAL_SHIFT 16
|
||||
#define RCC_ICSCR_MSICAL_MASK 0xff
|
||||
|
||||
#define RCC_ICSCR_MSIRANGE_SHIFT 13
|
||||
#define RCC_ICSCR_MSIRANGE_MASK 0x7
|
||||
#define RCC_ICSCR_MSIRANGE_65KHZ 0x0
|
||||
#define RCC_ICSCR_MSIRANGE_131KHZ 0x1
|
||||
#define RCC_ICSCR_MSIRANGE_262KHZ 0x2
|
||||
#define RCC_ICSCR_MSIRANGE_524KHZ 0x3
|
||||
#define RCC_ICSCR_MSIRANGE_1MHZ 0x4
|
||||
#define RCC_ICSCR_MSIRANGE_2MHZ 0x5
|
||||
#define RCC_ICSCR_MSIRANGE_4MHZ 0x6
|
||||
|
||||
#define RCC_ICSCR_HSITRIM_SHIFT 8
|
||||
#define RCC_ICSCR_HSITRIM_MASK 0x1f
|
||||
#define RCC_ICSCR_HSICAL_SHIFT 0
|
||||
#define RCC_ICSCR_HSICAL_MASK 0xff
|
||||
|
||||
/* --- RCC_CFGR values ----------------------------------------------------- */
|
||||
|
||||
@@ -347,7 +367,14 @@ LGPL License Terms @ref lgpl_license
|
||||
#define RCC_CSR_RMVF (1 << 24)
|
||||
#define RCC_CSR_RTCRST (1 << 23)
|
||||
#define RCC_CSR_RTCEN (1 << 22)
|
||||
/* RTCSEL[1:0] */
|
||||
#define RCC_CSR_RTCSEL_SHIFT (16)
|
||||
#define RCC_CSR_RTCSEL_MASK (0x3)
|
||||
#define RCC_CSR_RTCSEL_NONE (0x0)
|
||||
#define RCC_CSR_RTCSEL_LSE (0x1)
|
||||
#define RCC_CSR_RTCSEL_LSI (0x2)
|
||||
#define RCC_CSR_RTCSEL_HSI (0x3)
|
||||
#define RCC_CSR_LSECSSD (1 << 12)
|
||||
#define RCC_CSR_LSECSSON (1 << 11)
|
||||
#define RCC_CSR_LSEBYP (1 << 10)
|
||||
#define RCC_CSR_LSERDY (1 << 9)
|
||||
#define RCC_CSR_LSEON (1 << 8)
|
||||
@@ -365,16 +392,20 @@ typedef struct {
|
||||
vos_scale_t voltage_scale;
|
||||
uint32_t apb1_frequency;
|
||||
uint32_t apb2_frequency;
|
||||
uint8_t msi_range;
|
||||
} clock_scale_t;
|
||||
|
||||
typedef enum {
|
||||
CLOCK_VRANGE1_HSI_PLL_24MHZ,
|
||||
CLOCK_VRANGE1_HSI_PLL_32MHZ,
|
||||
CLOCK_VRANGE1_HSI_RAW_16MHZ,
|
||||
CLOCK_VRANGE1_END
|
||||
} clock_volt_range1_t;
|
||||
CLOCK_VRANGE1_HSI_RAW_4MHZ,
|
||||
CLOCK_VRANGE1_MSI_RAW_4MHZ,
|
||||
CLOCK_VRANGE1_MSI_RAW_2MHZ,
|
||||
CLOCK_CONFIG_END
|
||||
} clock_config_entry_t;
|
||||
|
||||
extern const clock_scale_t clock_vrange1_config[CLOCK_VRANGE1_END];
|
||||
extern const clock_scale_t clock_config[CLOCK_CONFIG_END];
|
||||
|
||||
|
||||
/* --- Variable definitions ------------------------------------------------ */
|
||||
@@ -413,6 +444,8 @@ void rcc_set_ppre1(u32 ppre1);
|
||||
void rcc_set_hpre(u32 hpre);
|
||||
void rcc_set_usbpre(u32 usbpre);
|
||||
u32 rcc_get_system_clock_source(int i);
|
||||
void rcc_rtc_select_clock(u32 clock);
|
||||
void rcc_clock_setup_msi(const clock_scale_t *clock);
|
||||
void rcc_clock_setup_hsi(const clock_scale_t *clock);
|
||||
void rcc_clock_setup_pll(const clock_scale_t *clock);
|
||||
void rcc_backupdomain_reset(void);
|
||||
|
||||
39
include/libopencm3/stm32/l1/rtc.h
Normal file
39
include/libopencm3/stm32/l1/rtc.h
Normal file
@@ -0,0 +1,39 @@
|
||||
/** @defgroup rtc_defines RTC Defines
|
||||
|
||||
@brief <b>Defined Constants and Types for the STM32L1xx RTC</b>
|
||||
|
||||
@ingroup STM32L1xx_defines
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2012 Ken Sarkies <ksarkies@internode.on.net>
|
||||
|
||||
@date 5 December 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#ifndef LIBOPENCM3_RTC_H
|
||||
#define LIBOPENCM3_RTC_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/stm32/common/rtc_common_bcd.h>
|
||||
|
||||
#endif
|
||||
@@ -1,22 +1,8 @@
|
||||
/** @defgroup STM32F_pwr_defines PWR Defines
|
||||
/* This provides unification of code over STM32F subfamilies */
|
||||
|
||||
@ingroup STM32F_defines
|
||||
|
||||
@brief <b>libopencm3 STM32F Power Control</b>
|
||||
|
||||
@version 1.0.0
|
||||
|
||||
@author @htmlonly © @endhtmlonly 2010 Thomas Otto <tommi@viadmin.org>
|
||||
|
||||
@date 17 August 2012
|
||||
|
||||
LGPL License Terms @ref lgpl_license
|
||||
*/
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* Copyright (C) 2010 Thomas Otto <tommi@viadmin.org>
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
@@ -31,101 +17,15 @@ LGPL License Terms @ref lgpl_license
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
/**@{*/
|
||||
|
||||
#ifndef LIBOPENCM3_PWR_H
|
||||
#define LIBOPENCM3_PWR_H
|
||||
|
||||
#include <libopencm3/stm32/memorymap.h>
|
||||
#include <libopencm3/cm3/common.h>
|
||||
|
||||
/* --- PWR registers ------------------------------------------------------- */
|
||||
|
||||
/* Power control register (PWR_CR) */
|
||||
#define PWR_CR MMIO32(POWER_CONTROL_BASE + 0x00)
|
||||
|
||||
/* Power control/status register (PWR_CSR) */
|
||||
#define PWR_CSR MMIO32(POWER_CONTROL_BASE + 0x04)
|
||||
|
||||
/* --- PWR_CR values ------------------------------------------------------- */
|
||||
|
||||
/* Bits [31:9]: Reserved, must be kept at reset value. */
|
||||
|
||||
/* DBP: Disable backup domain write protection */
|
||||
#define PWR_CR_DBP (1 << 8)
|
||||
|
||||
/* PLS[7:5]: PVD level selection */
|
||||
#define PWR_CR_PLS_LSB 5
|
||||
/** @defgroup pwr_pls PVD level selection
|
||||
@ingroup STM32F_pwr_defines
|
||||
|
||||
@{*/
|
||||
#define PWR_CR_PLS_2V2 (0x0 << PWR_CR_PLS_LSB)
|
||||
#define PWR_CR_PLS_2V3 (0x1 << PWR_CR_PLS_LSB)
|
||||
#define PWR_CR_PLS_2V4 (0x2 << PWR_CR_PLS_LSB)
|
||||
#define PWR_CR_PLS_2V5 (0x3 << PWR_CR_PLS_LSB)
|
||||
#define PWR_CR_PLS_2V6 (0x4 << PWR_CR_PLS_LSB)
|
||||
#define PWR_CR_PLS_2V7 (0x5 << PWR_CR_PLS_LSB)
|
||||
#define PWR_CR_PLS_2V8 (0x6 << PWR_CR_PLS_LSB)
|
||||
#define PWR_CR_PLS_2V9 (0x7 << PWR_CR_PLS_LSB)
|
||||
/**@}*/
|
||||
#define PWR_CR_PLS_MASK (0x7 << PWR_CR_PLS_LSB)
|
||||
|
||||
/* PVDE: Power voltage detector enable */
|
||||
#define PWR_CR_PVDE (1 << 4)
|
||||
|
||||
/* CSBF: Clear standby flag */
|
||||
#define PWR_CR_CSBF (1 << 3)
|
||||
|
||||
/* CWUF: Clear wakeup flag */
|
||||
#define PWR_CR_CWUF (1 << 2)
|
||||
|
||||
/* PDDS: Power down deepsleep */
|
||||
#define PWR_CR_PDDS (1 << 1)
|
||||
|
||||
/* LPDS: Low-power deepsleep */
|
||||
#define PWR_CR_LPDS (1 << 0)
|
||||
|
||||
/* --- PWR_CSR values ------------------------------------------------------ */
|
||||
|
||||
/* Bits [31:9]: Reserved, must be kept at reset value. */
|
||||
|
||||
/* EWUP: Enable WKUP pin */
|
||||
#define PWR_CSR_EWUP (1 << 8)
|
||||
|
||||
/* Bits [7:3]: Reserved, must be kept at reset value. */
|
||||
|
||||
/* PVDO: PVD output */
|
||||
#define PWR_CSR_PVDO (1 << 2)
|
||||
|
||||
/* SBF: Standby flag */
|
||||
#define PWR_CSR_SBF (1 << 1)
|
||||
|
||||
/* WUF: Wakeup flag */
|
||||
#define PWR_CSR_WUF (1 << 0)
|
||||
|
||||
/* --- PWR function prototypes ------------------------------------------- */
|
||||
|
||||
BEGIN_DECLS
|
||||
|
||||
void pwr_disable_backup_domain_write_protect(void);
|
||||
void pwr_enable_backup_domain_write_protect(void);
|
||||
void pwr_enable_power_voltage_detect(u32 pvd_level);
|
||||
void pwr_disable_power_voltage_detect(void);
|
||||
void pwr_clear_standby_flag(void);
|
||||
void pwr_clear_wakeup_flag(void);
|
||||
void pwr_set_standby_mode(void);
|
||||
void pwr_set_stop_mode(void);
|
||||
void pwr_voltage_regulator_on_in_stop(void);
|
||||
void pwr_voltage_regulator_low_power_in_stop(void);
|
||||
void pwr_enable_wakeup_pin(void);
|
||||
void pwr_disable_wakeup_pin(void);
|
||||
bool pwr_voltage_high(void);
|
||||
bool pwr_get_standby_flag(void);
|
||||
bool pwr_get_wakeup_flag(void);
|
||||
|
||||
END_DECLS
|
||||
|
||||
#if defined(STM32F1)
|
||||
# include <libopencm3/stm32/f1/pwr.h>
|
||||
#elif defined(STM32F2)
|
||||
# include <libopencm3/stm32/f2/pwr.h>
|
||||
#elif defined(STM32F4)
|
||||
# include <libopencm3/stm32/f4/pwr.h>
|
||||
#elif defined(STM32L1)
|
||||
# include <libopencm3/stm32/l1/pwr.h>
|
||||
#else
|
||||
# error "stm32 family not defined."
|
||||
#endif
|
||||
/**@}*/
|
||||
|
||||
|
||||
31
include/libopencm3/stm32/rtc.h
Normal file
31
include/libopencm3/stm32/rtc.h
Normal file
@@ -0,0 +1,31 @@
|
||||
/* This provides unification of code over STM32 subfamilies */
|
||||
|
||||
/*
|
||||
* This file is part of the libopencm3 project.
|
||||
*
|
||||
* This library is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU Lesser General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This library is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU Lesser General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU Lesser General Public License
|
||||
* along with this library. If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
|
||||
#if defined(STM32F1)
|
||||
# include <libopencm3/stm32/f1/rtc.h>
|
||||
#elif defined(STM32F2)
|
||||
# include <libopencm3/stm32/f2/rtc.h>
|
||||
#elif defined(STM32F4)
|
||||
# include <libopencm3/stm32/f4/rtc.h>
|
||||
#elif defined(STM32L1)
|
||||
# include <libopencm3/stm32/l1/rtc.h>
|
||||
#else
|
||||
# error "stm32 family not defined."
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user